3 files changed, 142 insertions, 3 deletions

diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index ba5a5b8c4681..2ec252be4ed9 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -61,6 +61,9 @@ mba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m,
                 struct rdt_resource *r);
 static void
 cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r);
+static void
+mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m,
+              struct rdt_resource *r);
 
 #define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].domains)
 
@@ -255,7 +258,7 @@ static inline bool rdt_get_mb_table(struct rdt_resource *r)
         return false;
 }
 
-static bool __get_mem_config(struct rdt_resource *r)
+static bool __get_mem_config_intel(struct rdt_resource *r)
 {
         union cpuid_0x10_3_eax eax;
         union cpuid_0x10_x_edx edx;
@@ -281,6 +284,30 @@ static bool __get_mem_config(struct rdt_resource *r)
         return true;
 }
 
+static bool __rdt_get_mem_config_amd(struct rdt_resource *r)
+{
+        union cpuid_0x10_3_eax eax;
+        union cpuid_0x10_x_edx edx;
+        u32 ebx, ecx;
+
+        cpuid_count(0x80000020, 1, &eax.full, &ebx, &ecx, &edx.full);
+        r->num_closid = edx.split.cos_max + 1;
+        r->default_ctrl = MAX_MBA_BW_AMD;
+
+        /* AMD does not use delay */
+        r->membw.delay_linear = false;
+
+        r->membw.min_bw = 0;
+        r->membw.bw_gran = 1;
+        /* Max value is 2048, Data width should be 4 in decimal */
+        r->data_width = 4;
+
+        r->alloc_capable = true;
+        r->alloc_enabled = true;
+
+        return true;
+}
+
 static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r)
 {
         union cpuid_0x10_1_eax eax;
@@ -340,6 +367,15 @@ static int get_cache_id(int cpu, int level)
         return -1;
 }
 
+static void
+mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r)
+{
+        unsigned int i;
+
+        for (i = m->low; i < m->high; i++)
+                wrmsrl(r->msr_base + i, d->ctrl_val[i]);
+}
+
 /*
  * Map the memory b/w percentage value to delay values
  * that can be written to QOS_MSRs.
@@ -793,8 +829,13 @@ static bool __init rdt_cpu_has(int flag)
 
 static __init bool get_mem_config(void)
 {
-        if (rdt_cpu_has(X86_FEATURE_MBA))
-                return __get_mem_config(&rdt_resources_all[RDT_RESOURCE_MBA]);
+        if (!rdt_cpu_has(X86_FEATURE_MBA))
+                return false;
+
+        if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
+                return __get_mem_config_intel(&rdt_resources_all[RDT_RESOURCE_MBA]);
+        else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+                return __rdt_get_mem_config_amd(&rdt_resources_all[RDT_RESOURCE_MBA]);
 
         return false;
 }
@@ -893,10 +934,32 @@ static __init void rdt_init_res_defs_intel(void)
         }
 }
 
+static __init void rdt_init_res_defs_amd(void)
+{
+        struct rdt_resource *r;
+
+        for_each_rdt_resource(r) {
+                if (r->rid == RDT_RESOURCE_L3 ||
+                    r->rid == RDT_RESOURCE_L3DATA ||
+                    r->rid == RDT_RESOURCE_L3CODE ||
+                    r->rid == RDT_RESOURCE_L2 ||
+                    r->rid == RDT_RESOURCE_L2DATA ||
+                    r->rid == RDT_RESOURCE_L2CODE)
+                        r->cbm_validate = cbm_validate_amd;
+                else if (r->rid == RDT_RESOURCE_MBA) {
+                        r->msr_base = MSR_IA32_MBA_BW_BASE;
+                        r->msr_update = mba_wrmsr_amd;
+                        r->parse_ctrlval = parse_bw_amd;
+                }
+        }
+}
+
 static __init void rdt_init_res_defs(void)
 {
         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
                 rdt_init_res_defs_intel();
+        else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+                rdt_init_res_defs_amd();
 }
 
 static enum cpuhp_state rdt_online;
diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
index bfd7bdf8a156..43ee3cee6494 100644
--- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
+++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
@@ -30,6 +30,53 @@
 
 /*
  * Check whether MBA bandwidth percentage value is correct. The value is
+ * checked against the minimum and maximum bandwidth values specified by
+ * the hardware. The allocated bandwidth percentage is rounded to the next
+ * control step available on the hardware.
+ */
+static bool bw_validate_amd(char *buf, unsigned long *data,
+                            struct rdt_resource *r)
+{
+        unsigned long bw;
+        int ret;
+
+        ret = kstrtoul(buf, 10, &bw);
+        if (ret) {
+                rdt_last_cmd_printf("Non-decimal digit in MB value %s\n", buf);
+                return false;
+        }
+
+        if (bw < r->membw.min_bw || bw > r->default_ctrl) {
+                rdt_last_cmd_printf("MB value %ld out of range [%d,%d]\n", bw,
+                                    r->membw.min_bw, r->default_ctrl);
+                return false;
+        }
+
+        *data = roundup(bw, (unsigned long)r->membw.bw_gran);
+        return true;
+}
+
+int parse_bw_amd(struct rdt_parse_data *data, struct rdt_resource *r,
+                 struct rdt_domain *d)
+{
+        unsigned long bw_val;
+
+        if (d->have_new_ctrl) {
+                rdt_last_cmd_printf("Duplicate domain %d\n", d->id);
+                return -EINVAL;
+        }
+
+        if (!bw_validate_amd(data->buf, &bw_val, r))
+                return -EINVAL;
+
+        d->new_ctrl = bw_val;
+        d->have_new_ctrl = true;
+
+        return 0;
+}
+
+/*
+ * Check whether MBA bandwidth percentage value is correct. The value is
  * checked against the minimum and max bandwidth values specified by the
  * hardware. The allocated bandwidth percentage is rounded to the next
  * control step available on the hardware.
@@ -124,6 +171,30 @@ bool cbm_validate_intel(char *buf, u32 *data, struct rdt_resource *r)
 }
 
 /*
+ * Check whether a cache bit mask is valid. AMD allows non-contiguous
+ * bitmasks
+ */
+bool cbm_validate_amd(char *buf, u32 *data, struct rdt_resource *r)
+{
+        unsigned long val;
+        int ret;
+
+        ret = kstrtoul(buf, 16, &val);
+        if (ret) {
+                rdt_last_cmd_printf("Non-hex character in the mask %s\n", buf);