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-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c6
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c20
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c16
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c57
5 files changed, 53 insertions, 48 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 9bf622e123b6..8cc0df9b534a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1167,9 +1167,9 @@ static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
1167 1167
1168 cz_ps->action = cz_current_ps->action; 1168 cz_ps->action = cz_current_ps->action;
1169 1169
1170 if ((force_high == false) && (cz_ps->action == FORCE_HIGH)) 1170 if (!force_high && (cz_ps->action == FORCE_HIGH))
1171 cz_ps->action = CANCEL_FORCE_HIGH; 1171 cz_ps->action = CANCEL_FORCE_HIGH;
1172 else if ((force_high == true) && (cz_ps->action != FORCE_HIGH)) 1172 else if (force_high && (cz_ps->action != FORCE_HIGH))
1173 cz_ps->action = FORCE_HIGH; 1173 cz_ps->action = FORCE_HIGH;
1174 else 1174 else
1175 cz_ps->action = DO_NOTHING; 1175 cz_ps->action = DO_NOTHING;
@@ -1656,7 +1656,7 @@ static void cz_hw_print_display_cfg(
1656 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend); 1656 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1657 uint32_t data = 0; 1657 uint32_t data = 0;
1658 1658
1659 if (hw_data->cc6_settings.cc6_setting_changed == true) { 1659 if (hw_data->cc6_settings.cc6_setting_changed) {
1660 1660
1661 hw_data->cc6_settings.cc6_setting_changed = false; 1661 hw_data->cc6_settings.cc6_setting_changed = false;
1662 1662
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index b3ef86eed0f9..c0c9cc32409a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -4389,8 +4389,9 @@ static int fiji_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4389 if ((0 == data->sclk_dpm_key_disabled) && 4389 if ((0 == data->sclk_dpm_key_disabled) &&
4390 (data->need_update_smu7_dpm_table & 4390 (data->need_update_smu7_dpm_table &
4391 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { 4391 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4392 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr), 4392 PP_ASSERT_WITH_CODE(fiji_is_dpm_running(hwmgr),
4393 "Trying to freeze SCLK DPM when DPM is disabled",); 4393 "Trying to freeze SCLK DPM when DPM is disabled",
4394 );
4394 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, 4395 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4395 PPSMC_MSG_SCLKDPM_FreezeLevel), 4396 PPSMC_MSG_SCLKDPM_FreezeLevel),
4396 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", 4397 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
@@ -4400,8 +4401,9 @@ static int fiji_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4400 if ((0 == data->mclk_dpm_key_disabled) && 4401 if ((0 == data->mclk_dpm_key_disabled) &&
4401 (data->need_update_smu7_dpm_table & 4402 (data->need_update_smu7_dpm_table &
4402 DPMTABLE_OD_UPDATE_MCLK)) { 4403 DPMTABLE_OD_UPDATE_MCLK)) {
4403 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr), 4404 PP_ASSERT_WITH_CODE(fiji_is_dpm_running(hwmgr),
4404 "Trying to freeze MCLK DPM when DPM is disabled",); 4405 "Trying to freeze MCLK DPM when DPM is disabled",
4406 );
4405 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, 4407 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4406 PPSMC_MSG_MCLKDPM_FreezeLevel), 4408 PPSMC_MSG_MCLKDPM_FreezeLevel),
4407 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", 4409 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
@@ -4850,8 +4852,9 @@ static int fiji_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4850 (data->need_update_smu7_dpm_table & 4852 (data->need_update_smu7_dpm_table &
4851 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { 4853 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4852 4854
4853 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr), 4855 PP_ASSERT_WITH_CODE(fiji_is_dpm_running(hwmgr),
4854 "Trying to Unfreeze SCLK DPM when DPM is disabled",); 4856 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4857 );
4855 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, 4858 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4856 PPSMC_MSG_SCLKDPM_UnfreezeLevel), 4859 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4857 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", 4860 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
@@ -4861,8 +4864,9 @@ static int fiji_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4861 if ((0 == data->mclk_dpm_key_disabled) && 4864 if ((0 == data->mclk_dpm_key_disabled) &&
4862 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 4865 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4863 4866
4864 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr), 4867 PP_ASSERT_WITH_CODE(fiji_is_dpm_running(hwmgr),
4865 "Trying to Unfreeze MCLK DPM when DPM is disabled",); 4868 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4869 );
4866 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, 4870 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4867 PPSMC_MSG_SCLKDPM_UnfreezeLevel), 4871 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4868 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", 4872 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 5afd94dfaa3a..417e525dc374 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -4149,8 +4149,8 @@ static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4149 if ((0 == data->sclk_dpm_key_disabled) && 4149 if ((0 == data->sclk_dpm_key_disabled) &&
4150 (data->need_update_smu7_dpm_table & 4150 (data->need_update_smu7_dpm_table &
4151 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { 4151 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4152 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr), 4152 PP_ASSERT_WITH_CODE(polaris10_is_dpm_running(hwmgr),
4153 "Trying to freeze SCLK DPM when DPM is disabled", 4153 "Trying to freeze SCLK DPM when DPM is disabled",
4154 ); 4154 );
4155 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, 4155 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4156 PPSMC_MSG_SCLKDPM_FreezeLevel), 4156 PPSMC_MSG_SCLKDPM_FreezeLevel),
@@ -4161,8 +4161,8 @@ static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4161 if ((0 == data->mclk_dpm_key_disabled) && 4161 if ((0 == data->mclk_dpm_key_disabled) &&
4162 (data->need_update_smu7_dpm_table & 4162 (data->need_update_smu7_dpm_table &
4163 DPMTABLE_OD_UPDATE_MCLK)) { 4163 DPMTABLE_OD_UPDATE_MCLK)) {
4164 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr), 4164 PP_ASSERT_WITH_CODE(polaris10_is_dpm_running(hwmgr),
4165 "Trying to freeze MCLK DPM when DPM is disabled", 4165 "Trying to freeze MCLK DPM when DPM is disabled",
4166 ); 4166 );
4167 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, 4167 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4168 PPSMC_MSG_MCLKDPM_FreezeLevel), 4168 PPSMC_MSG_MCLKDPM_FreezeLevel),
@@ -4552,8 +4552,8 @@ static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4552 (data->need_update_smu7_dpm_table & 4552 (data->need_update_smu7_dpm_table &
4553 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { 4553 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4554 4554
4555 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr), 4555 PP_ASSERT_WITH_CODE(polaris10_is_dpm_running(hwmgr),
4556 "Trying to Unfreeze SCLK DPM when DPM is disabled", 4556 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4557 ); 4557 );
4558 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, 4558 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4559 PPSMC_MSG_SCLKDPM_UnfreezeLevel), 4559 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
@@ -4564,8 +4564,8 @@ static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4564 if ((0 == data->mclk_dpm_key_disabled) && 4564 if ((0 == data->mclk_dpm_key_disabled) &&
4565 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 4565 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4566 4566
4567 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr), 4567 PP_ASSERT_WITH_CODE(polaris10_is_dpm_running(hwmgr),
4568 "Trying to Unfreeze MCLK DPM when DPM is disabled", 4568 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4569 ); 4569 );
4570 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, 4570 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4571 PPSMC_MSG_SCLKDPM_UnfreezeLevel), 4571 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
index a3c38bbd1e94..1944d289f846 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
@@ -66,7 +66,7 @@ int acpi_pcie_perf_request(void *device, uint8_t perf_req, bool advertise)
66 int result; 66 int result;
67 struct cgs_system_info info = {0}; 67 struct cgs_system_info info = {0};
68 68
69 if( 0 != acpi_atcs_notify_pcie_device_ready(device)) 69 if (acpi_atcs_notify_pcie_device_ready(device))
70 return -EINVAL; 70 return -EINVAL;
71 71
72 info.size = sizeof(struct cgs_system_info); 72 info.size = sizeof(struct cgs_system_info);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index 6e42b470d57d..306483d8036a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -571,7 +571,7 @@ int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
571 if (0 == data->sclk_dpm_key_disabled) { 571 if (0 == data->sclk_dpm_key_disabled) {
572 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ 572 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
573 PP_ASSERT_WITH_CODE( 573 PP_ASSERT_WITH_CODE(
574 (0 == tonga_is_dpm_running(hwmgr)), 574 !tonga_is_dpm_running(hwmgr),
575 "Trying to Disable SCLK DPM when DPM is disabled", 575 "Trying to Disable SCLK DPM when DPM is disabled",
576 return -1 576 return -1
577 ); 577 );
@@ -587,7 +587,7 @@ int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
587 if (0 == data->mclk_dpm_key_disabled) { 587 if (0 == data->mclk_dpm_key_disabled) {
588 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */ 588 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
589 PP_ASSERT_WITH_CODE( 589 PP_ASSERT_WITH_CODE(
590 (0 == tonga_is_dpm_running(hwmgr)), 590 !tonga_is_dpm_running(hwmgr),
591 "Trying to Disable MCLK DPM when DPM is disabled", 591 "Trying to Disable MCLK DPM when DPM is disabled",
592 return -1 592 return -1
593 ); 593 );
@@ -614,7 +614,7 @@ int tonga_stop_dpm(struct pp_hwmgr *hwmgr)
614 if (0 == data->pcie_dpm_key_disabled) { 614 if (0 == data->pcie_dpm_key_disabled) {
615 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ 615 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
616 PP_ASSERT_WITH_CODE( 616 PP_ASSERT_WITH_CODE(
617 (0 == tonga_is_dpm_running(hwmgr)), 617 !tonga_is_dpm_running(hwmgr),
618 "Trying to Disable PCIE DPM when DPM is disabled", 618 "Trying to Disable PCIE DPM when DPM is disabled",
619 return -1 619 return -1
620 ); 620 );
@@ -630,7 +630,7 @@ int tonga_stop_dpm(struct pp_hwmgr *hwmgr)
630 630
631 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ 631 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
632 PP_ASSERT_WITH_CODE( 632 PP_ASSERT_WITH_CODE(
633 (0 == tonga_is_dpm_running(hwmgr)), 633 !tonga_is_dpm_running(hwmgr),
634 "Trying to Disable Voltage CNTL when DPM is disabled", 634 "Trying to Disable Voltage CNTL when DPM is disabled",
635 return -1 635 return -1
636 ); 636 );
@@ -688,8 +688,9 @@ int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
688 uint32_t level_mask = 1 << n; 688 uint32_t level_mask = 1 << n;
689 689
690 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */ 690 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
691 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr), 691 PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr),
692 "Trying to force SCLK when DPM is disabled", return -1;); 692 "Trying to force SCLK when DPM is disabled",
693 return -1;);
693 if (0 == data->sclk_dpm_key_disabled) 694 if (0 == data->sclk_dpm_key_disabled)
694 return (0 == smum_send_msg_to_smc_with_parameter( 695 return (0 == smum_send_msg_to_smc_with_parameter(
695 hwmgr->smumgr, 696 hwmgr->smumgr,
@@ -712,8 +713,9 @@ int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
712 uint32_t level_mask = 1 << n; 713 uint32_t level_mask = 1 << n;
713 714
714 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */ 715 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
715 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr), 716 PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr),
716 "Trying to Force MCLK when DPM is disabled", return -1;); 717 "Trying to Force MCLK when DPM is disabled",
718 return -1;);
717 if (0 == data->mclk_dpm_key_disabled) 719 if (0 == data->mclk_dpm_key_disabled)
718 return (0 == smum_send_msg_to_smc_with_parameter( 720 return (0 == smum_send_msg_to_smc_with_parameter(
719 hwmgr->smumgr, 721 hwmgr->smumgr,
@@ -735,8 +737,9 @@ int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n)
735 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); 737 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
736 738
737 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ 739 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
738 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr), 740 PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr),
739 "Trying to Force PCIE level when DPM is disabled", return -1;); 741 "Trying to Force PCIE level when DPM is disabled",
742 return -1;);
740 if (0 == data->pcie_dpm_key_disabled) 743 if (0 == data->pcie_dpm_key_disabled)
741 return (0 == smum_send_msg_to_smc_with_parameter( 744 return (0 == smum_send_msg_to_smc_with_parameter(
742 hwmgr->smumgr, 745 hwmgr->smumgr,
@@ -955,7 +958,7 @@ int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr)
955 * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM, 958 * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
956 * whereas voltage control is a fundemental change that will not be disabled 959 * whereas voltage control is a fundemental change that will not be disabled
957 */ 960 */
958 return (0 == tonga_is_dpm_running(hwmgr) ? 0 : 1); 961 return (!tonga_is_dpm_running(hwmgr) ? 0 : 1);
959} 962}
960 963
961/** 964/**
@@ -968,7 +971,7 @@ int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr)
968{ 971{
969 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); 972 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
970 973
971 if (0 != tonga_is_dpm_running(hwmgr)) { 974 if (tonga_is_dpm_running(hwmgr)) {
972 /* If HW Virtualization is enabled, dpm_table_start will not have a valid value */ 975 /* If HW Virtualization is enabled, dpm_table_start will not have a valid value */
973 if (!data->dpm_table_start) { 976 if (!data->dpm_table_start) {
974 return 1; 977 return 1;
@@ -2042,7 +2045,7 @@ static int tonga_populate_single_memory_level(
2042 2045
2043 if ((data->mclk_stutter_mode_threshold != 0) && 2046 if ((data->mclk_stutter_mode_threshold != 0) &&
2044 (memory_clock <= data->mclk_stutter_mode_threshold) && 2047 (memory_clock <= data->mclk_stutter_mode_threshold) &&
2045 (data->is_uvd_enabled == 0) 2048 (!data->is_uvd_enabled)
2046 && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1) 2049 && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
2047 && (data->display_timing.num_existing_displays <= 2) 2050 && (data->display_timing.num_existing_displays <= 2)
2048 && (data->display_timing.num_existing_displays != 0)) 2051 && (data->display_timing.num_existing_displays != 0))
@@ -3134,7 +3137,7 @@ int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3134 3137
3135 if (0 == data->sclk_dpm_key_disabled) { 3138 if (0 == data->sclk_dpm_key_disabled) {
3136 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ 3139 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
3137 if (0 != tonga_is_dpm_running(hwmgr)) 3140 if (tonga_is_dpm_running(hwmgr))
3138 printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n"); 3141 printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
3139 3142
3140 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3143 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
@@ -3149,7 +3152,7 @@ int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3149 3152
3150 if (0 == data->mclk_dpm_key_disabled) { 3153 if (0 == data->mclk_dpm_key_disabled) {
3151 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/ 3154 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
3152 if (0 != tonga_is_dpm_running(hwmgr)) 3155 if (tonga_is_dpm_running(hwmgr))
3153 printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n"); 3156 printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
3154 3157
3155 if (0 != data->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3158 if (0 != data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
@@ -3335,9 +3338,9 @@ int tonga_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3335 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend); 3338 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3336 int result = 1; 3339 int result = 1;
3337 3340
3338 PP_ASSERT_WITH_CODE (0 == tonga_is_dpm_running(hwmgr), 3341 PP_ASSERT_WITH_CODE (!tonga_is_dpm_running(hwmgr),
3339 "Trying to Unforce DPM when DPM is disabled. Returning without sending SMC message.", 3342 "Trying to Unforce DPM when DPM is disabled. Returning without sending SMC message.",
3340 return result); 3343 return result);
3341 3344
3342 if (0 == data->pcie_dpm_key_disabled) { 3345 if (0 == data->pcie_dpm_key_disabled) {
3343 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc( 3346 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(
@@ -5308,9 +5311,8 @@ static int tonga_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5308 if ((0 == data->sclk_dpm_key_disabled) && 5311 if ((0 == data->sclk_dpm_key_disabled) &&
5309 (data->need_update_smu7_dpm_table & 5312 (data->need_update_smu7_dpm_table &
5310 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { 5313 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
5311 PP_ASSERT_WITH_CODE( 5314 PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr),
5312 0 == tonga_is_dpm_running(hwmgr), 5315 "Trying to freeze SCLK DPM when DPM is disabled",
5313 "Trying to freeze SCLK DPM when DPM is disabled",
5314 ); 5316 );
5315 PP_ASSERT_WITH_CODE( 5317 PP_ASSERT_WITH_CODE(
5316 0 == smum_send_msg_to_smc(hwmgr->smumgr, 5318 0 == smum_send_msg_to_smc(hwmgr->smumgr,
@@ -5322,8 +5324,8 @@ static int tonga_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5322 if ((0 == data->mclk_dpm_key_disabled) && 5324 if ((0 == data->mclk_dpm_key_disabled) &&
5323 (data->need_update_smu7_dpm_table & 5325 (data->need_update_smu7_dpm_table &
5324 DPMTABLE_OD_UPDATE_MCLK)) { 5326 DPMTABLE_OD_UPDATE_MCLK)) {
5325 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr), 5327 PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr),
5326 "Trying to freeze MCLK DPM when DPM is disabled", 5328 "Trying to freeze MCLK DPM when DPM is disabled",
5327 ); 5329 );
5328 PP_ASSERT_WITH_CODE( 5330 PP_ASSERT_WITH_CODE(
5329 0 == smum_send_msg_to_smc(hwmgr->smumgr, 5331 0 == smum_send_msg_to_smc(hwmgr->smumgr,
@@ -5625,8 +5627,8 @@ static int tonga_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5625 (data->need_update_smu7_dpm_table & 5627 (data->need_update_smu7_dpm_table &
5626 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { 5628 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
5627 5629
5628 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr), 5630 PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr),
5629 "Trying to Unfreeze SCLK DPM when DPM is disabled", 5631 "Trying to Unfreeze SCLK DPM when DPM is disabled",
5630 ); 5632 );
5631 PP_ASSERT_WITH_CODE( 5633 PP_ASSERT_WITH_CODE(
5632 0 == smum_send_msg_to_smc(hwmgr->smumgr, 5634 0 == smum_send_msg_to_smc(hwmgr->smumgr,
@@ -5638,9 +5640,8 @@ static int tonga_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5638 if ((0 == data->mclk_dpm_key_disabled) && 5640 if ((0 == data->mclk_dpm_key_disabled) &&
5639 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 5641 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
5640 5642
5641 PP_ASSERT_WITH_CODE( 5643 PP_ASSERT_WITH_CODE(!tonga_is_dpm_running(hwmgr),
5642 0 == tonga_is_dpm_running(hwmgr), 5644 "Trying to Unfreeze MCLK DPM when DPM is disabled",
5643 "Trying to Unfreeze MCLK DPM when DPM is disabled",
5644 ); 5645 );
5645 PP_ASSERT_WITH_CODE( 5646 PP_ASSERT_WITH_CODE(
5646 0 == smum_send_msg_to_smc(hwmgr->smumgr, 5647 0 == smum_send_msg_to_smc(hwmgr->smumgr,