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-rw-r--r--drivers/iio/Kconfig1
-rw-r--r--drivers/iio/Makefile1
-rw-r--r--drivers/staging/android/binder.c30
-rw-r--r--drivers/staging/comedi/drivers/8255_pci.c2
-rw-r--r--drivers/staging/comedi/drivers/amplc_dio200.c2
-rw-r--r--drivers/staging/comedi/drivers/amplc_pc236.c5
-rw-r--r--drivers/staging/comedi/drivers/amplc_pc263.c2
-rw-r--r--drivers/staging/comedi/drivers/das08.c2
-rw-r--r--drivers/staging/comedi/drivers/ni_daq_700.c2
-rw-r--r--drivers/staging/comedi/drivers/ni_labpc.c2
-rw-r--r--drivers/staging/iio/accel/adis16201_core.c24
-rw-r--r--drivers/staging/iio/accel/adis16203_core.c20
-rw-r--r--drivers/staging/iio/accel/adis16204_core.c22
-rw-r--r--drivers/staging/iio/accel/adis16209_core.c18
-rw-r--r--drivers/staging/iio/accel/adis16220_core.c19
-rw-r--r--drivers/staging/iio/accel/adis16240_core.c23
-rw-r--r--drivers/staging/iio/gyro/adis16260_core.c29
-rw-r--r--drivers/staging/iio/imu/adis16400.h2
-rw-r--r--drivers/staging/iio/imu/adis16400_core.c70
-rw-r--r--drivers/staging/ipack/bridges/tpci200.c1
-rw-r--r--drivers/staging/omapdrm/omap_gem.c4
-rw-r--r--drivers/staging/ramster/Kconfig1
-rw-r--r--drivers/staging/tidspbridge/core/tiomap3430.c37
-rw-r--r--drivers/staging/tidspbridge/hw/hw_mmu.c115
-rw-r--r--drivers/staging/tidspbridge/hw/hw_mmu.h31
-rw-r--r--drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h4
-rw-r--r--drivers/staging/tidspbridge/include/dspbridge/host_os.h4
-rw-r--r--drivers/staging/tidspbridge/rmgr/drv.c8
-rw-r--r--drivers/staging/tidspbridge/rmgr/node.c21
-rw-r--r--drivers/staging/zram/zram_drv.c12
-rw-r--r--include/linux/iio/iio.h16
31 files changed, 287 insertions, 243 deletions
diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig
index 6e3f143fc71d..fc937aca71fb 100644
--- a/drivers/iio/Kconfig
+++ b/drivers/iio/Kconfig
@@ -62,7 +62,6 @@ source "drivers/iio/frequency/Kconfig"
62source "drivers/iio/dac/Kconfig" 62source "drivers/iio/dac/Kconfig"
63source "drivers/iio/common/Kconfig" 63source "drivers/iio/common/Kconfig"
64source "drivers/iio/gyro/Kconfig" 64source "drivers/iio/gyro/Kconfig"
65source "drivers/iio/light/Kconfig"
66source "drivers/iio/magnetometer/Kconfig" 65source "drivers/iio/magnetometer/Kconfig"
67 66
68endif # IIO 67endif # IIO
diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile
index f7fa3c0867b4..761f2b65ac52 100644
--- a/drivers/iio/Makefile
+++ b/drivers/iio/Makefile
@@ -18,5 +18,4 @@ obj-y += frequency/
18obj-y += dac/ 18obj-y += dac/
19obj-y += common/ 19obj-y += common/
20obj-y += gyro/ 20obj-y += gyro/
21obj-y += light/
22obj-y += magnetometer/ 21obj-y += magnetometer/
diff --git a/drivers/staging/android/binder.c b/drivers/staging/android/binder.c
index 7b0ba92e7e46..5d4610babd8a 100644
--- a/drivers/staging/android/binder.c
+++ b/drivers/staging/android/binder.c
@@ -567,7 +567,7 @@ static int binder_update_page_range(struct binder_proc *proc, int allocate,
567 page = &proc->pages[(page_addr - proc->buffer) / PAGE_SIZE]; 567 page = &proc->pages[(page_addr - proc->buffer) / PAGE_SIZE];
568 568
569 BUG_ON(*page); 569 BUG_ON(*page);
570 *page = alloc_page(GFP_KERNEL | __GFP_ZERO); 570 *page = alloc_page(GFP_KERNEL | __GFP_HIGHMEM | __GFP_ZERO);
571 if (*page == NULL) { 571 if (*page == NULL) {
572 pr_err("binder: %d: binder_alloc_buf failed " 572 pr_err("binder: %d: binder_alloc_buf failed "
573 "for page at %p\n", proc->pid, page_addr); 573 "for page at %p\n", proc->pid, page_addr);
@@ -2419,14 +2419,38 @@ static void binder_release_work(struct list_head *list)
2419 struct binder_transaction *t; 2419 struct binder_transaction *t;
2420 2420
2421 t = container_of(w, struct binder_transaction, work); 2421 t = container_of(w, struct binder_transaction, work);
2422 if (t->buffer->target_node && !(t->flags & TF_ONE_WAY)) 2422 if (t->buffer->target_node &&
2423 !(t->flags & TF_ONE_WAY)) {
2423 binder_send_failed_reply(t, BR_DEAD_REPLY); 2424 binder_send_failed_reply(t, BR_DEAD_REPLY);
2425 } else {
2426 binder_debug(BINDER_DEBUG_DEAD_TRANSACTION,
2427 "binder: undelivered transaction %d\n",
2428 t->debug_id);
2429 t->buffer->transaction = NULL;
2430 kfree(t);
2431 binder_stats_deleted(BINDER_STAT_TRANSACTION);
2432 }
2424 } break; 2433 } break;
2425 case BINDER_WORK_TRANSACTION_COMPLETE: { 2434 case BINDER_WORK_TRANSACTION_COMPLETE: {
2435 binder_debug(BINDER_DEBUG_DEAD_TRANSACTION,
2436 "binder: undelivered TRANSACTION_COMPLETE\n");
2426 kfree(w); 2437 kfree(w);
2427 binder_stats_deleted(BINDER_STAT_TRANSACTION_COMPLETE); 2438 binder_stats_deleted(BINDER_STAT_TRANSACTION_COMPLETE);
2428 } break; 2439 } break;
2440 case BINDER_WORK_DEAD_BINDER_AND_CLEAR:
2441 case BINDER_WORK_CLEAR_DEATH_NOTIFICATION: {
2442 struct binder_ref_death *death;
2443
2444 death = container_of(w, struct binder_ref_death, work);
2445 binder_debug(BINDER_DEBUG_DEAD_TRANSACTION,
2446 "binder: undelivered death notification, %p\n",
2447 death->cookie);
2448 kfree(death);
2449 binder_stats_deleted(BINDER_STAT_DEATH);
2450 } break;
2429 default: 2451 default:
2452 pr_err("binder: unexpected work type, %d, not freed\n",
2453 w->type);
2430 break; 2454 break;
2431 } 2455 }
2432 } 2456 }
@@ -2899,6 +2923,7 @@ static void binder_deferred_release(struct binder_proc *proc)
2899 nodes++; 2923 nodes++;
2900 rb_erase(&node->rb_node, &proc->nodes); 2924 rb_erase(&node->rb_node, &proc->nodes);
2901 list_del_init(&node->work.entry); 2925 list_del_init(&node->work.entry);
2926 binder_release_work(&node->async_todo);
2902 if (hlist_empty(&node->refs)) { 2927 if (hlist_empty(&node->refs)) {
2903 kfree(node); 2928 kfree(node);
2904 binder_stats_deleted(BINDER_STAT_NODE); 2929 binder_stats_deleted(BINDER_STAT_NODE);
@@ -2937,6 +2962,7 @@ static void binder_deferred_release(struct binder_proc *proc)
2937 binder_delete_ref(ref); 2962 binder_delete_ref(ref);
2938 } 2963 }
2939 binder_release_work(&proc->todo); 2964 binder_release_work(&proc->todo);
2965 binder_release_work(&proc->delivered_death);
2940 buffers = 0; 2966 buffers = 0;
2941 2967
2942 while ((n = rb_first(&proc->allocated_buffers))) { 2968 while ((n = rb_first(&proc->allocated_buffers))) {
diff --git a/drivers/staging/comedi/drivers/8255_pci.c b/drivers/staging/comedi/drivers/8255_pci.c
index 7dff3c01dc29..d00aff6671df 100644
--- a/drivers/staging/comedi/drivers/8255_pci.c
+++ b/drivers/staging/comedi/drivers/8255_pci.c
@@ -289,6 +289,8 @@ static void pci_8255_detach(struct comedi_device *dev)
289 struct comedi_subdevice *s; 289 struct comedi_subdevice *s;
290 int i; 290 int i;
291 291
292 if (!board || !devpriv)
293 return;
292 if (dev->subdevices) { 294 if (dev->subdevices) {
293 for (i = 0; i < board->n_8255; i++) { 295 for (i = 0; i < board->n_8255; i++) {
294 s = &dev->subdevices[i]; 296 s = &dev->subdevices[i];
diff --git a/drivers/staging/comedi/drivers/amplc_dio200.c b/drivers/staging/comedi/drivers/amplc_dio200.c
index 08f305210a69..29eb52d11d2f 100644
--- a/drivers/staging/comedi/drivers/amplc_dio200.c
+++ b/drivers/staging/comedi/drivers/amplc_dio200.c
@@ -1410,6 +1410,8 @@ static void dio200_detach(struct comedi_device *dev)
1410 const struct dio200_layout_struct *layout; 1410 const struct dio200_layout_struct *layout;
1411 unsigned n; 1411 unsigned n;
1412 1412
1413 if (!thisboard)
1414 return;
1413 if (dev->irq) 1415 if (dev->irq)
1414 free_irq(dev->irq, dev); 1416 free_irq(dev->irq, dev);
1415 if (dev->subdevices) { 1417 if (dev->subdevices) {
diff --git a/drivers/staging/comedi/drivers/amplc_pc236.c b/drivers/staging/comedi/drivers/amplc_pc236.c
index eacb5e4735d7..4e4f3c15df87 100644
--- a/drivers/staging/comedi/drivers/amplc_pc236.c
+++ b/drivers/staging/comedi/drivers/amplc_pc236.c
@@ -573,9 +573,10 @@ static int __devinit pc236_attach_pci(struct comedi_device *dev,
573static void pc236_detach(struct comedi_device *dev) 573static void pc236_detach(struct comedi_device *dev)
574{ 574{
575 const struct pc236_board *thisboard = comedi_board(dev); 575 const struct pc236_board *thisboard = comedi_board(dev);
576 struct pc236_private *devpriv = dev->private;
577 576
578 if (devpriv) 577 if (!thisboard)
578 return;
579 if (dev->iobase)
579 pc236_intr_disable(dev); 580 pc236_intr_disable(dev);
580 if (dev->irq) 581 if (dev->irq)
581 free_irq(dev->irq, dev); 582 free_irq(dev->irq, dev);
diff --git a/drivers/staging/comedi/drivers/amplc_pc263.c b/drivers/staging/comedi/drivers/amplc_pc263.c
index 60830ccfb903..d0a4c441228b 100644
--- a/drivers/staging/comedi/drivers/amplc_pc263.c
+++ b/drivers/staging/comedi/drivers/amplc_pc263.c
@@ -323,6 +323,8 @@ static void pc263_detach(struct comedi_device *dev)
323{ 323{
324 const struct pc263_board *thisboard = comedi_board(dev); 324 const struct pc263_board *thisboard = comedi_board(dev);
325 325
326 if (!thisboard)
327 return;
326 if (is_isa_board(thisboard)) { 328 if (is_isa_board(thisboard)) {
327 if (dev->iobase) 329 if (dev->iobase)
328 release_region(dev->iobase, PC263_IO_SIZE); 330 release_region(dev->iobase, PC263_IO_SIZE);
diff --git a/drivers/staging/comedi/drivers/das08.c b/drivers/staging/comedi/drivers/das08.c
index 5fd21fa6c1c7..c304528cfb13 100644
--- a/drivers/staging/comedi/drivers/das08.c
+++ b/drivers/staging/comedi/drivers/das08.c
@@ -846,6 +846,8 @@ static void __maybe_unused das08_detach(struct comedi_device *dev)
846{ 846{
847 const struct das08_board_struct *thisboard = comedi_board(dev); 847 const struct das08_board_struct *thisboard = comedi_board(dev);
848 848
849 if (!thisboard)
850 return;
849 das08_common_detach(dev); 851 das08_common_detach(dev);
850 if (is_isa_board(thisboard)) { 852 if (is_isa_board(thisboard)) {
851 if (dev->iobase) 853 if (dev->iobase)
diff --git a/drivers/staging/comedi/drivers/ni_daq_700.c b/drivers/staging/comedi/drivers/ni_daq_700.c
index 2ba0ade45c64..68d7c6a5db7d 100644
--- a/drivers/staging/comedi/drivers/ni_daq_700.c
+++ b/drivers/staging/comedi/drivers/ni_daq_700.c
@@ -95,7 +95,7 @@ static int daq700_dio_insn_bits(struct comedi_device *dev,
95 } 95 }
96 96
97 data[1] = s->state & 0xff; 97 data[1] = s->state & 0xff;
98 data[1] |= inb(dev->iobase + DIO_R); 98 data[1] |= inb(dev->iobase + DIO_R) << 8;
99 99
100 return insn->n; 100 return insn->n;
101} 101}
diff --git a/drivers/staging/comedi/drivers/ni_labpc.c b/drivers/staging/comedi/drivers/ni_labpc.c
index 28b91a6c3789..b5a19a0863fb 100644
--- a/drivers/staging/comedi/drivers/ni_labpc.c
+++ b/drivers/staging/comedi/drivers/ni_labpc.c
@@ -772,6 +772,8 @@ void labpc_common_detach(struct comedi_device *dev)
772{ 772{
773 struct comedi_subdevice *s; 773 struct comedi_subdevice *s;
774 774
775 if (!thisboard)
776 return;
775 if (dev->subdevices) { 777 if (dev->subdevices) {
776 s = &dev->subdevices[2]; 778 s = &dev->subdevices[2];
777 subdev_8255_cleanup(dev, s); 779 subdev_8255_cleanup(dev, s);
diff --git a/drivers/staging/iio/accel/adis16201_core.c b/drivers/staging/iio/accel/adis16201_core.c
index 8e37d6e04277..b12ca68cd9e4 100644
--- a/drivers/staging/iio/accel/adis16201_core.c
+++ b/drivers/staging/iio/accel/adis16201_core.c
@@ -310,30 +310,32 @@ static int adis16201_read_raw(struct iio_dev *indio_dev,
310 case IIO_CHAN_INFO_SCALE: 310 case IIO_CHAN_INFO_SCALE:
311 switch (chan->type) { 311 switch (chan->type) {
312 case IIO_VOLTAGE: 312 case IIO_VOLTAGE:
313 *val = 0; 313 if (chan->channel == 0) {
314 if (chan->channel == 0) 314 *val = 1;
315 *val2 = 1220; 315 *val2 = 220000; /* 1.22 mV */
316 else 316 } else {
317 *val2 = 610; 317 *val = 0;
318 *val2 = 610000; /* 0.610 mV */
319 }
318 return IIO_VAL_INT_PLUS_MICRO; 320 return IIO_VAL_INT_PLUS_MICRO;
319 case IIO_TEMP: 321 case IIO_TEMP:
320 *val = 0; 322 *val = -470; /* 0.47 C */
321 *val2 = -470000; 323 *val2 = 0;
322 return IIO_VAL_INT_PLUS_MICRO; 324 return IIO_VAL_INT_PLUS_MICRO;
323 case IIO_ACCEL: 325 case IIO_ACCEL:
324 *val = 0; 326 *val = 0;
325 *val2 = 462500; 327 *val2 = IIO_G_TO_M_S_2(462400); /* 0.4624 mg */
326 return IIO_VAL_INT_PLUS_MICRO; 328 return IIO_VAL_INT_PLUS_NANO;
327 case IIO_INCLI: 329 case IIO_INCLI:
328 *val = 0; 330 *val = 0;
329 *val2 = 100000; 331 *val2 = 100000; /* 0.1 degree */
330 return IIO_VAL_INT_PLUS_MICRO; 332 return IIO_VAL_INT_PLUS_MICRO;
331 default: 333 default:
332 return -EINVAL; 334 return -EINVAL;
333 } 335 }
334 break; 336 break;
335 case IIO_CHAN_INFO_OFFSET: 337 case IIO_CHAN_INFO_OFFSET:
336 *val = 25; 338 *val = 25000 / -470 - 1278; /* 25 C = 1278 */
337 return IIO_VAL_INT; 339 return IIO_VAL_INT;
338 case IIO_CHAN_INFO_CALIBBIAS: 340 case IIO_CHAN_INFO_CALIBBIAS:
339 switch (chan->type) { 341 switch (chan->type) {
diff --git a/drivers/staging/iio/accel/adis16203_core.c b/drivers/staging/iio/accel/adis16203_core.c
index 002fa9dfc375..e7b3441115ae 100644
--- a/drivers/staging/iio/accel/adis16203_core.c
+++ b/drivers/staging/iio/accel/adis16203_core.c
@@ -316,25 +316,27 @@ static int adis16203_read_raw(struct iio_dev *indio_dev,
316 case IIO_CHAN_INFO_SCALE: 316 case IIO_CHAN_INFO_SCALE:
317 switch (chan->type) { 317 switch (chan->type) {
318 case IIO_VOLTAGE: 318 case IIO_VOLTAGE:
319 *val = 0; 319 if (chan->channel == 0) {
320 if (chan->channel == 0) 320 *val = 1;
321 *val2 = 1220; 321 *val2 = 220000; /* 1.22 mV */
322 else 322 } else {
323 *val2 = 610; 323 *val = 0;
324 *val2 = 610000; /* 0.61 mV */
325 }
324 return IIO_VAL_INT_PLUS_MICRO; 326 return IIO_VAL_INT_PLUS_MICRO;
325 case IIO_TEMP: 327 case IIO_TEMP:
326 *val = 0; 328 *val = -470; /* -0.47 C */
327 *val2 = -470000; 329 *val2 = 0;
328 return IIO_VAL_INT_PLUS_MICRO; 330 return IIO_VAL_INT_PLUS_MICRO;
329 case IIO_INCLI: 331 case IIO_INCLI:
330 *val = 0; 332 *val = 0;
331 *val2 = 25000; 333 *val2 = 25000; /* 0.025 degree */
332 return IIO_VAL_INT_PLUS_MICRO; 334 return IIO_VAL_INT_PLUS_MICRO;
333 default: 335 default:
334 return -EINVAL; 336 return -EINVAL;
335 } 337 }
336 case IIO_CHAN_INFO_OFFSET: 338 case IIO_CHAN_INFO_OFFSET:
337 *val = 25; 339 *val = 25000 / -470 - 1278; /* 25 C = 1278 */
338 return IIO_VAL_INT; 340 return IIO_VAL_INT;
339 case IIO_CHAN_INFO_CALIBBIAS: 341 case IIO_CHAN_INFO_CALIBBIAS:
340 bits = 14; 342 bits = 14;
diff --git a/drivers/staging/iio/accel/adis16204_core.c b/drivers/staging/iio/accel/adis16204_core.c
index 05bdb7c2c8e3..c6234c2f46aa 100644
--- a/drivers/staging/iio/accel/adis16204_core.c
+++ b/drivers/staging/iio/accel/adis16204_core.c
@@ -317,26 +317,28 @@ static int adis16204_read_raw(struct iio_dev *indio_dev,
317 case IIO_CHAN_INFO_SCALE: 317 case IIO_CHAN_INFO_SCALE:
318 switch (chan->type) { 318 switch (chan->type) {
319 case IIO_VOLTAGE: 319 case IIO_VOLTAGE:
320 *val = 0; 320 if (chan->channel == 0) {
321 if (chan->channel == 0) 321 *val = 1;
322 *val2 = 1220; 322 *val2 = 220000; /* 1.22 mV */
323 else 323 } else {
324 *val2 = 610; 324 *val = 0;
325 *val2 = 610000; /* 0.61 mV */
326 }
325 return IIO_VAL_INT_PLUS_MICRO; 327 return IIO_VAL_INT_PLUS_MICRO;
326 case IIO_TEMP: 328 case IIO_TEMP:
327 *val = 0; 329 *val = -470; /* 0.47 C */
328 *val2 = -470000; 330 *val2 = 0;
329 return IIO_VAL_INT_PLUS_MICRO; 331 return IIO_VAL_INT_PLUS_MICRO;
330 case IIO_ACCEL: 332 case IIO_ACCEL:
331 *val = 0; 333 *val = 0;
332 switch (chan->channel2) { 334 switch (chan->channel2) {
333 case IIO_MOD_X: 335 case IIO_MOD_X:
334 case IIO_MOD_ROOT_SUM_SQUARED_X_Y: 336 case IIO_MOD_ROOT_SUM_SQUARED_X_Y:
335 *val2 = 17125; 337 *val2 = IIO_G_TO_M_S_2(17125); /* 17.125 mg */
336 break; 338 break;
337 case IIO_MOD_Y: 339 case IIO_MOD_Y:
338 case IIO_MOD_Z: 340 case IIO_MOD_Z:
339 *val2 = 8407; 341 *val2 = IIO_G_TO_M_S_2(8407); /* 8.407 mg */
340 break; 342 break;
341 } 343 }
342 return IIO_VAL_INT_PLUS_MICRO; 344 return IIO_VAL_INT_PLUS_MICRO;
@@ -345,7 +347,7 @@ static int adis16204_read_raw(struct iio_dev *indio_dev,
345 } 347 }
346 break; 348 break;
347 case IIO_CHAN_INFO_OFFSET: 349 case IIO_CHAN_INFO_OFFSET:
348 *val = 25; 350 *val = 25000 / -470 - 1278; /* 25 C = 1278 */
349 return IIO_VAL_INT; 351 return IIO_VAL_INT;
350 case IIO_CHAN_INFO_CALIBBIAS: 352 case IIO_CHAN_INFO_CALIBBIAS:
351 case IIO_CHAN_INFO_PEAK: 353 case IIO_CHAN_INFO_PEAK:
diff --git a/drivers/staging/iio/accel/adis16209_core.c b/drivers/staging/iio/accel/adis16209_core.c
index b7333bfe0b2f..7ee974b45d7d 100644
--- a/drivers/staging/iio/accel/adis16209_core.c
+++ b/drivers/staging/iio/accel/adis16209_core.c
@@ -343,28 +343,29 @@ static int adis16209_read_raw(struct iio_dev *indio_dev,
343 case IIO_VOLTAGE: 343 case IIO_VOLTAGE:
344 *val = 0; 344 *val = 0;
345 if (chan->channel == 0) 345 if (chan->channel == 0)
346 *val2 = 305180; 346 *val2 = 305180; /* 0.30518 mV */
347 else 347 else
348 *val2 = 610500; 348 *val2 = 610500; /* 0.6105 mV */
349 return IIO_VAL_INT_PLUS_MICRO; 349 return IIO_VAL_INT_PLUS_MICRO;
350 case IIO_TEMP: 350 case IIO_TEMP:
351 *val = 0; 351 *val = -470; /* -0.47 C */
352 *val2 = -470000; 352 *val2 = 0;
353 return IIO_VAL_INT_PLUS_MICRO; 353 return IIO_VAL_INT_PLUS_MICRO;
354 case IIO_ACCEL: 354 case IIO_ACCEL:
355 *val = 0; 355 *val = 0;
356 *val2 = 2394; 356 *val2 = IIO_G_TO_M_S_2(244140); /* 0.244140 mg */
357 return IIO_VAL_INT_PLUS_MICRO; 357 return IIO_VAL_INT_PLUS_NANO;
358 case IIO_INCLI: 358 case IIO_INCLI:
359 case IIO_ROT:
359 *val = 0; 360 *val = 0;
360 *val2 = 436; 361 *val2 = 25000; /* 0.025 degree */
361 return IIO_VAL_INT_PLUS_MICRO; 362 return IIO_VAL_INT_PLUS_MICRO;
362 default: 363 default:
363 return -EINVAL; 364 return -EINVAL;
364 } 365 }
365 break; 366 break;
366 case IIO_CHAN_INFO_OFFSET: 367 case IIO_CHAN_INFO_OFFSET:
367 *val = 25; 368 *val = 25000 / -470 - 0x4FE; /* 25 C = 0x4FE */
368 return IIO_VAL_INT; 369 return IIO_VAL_INT;
369 case IIO_CHAN_INFO_CALIBBIAS: 370 case IIO_CHAN_INFO_CALIBBIAS:
370 switch (chan->type) { 371 switch (chan->type) {
@@ -491,6 +492,7 @@ static const struct iio_chan_spec adis16209_channels[] = {
491 .modified = 1, 492 .modified = 1,
492 .channel2 = IIO_MOD_X, 493 .channel2 = IIO_MOD_X,
493 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT, 494 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT,
495 IIO_CHAN_INFO_SCALE_SHARED_BIT,
494 .address = rot, 496 .address = rot,
495 .scan_index = ADIS16209_SCAN_ROT, 497 .scan_index = ADIS16209_SCAN_ROT,
496 .scan_type = { 498 .scan_type = {
diff --git a/drivers/staging/iio/accel/adis16220_core.c b/drivers/staging/iio/accel/adis16220_core.c
index c755089c7117..eaadd9df3f78 100644
--- a/drivers/staging/iio/accel/adis16220_core.c
+++ b/drivers/staging/iio/accel/adis16220_core.c
@@ -486,7 +486,7 @@ static int adis16220_read_raw(struct iio_dev *indio_dev,
486 break; 486 break;
487 case IIO_CHAN_INFO_OFFSET: 487 case IIO_CHAN_INFO_OFFSET:
488 if (chan->type == IIO_TEMP) { 488 if (chan->type == IIO_TEMP) {
489 *val = 25; 489 *val = 25000 / -470 - 1278; /* 25 C = 1278 */
490 return IIO_VAL_INT; 490 return IIO_VAL_INT;
491 } 491 }
492 addrind = 1; 492 addrind = 1;
@@ -495,19 +495,22 @@ static int adis16220_read_raw(struct iio_dev *indio_dev,
495 addrind = 2; 495 addrind = 2;
496 break; 496 break;
497 case IIO_CHAN_INFO_SCALE: 497 case IIO_CHAN_INFO_SCALE:
498 *val = 0;
499 switch (chan->type) { 498 switch (chan->type) {
500 case IIO_TEMP: 499 case IIO_TEMP:
501 *val2 = -470000; 500 *val = -470; /* -0.47 C */
501 *val2 = 0;
502 return IIO_VAL_INT_PLUS_MICRO; 502 return IIO_VAL_INT_PLUS_MICRO;
503 case IIO_ACCEL: 503 case IIO_ACCEL:
504 *val2 = 1887042; 504 *val2 = IIO_G_TO_M_S_2(19073); /* 19.073 g */
505 return IIO_VAL_INT_PLUS_MICRO; 505 return IIO_VAL_INT_PLUS_MICRO;
506 case IIO_VOLTAGE: 506 case IIO_VOLTAGE:
507 if (chan->channel == 0) 507 if (chan->channel == 0) {
508 *val2 = 0012221; 508 *val = 1;
509 else /* Should really be dependent on VDD */ 509 *val2 = 220700; /* 1.2207 mV */
510 *val2 = 305; 510 } else {
511 /* Should really be dependent on VDD */
512 *val2 = 305180; /* 305.18 uV */
513 }
511 return IIO_VAL_INT_PLUS_MICRO; 514 return IIO_VAL_INT_PLUS_MICRO;
512 default: 515 default:
513 return -EINVAL; 516 return -EINVAL;
diff --git a/drivers/staging/iio/accel/adis16240_core.c b/drivers/staging/iio/accel/adis16240_core.c
index 0fc26a49d681..35e093973d5c 100644
--- a/drivers/staging/iio/accel/adis16240_core.c
+++ b/drivers/staging/iio/accel/adis16240_core.c
@@ -373,30 +373,31 @@ static int adis16240_read_raw(struct iio_dev *indio_dev,
373 case IIO_CHAN_INFO_SCALE: 373 case IIO_CHAN_INFO_SCALE:
374 switch (chan->type) { 374 switch (chan->type) {
375 case IIO_VOLTAGE: 375 case IIO_VOLTAGE:
376 *val = 0; 376 if (chan->channel == 0) {
377 if (chan->channel == 0) 377 *val = 4;
378 *val2 = 4880; 378 *val2 = 880000; /* 4.88 mV */
379 else 379 return IIO_VAL_INT_PLUS_MICRO;
380 } else {
380 return -EINVAL; 381 return -EINVAL;
381 return IIO_VAL_INT_PLUS_MICRO; 382 }
382 case IIO_TEMP: 383 case IIO_TEMP:
383 *val = 0; 384 *val = 244; /* 0.244 C */
384 *val2 = 244000; 385 *val2 = 0;
385 return IIO_VAL_INT_PLUS_MICRO; 386 return IIO_VAL_INT_PLUS_MICRO;
386 case IIO_ACCEL: 387 case IIO_ACCEL:
387 *val = 0; 388 *val = 0;
388 *val2 = 504062; 389 *val2 = IIO_G_TO_M_S_2(51400); /* 51.4 mg */
389 return IIO_VAL_INT_PLUS_MICRO; 390 return IIO_VAL_INT_PLUS_MICRO;
390 default: 391 default:
391 return -EINVAL; 392 return -EINVAL;
392 } 393 }
393 break; 394 break;
394 case IIO_CHAN_INFO_PEAK_SCALE: 395 case IIO_CHAN_INFO_PEAK_SCALE:
395 *val = 6; 396 *val = 0;
396 *val2 = 629295; 397 *val2 = IIO_G_TO_M_S_2(51400); /* 51.4 mg */
397 return IIO_VAL_INT_PLUS_MICRO; 398 return IIO_VAL_INT_PLUS_MICRO;
398 case IIO_CHAN_INFO_OFFSET: 399 case IIO_CHAN_INFO_OFFSET:
399 *val = 25; 400 *val = 25000 / 244 - 0x133; /* 25 C = 0x133 */
400 return IIO_VAL_INT; 401 return IIO_VAL_INT;
401 case IIO_CHAN_INFO_CALIBBIAS: 402 case IIO_CHAN_INFO_CALIBBIAS:
402 bits = 10; 403 bits = 10;
diff --git a/drivers/staging/iio/gyro/adis16260_core.c b/drivers/staging/iio/gyro/adis16260_core.c
index 9571c03aa4cc..aa964a2d8290 100644
--- a/drivers/staging/iio/gyro/adis16260_core.c
+++ b/drivers/staging/iio/gyro/adis16260_core.c
@@ -498,28 +498,33 @@ static int adis16260_read_raw(struct iio_dev *indio_dev,
498 switch (chan->type) { 498 switch (chan->type) {
499 case IIO_ANGL_VEL: 499 case IIO_ANGL_VEL:
500 *val = 0; 500 *val = 0;
501 if (spi_get_device_id(st->us)->driver_data) 501 if (spi_get_device_id(st->us)->driver_data) {
502 *val2 = 320; 502 /* 0.01832 degree / sec */
503 else 503 *val2 = IIO_DEGREE_TO_RAD(18320);
504 *val2 = 1278; 504 } else {
505 /* 0.07326 degree / sec */
506 *val2 = IIO_DEGREE_TO_RAD(73260);
507 }
505 return IIO_VAL_INT_PLUS_MICRO; 508 return IIO_VAL_INT_PLUS_MICRO;
506 case IIO_VOLTAGE: 509 case IIO_VOLTAGE:
507 *val = 0; 510 if (chan->channel == 0) {
508 if (chan->channel == 0) 511 *val = 1;
509 *val2 = 18315; 512 *val2 = 831500; /* 1.8315 mV */
510 else 513 } else {
511 *val2 = 610500; 514 *val = 0;
515 *val2 = 610500; /* 610.5 uV */
516 }
512 return IIO_VAL_INT_PLUS_MICRO; 517 return IIO_VAL_INT_PLUS_MICRO;
513 case IIO_TEMP: 518 case IIO_TEMP:
514 *val = 0; 519 *val = 145;
515 *val2 = 145300; 520 *val2 = 300000; /* 0.1453 C */
516 return IIO_VAL_INT_PLUS_MICRO; 521 return IIO_VAL_INT_PLUS_MICRO;
517 default: 522 default:
518 return -EINVAL; 523 return -EINVAL;
519 } 524 }
520 break; 525 break;
521 case IIO_CHAN_INFO_OFFSET: 526 case IIO_CHAN_INFO_OFFSET:
522 *val = 25; 527 *val = 250000 / 1453; /* 25 C = 0x00 */
523 return IIO_VAL_INT; 528 return IIO_VAL_INT;
524 case IIO_CHAN_INFO_CALIBBIAS: 529 case IIO_CHAN_INFO_CALIBBIAS:
525 switch (chan->type) { 530 switch (chan->type) {
diff --git a/drivers/staging/iio/imu/adis16400.h b/drivers/staging/iio/imu/adis16400.h
index d59d7ac856a9..77c601da1846 100644
--- a/drivers/staging/iio/imu/adis16400.h
+++ b/drivers/staging/iio/imu/adis16400.h
@@ -139,6 +139,8 @@ struct adis16400_chip_info {
139 const long flags; 139 const long flags;
140 unsigned int gyro_scale_micro; 140 unsigned int gyro_scale_micro;
141 unsigned int accel_scale_micro; 141 unsigned int accel_scale_micro;
142 int temp_scale_nano;
143 int temp_offset;
142 unsigned long default_scan_mask; 144 unsigned long default_scan_mask;
143}; 145};
144 146
diff --git a/drivers/staging/iio/imu/adis16400_core.c b/drivers/staging/iio/imu/adis16400_core.c
index b302c9ba2712..3144a7b1e1c4 100644
--- a/drivers/staging/iio/imu/adis16400_core.c
+++ b/drivers/staging/iio/imu/adis16400_core.c
@@ -553,10 +553,13 @@ static int adis16400_read_raw(struct iio_dev *indio_dev,
553 return IIO_VAL_INT_PLUS_MICRO; 553 return IIO_VAL_INT_PLUS_MICRO;
554 case IIO_VOLTAGE: 554 case IIO_VOLTAGE:
555 *val = 0; 555 *val = 0;
556 if (chan->channel == 0) 556 if (chan->channel == 0) {
557 *val2 = 2418; 557 *val = 2;
558 else 558 *val2 = 418000; /* 2.418 mV */
559 *val2 = 806; 559 } else {
560 *val = 0;
561 *val2 = 805800; /* 805.8 uV */
562 }
560 return IIO_VAL_INT_PLUS_MICRO; 563 return IIO_VAL_INT_PLUS_MICRO;
561 case IIO_ACCEL: 564 case IIO_ACCEL:
562 *val = 0; 565 *val = 0;
@@ -564,11 +567,11 @@ static int adis16400_read_raw(struct iio_dev *indio_dev,
564 return IIO_VAL_INT_PLUS_MICRO; 567 return IIO_VAL_INT_PLUS_MICRO;
565 case IIO_MAGN: 568 case IIO_MAGN:
566 *val = 0; 569 *val = 0;
567 *val2 = 500; 570 *val2 = 500; /* 0.5 mgauss */
568 return IIO_VAL_INT_PLUS_MICRO; 571 return IIO_VAL_INT_PLUS_MICRO;
569 case IIO_TEMP: 572 case IIO_TEMP:
570 *val = 0; 573 *val = st->variant->temp_scale_nano / 1000000;
571 *val2 = 140000; 574 *val2 = (st->variant->temp_scale_nano % 1000000);
572 return IIO_VAL_INT_PLUS_MICRO; 575 return IIO_VAL_INT_PLUS_MICRO;
573 default: 576 default:
574 return -EINVAL; 577 return -EINVAL;
@@ -586,9 +589,8 @@ static int adis16400_read_raw(struct iio_dev *indio_dev,
586 return IIO_VAL_INT; 589 return IIO_VAL_INT;
587 case IIO_CHAN_INFO_OFFSET: 590 case IIO_CHAN_INFO_OFFSET:
588 /* currently only temperature */ 591 /* currently only temperature */
589 *val = 198; 592 *val = st->variant->temp_offset;
590 *val2 = 160000; 593 return IIO_VAL_INT;
591 return IIO_VAL_INT_PLUS_MICRO;
592 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 594 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
593 mutex_lock(&indio_dev->mlock); 595 mutex_lock(&indio_dev->mlock);
594 /* Need both the number of taps and the sampling frequency */ 596 /* Need both the number of taps and the sampling frequency */
@@ -1035,7 +1037,7 @@ static const struct iio_chan_spec adis16334_channels[] = {
1035 .indexed = 1, 1037 .indexed = 1,
1036 .channel = 0, 1038 .channel = 0,
1037 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | 1039 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
1038 IIO_CHAN_INFO_CALIBBIAS_SEPARATE_BIT | 1040 IIO_CHAN_INFO_OFFSET_SEPARATE_BIT |
1039 IIO_CHAN_INFO_SCALE_SHARED_BIT, 1041 IIO_CHAN_INFO_SCALE_SHARED_BIT,
1040 .address = temp0, 1042 .address = temp0,
1041 .scan_index = ADIS16400_SCAN_TEMP, 1043 .scan_index = ADIS16400_SCAN_TEMP,
@@ -1058,8 +1060,10 @@ static struct adis16400_chip_info adis16400_chips[] = {
1058 [ADIS16300] = { 1060 [ADIS16300] = {
1059 .channels = adis16300_channels, 1061 .channels = adis16300_channels,
1060 .num_channels = ARRAY_SIZE(adis16300_channels), 1062 .num_channels = ARRAY_SIZE(adis16300_channels),
1061 .gyro_scale_micro = 873, 1063 .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1062 .accel_scale_micro = 5884, 1064 .accel_scale_micro = 5884,
1065 .temp_scale_nano = 140000000, /* 0.14 C */
1066 .temp_offset = 25000000 / 140000, /* 25 C = 0x00 */
1063 .default_scan_mask = (1 << ADIS16400_SCAN_SUPPLY) | 1067 .default_scan_mask = (1 << ADIS16400_SCAN_SUPPLY) |
1064 (1 << ADIS16400_SCAN_GYRO_X) | (1 << ADIS16400_SCAN_ACC_X) | 1068 (1 << ADIS16400_SCAN_GYRO_X) | (1 << ADIS16400_SCAN_ACC_X) |
1065 (1 << ADIS16400_SCAN_ACC_Y) | (1 << ADIS16400_SCAN_ACC_Z) | 1069 (1 << ADIS16400_SCAN_ACC_Y) | (1 << ADIS16400_SCAN_ACC_Z) |
@@ -1070,8 +1074,10 @@ static struct adis16400_chip_info adis16400_chips[] = {
1070 [ADIS16334] = { 1074 [ADIS16334] = {
1071 .channels = adis16334_channels, 1075 .channels = adis16334_channels,
1072 .num_channels = ARRAY_SIZE(adis16334_channels), 1076 .num_channels = ARRAY_SIZE(adis16334_channels),
1073 .gyro_scale_micro = 873, 1077 .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1074 .accel_scale_micro = 981, 1078 .accel_scale_micro = IIO_G_TO_M_S_2(1000), /* 1 mg */
1079 .temp_scale_nano = 67850000, /* 0.06785 C */
1080 .temp_offset = 25000000 / 67850, /* 25 C = 0x00 */
1075 .default_scan_mask = (1 << ADIS16400_SCAN_GYRO_X) | 1081 .default_scan_mask = (1 << ADIS16400_SCAN_GYRO_X) |
1076 (1 << ADIS16400_SCAN_GYRO_Y) | (1 << ADIS16400_SCAN_GYRO_Z) | 1082 (1 << ADIS16400_SCAN_GYRO_Y) | (1 << ADIS16400_SCAN_GYRO_Z) |
1077 (1 << ADIS16400_SCAN_ACC_X) | (1 << ADIS16400_SCAN_ACC_Y) | 1083 (1 << ADIS16400_SCAN_ACC_X) | (1 << ADIS16400_SCAN_ACC_Y) |
@@ -1080,8 +1086,10 @@ static struct adis16400_chip_info adis16400_chips[] = {
1080 [ADIS16350] = { 1086 [ADIS16350] = {
1081 .channels = adis16350_channels, 1087 .channels = adis16350_channels,
1082 .num_channels = ARRAY_SIZE(adis16350_channels), 1088 .num_channels = ARRAY_SIZE(adis16350_channels),
1083 .gyro_scale_micro = 872664, 1089 .gyro_scale_micro = IIO_DEGREE_TO_RAD(73260), /* 0.07326 deg/s */
1084 .accel_scale_micro = 24732, 1090 .accel_scale_micro = IIO_G_TO_M_S_2(2522), /* 0.002522 g */
1091 .temp_scale_nano = 145300000, /* 0.1453 C */
1092 .temp_offset = 25000000 / 145300, /* 25 C = 0x00 */
1085 .default_scan_mask = 0x7FF, 1093 .default_scan_mask = 0x7FF,
1086 .flags = ADIS16400_NO_BURST, 1094 .flags = ADIS16400_NO_BURST,
1087 }, 1095 },
@@ -1090,8 +1098,10 @@ static struct adis16400_chip_info adis16400_chips[] = {
1090 .num_channels = ARRAY_SIZE(adis16350_channels), 1098 .num_channels = ARRAY_SIZE(adis16350_channels),
1091 .flags = ADIS16400_HAS_PROD_ID, 1099 .flags = ADIS16400_HAS_PROD_ID,
1092 .product_id = 0x3FE8, 1100 .product_id = 0x3FE8,
1093 .gyro_scale_micro = 1279, 1101 .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1094 .accel_scale_micro = 24732, 1102 .accel_scale_micro = IIO_G_TO_M_S_2(3333), /* 3.333 mg */
1103 .temp_scale_nano = 136000000, /* 0.136 C */
1104 .temp_offset = 25000000 / 136000, /* 25 C = 0x00 */
1095 .default_scan_mask = 0x7FF, 1105 .default_scan_mask = 0x7FF,
1096 }, 1106 },
1097 [ADIS16362] = { 1107 [ADIS16362] = {
@@ -1099,8 +1109,10 @@ static struct adis16400_chip_info adis16400_chips[] = {
1099 .num_channels = ARRAY_SIZE(adis16350_channels), 1109 .num_channels = ARRAY_SIZE(adis16350_channels),
1100 .flags = ADIS16400_HAS_PROD_ID, 1110 .flags = ADIS16400_HAS_PROD_ID,
1101 .product_id = 0x3FEA, 1111 .product_id = 0x3FEA,
1102 .gyro_scale_micro = 1279, 1112 .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1103 .accel_scale_micro = 24732, 1113 .accel_scale_micro = IIO_G_TO_M_S_2(333), /* 0.333 mg */
1114 .temp_scale_nano = 136000000, /* 0.136 C */
1115 .temp_offset = 25000000 / 136000, /* 25 C = 0x00 */
1104 .default_scan_mask = 0x7FF, 1116 .default_scan_mask = 0x7FF,
1105 }, 1117 },
1106 [ADIS16364] = { 1118 [ADIS16364] = {
@@ -1108,8 +1120,10 @@ static struct adis16400_chip_info adis16400_chips[] = {
1108 .num_channels = ARRAY_SIZE(adis16350_channels), 1120 .num_channels = ARRAY_SIZE(adis16350_channels),
1109 .flags = ADIS16400_HAS_PROD_ID, 1121 .flags = ADIS16400_HAS_PROD_ID,
1110 .product_id = 0x3FEC, 1122 .product_id = 0x3FEC,
1111 .gyro_scale_micro = 1279, 1123 .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1112 .accel_scale_micro = 24732, 1124 .accel_scale_micro = IIO_G_TO_M_S_2(1000), /* 1 mg */
1125 .temp_scale_nano = 136000000, /* 0.136 C */
1126 .temp_offset = 25000000 / 136000, /* 25 C = 0x00 */
1113 .default_scan_mask = 0x7FF, 1127 .default_scan_mask = 0x7FF,
1114 }, 1128 },
1115 [ADIS16365] = { 1129 [ADIS16365] = {
@@ -1117,8 +1131,10 @@ static struct adis16400_chip_info adis16400_chips[] = {
1117 .num_channels = ARRAY_SIZE(adis16350_channels), 1131 .num_channels = ARRAY_SIZE(adis16350_channels),
1118 .flags = ADIS16400_HAS_PROD_ID, 1132 .flags = ADIS16400_HAS_PROD_ID,
1119 .product_id = 0x3FED, 1133 .product_id = 0x3FED,
1120 .gyro_scale_micro = 1279, 1134 .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1121 .accel_scale_micro = 24732, 1135 .accel_scale_micro = IIO_G_TO_M_S_2(1000), /* 1 mg */
1136 .temp_scale_nano = 136000000, /* 0.136 C */
1137 .temp_offset = 25000000 / 136000, /* 25 C = 0x00 */
1122 .default_scan_mask = 0x7FF, 1138 .default_scan_mask = 0x7FF,
1123 }, 1139 },
1124 [ADIS16400] = { 1140 [ADIS16400] = {
@@ -1126,9 +1142,11 @@ static struct adis16400_chip_info adis16400_chips[] = {
1126 .num_channels = ARRAY_SIZE(adis16400_channels), 1142 .num_channels = ARRAY_SIZE(adis16400_channels),
1127 .flags = ADIS16400_HAS_PROD_ID, 1143 .flags = ADIS16400_HAS_PROD_ID,
1128 .product_id = 0x4015, 1144 .product_id = 0x4015,
1129 .gyro_scale_micro = 873, 1145 .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1130 .accel_scale_micro = 32656, 1146 .accel_scale_micro = IIO_G_TO_M_S_2(3333), /* 3.333 mg */
1131 .default_scan_mask = 0xFFF, 1147 .default_scan_mask = 0xFFF,
1148 .temp_scale_nano = 140000000, /* 0.14 C */
1149 .temp_offset = 25000000 / 140000, /* 25 C = 0x00 */
1132 } 1150 }
1133}; 1151};
1134 1152
diff --git a/drivers/staging/ipack/bridges/tpci200.c b/drivers/staging/ipack/bridges/tpci200.c
index bb8aa70281cd..46d6657280b8 100644
--- a/drivers/staging/ipack/bridges/tpci200.c
+++ b/drivers/staging/ipack/bridges/tpci200.c
@@ -12,6 +12,7 @@
12 */ 12 */
13 13
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/slab.h>
15#include "tpci200.h" 16#include "tpci200.h"
16 17
17static u16 tpci200_status_timeout[] = { 18static u16 tpci200_status_timeout[] = {
diff --git a/drivers/staging/omapdrm/omap_gem.c b/drivers/staging/omapdrm/omap_gem.c
index 3434e6ec0142..66e2c2f8a239 100644
--- a/drivers/staging/omapdrm/omap_gem.c
+++ b/drivers/staging/omapdrm/omap_gem.c
@@ -246,7 +246,7 @@ static int omap_gem_attach_pages(struct drm_gem_object *obj)
246 * DSS, GPU, etc. are not cache coherent: 246 * DSS, GPU, etc. are not cache coherent:
247 */ 247 */
248 if (omap_obj->flags & (OMAP_BO_WC|OMAP_BO_UNCACHED)) { 248 if (omap_obj->flags & (OMAP_BO_WC|OMAP_BO_UNCACHED)) {
249 addrs = kmalloc(npages * sizeof(addrs), GFP_KERNEL); 249 addrs = kmalloc(npages * sizeof(*addrs), GFP_KERNEL);
250 if (!addrs) { 250 if (!addrs) {
251 ret = -ENOMEM; 251 ret = -ENOMEM;
252 goto free_pages; 252 goto free_pages;
@@ -257,7 +257,7 @@ static int omap_gem_attach_pages(struct drm_gem_object *obj)
257 0, PAGE_SIZE, DMA_BIDIRECTIONAL); 257 0, PAGE_SIZE, DMA_BIDIRECTIONAL);
258 } 258 }
259 } else { 259 } else {
260 addrs = kzalloc(npages * sizeof(addrs), GFP_KERNEL); 260 addrs = kzalloc(npages * sizeof(*addrs), GFP_KERNEL);
261 if (!addrs) { 261 if (!addrs) {
262 ret = -ENOMEM; 262 ret = -ENOMEM;
263 goto free_pages; 263 goto free_pages;
diff --git a/drivers/staging/ramster/Kconfig b/drivers/staging/ramster/Kconfig
index 843c54101438..3abf6619dace 100644
--- a/drivers/staging/ramster/Kconfig
+++ b/drivers/staging/ramster/Kconfig
@@ -18,6 +18,7 @@ config ZCACHE2
18config RAMSTER 18config RAMSTER
19 bool "Cross-machine RAM capacity sharing, aka peer-to-peer tmem" 19 bool "Cross-machine RAM capacity sharing, aka peer-to-peer tmem"
20 depends on CONFIGFS_FS=y && SYSFS=y && !HIGHMEM && ZCACHE2=y 20 depends on CONFIGFS_FS=y && SYSFS=y && !HIGHMEM && ZCACHE2=y
21 depends on NET
21 # must ensure struct page is 8-byte aligned 22 # must ensure struct page is 8-byte aligned
22 select HAVE_ALIGNED_STRUCT_PAGE if !64_BIT 23 select HAVE_ALIGNED_STRUCT_PAGE if !64_BIT
23 default n 24 default n
diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c
index 066a3ceec65e..f619fb3c56d2 100644
--- a/drivers/staging/tidspbridge/core/tiomap3430.c
+++ b/drivers/staging/tidspbridge/core/tiomap3430.c
@@ -126,7 +126,8 @@ static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
126 u32 ul_num_bytes, 126 u32 ul_num_bytes,
127 struct hw_mmu_map_attrs_t *hw_attrs); 127 struct hw_mmu_map_attrs_t *hw_attrs);
128 128
129bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr); 129bool wait_for_start(struct bridge_dev_context *dev_context,
130 void __iomem *sync_addr);
130 131
131/* ----------------------------------- Globals */ 132/* ----------------------------------- Globals */
132 133
@@ -363,10 +364,11 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
363{ 364{
364 int status = 0; 365 int status = 0;
365 struct bridge_dev_context *dev_context = dev_ctxt; 366 struct bridge_dev_context *dev_context = dev_ctxt;
366 u32 dw_sync_addr = 0; 367 void __iomem *sync_addr;
367 u32 ul_shm_base; /* Gpp Phys SM base addr(byte) */ 368 u32 ul_shm_base; /* Gpp Phys SM base addr(byte) */
368 u32 ul_shm_base_virt; /* Dsp Virt SM base addr */ 369 u32 ul_shm_base_virt; /* Dsp Virt SM base addr */
369 u32 ul_tlb_base_virt; /* Base of MMU TLB entry */ 370 u32 ul_tlb_base_virt; /* Base of MMU TLB entry */
371 u32 shm_sync_pa;
370 /* Offset of shm_base_virt from tlb_base_virt */ 372 /* Offset of shm_base_virt from tlb_base_virt */
371 u32 ul_shm_offset_virt; 373 u32 ul_shm_offset_virt;
372 s32 entry_ndx; 374 s32 entry_ndx;
@@ -397,15 +399,22 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
397 /* Kernel logical address */ 399 /* Kernel logical address */
398 ul_shm_base = dev_context->atlb_entry[0].gpp_va + ul_shm_offset_virt; 400 ul_shm_base = dev_context->atlb_entry[0].gpp_va + ul_shm_offset_virt;
399 401
402 /* SHM physical sync address */
403 shm_sync_pa = dev_context->atlb_entry[0].gpp_pa + ul_shm_offset_virt +
404 SHMSYNCOFFSET;
405
400 /* 2nd wd is used as sync field */ 406 /* 2nd wd is used as sync field */
401 dw_sync_addr = ul_shm_base + SHMSYNCOFFSET; 407 sync_addr = ioremap(shm_sync_pa, SZ_32);
408 if (!sync_addr)
409 return -ENOMEM;
410
402 /* Write a signature into the shm base + offset; this will 411 /* Write a signature into the shm base + offset; this will
403 * get cleared when the DSP program starts. */ 412 * get cleared when the DSP program starts. */
404 if ((ul_shm_base_virt == 0) || (ul_shm_base == 0)) { 413 if ((ul_shm_base_virt == 0) || (ul_shm_base == 0)) {
405 pr_err("%s: Illegal SM base\n", __func__); 414 pr_err("%s: Illegal SM base\n", __func__);
406 status = -EPERM; 415 status = -EPERM;
407 } else 416 } else
408 __raw_writel(0xffffffff, dw_sync_addr); 417 __raw_writel(0xffffffff, sync_addr);
409 418
410 if (!status) { 419 if (!status) {
411 resources = dev_context->resources; 420 resources = dev_context->resources;
@@ -419,8 +428,10 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
419 * function is made available. 428 * function is made available.
420 */ 429 */
421 void __iomem *ctrl = ioremap(0x48002000, SZ_4K); 430 void __iomem *ctrl = ioremap(0x48002000, SZ_4K);
422 if (!ctrl) 431 if (!ctrl) {
432 iounmap(sync_addr);
423 return -ENOMEM; 433 return -ENOMEM;
434 }
424 435
425 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, 436 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
426 OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD, 437 OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD,
@@ -588,15 +599,15 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
588 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, 0, 599 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, 0,
589 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 600 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
590 601
591 dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", dw_sync_addr); 602 dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", *(u32 *)sync_addr);
592 dev_dbg(bridge, "DSP c_int00 Address = 0x%x\n", dsp_addr); 603 dev_dbg(bridge, "DSP c_int00 Address = 0x%x\n", dsp_addr);
593 if (dsp_debug) 604 if (dsp_debug)
594 while (__raw_readw(dw_sync_addr)) 605 while (__raw_readw(sync_addr))
595 ; 606 ;
596 607
597 /* Wait for DSP to clear word in shared memory */ 608 /* Wait for DSP to clear word in shared memory */
598 /* Read the Location */ 609 /* Read the Location */
599 if (!wait_for_start(dev_context, dw_sync_addr)) 610 if (!wait_for_start(dev_context, sync_addr))
600 status = -ETIMEDOUT; 611 status = -ETIMEDOUT;
601 612
602 dev_get_symbol(dev_context->dev_obj, "_WDT_enable", &wdt_en); 613 dev_get_symbol(dev_context->dev_obj, "_WDT_enable", &wdt_en);
@@ -612,7 +623,7 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
612 /* Write the synchronization bit to indicate the 623 /* Write the synchronization bit to indicate the
613 * completion of OPP table update to DSP 624 * completion of OPP table update to DSP
614 */ 625 */
615 __raw_writel(0XCAFECAFE, dw_sync_addr); 626 __raw_writel(0XCAFECAFE, sync_addr);
616 627
617 /* update board state */ 628 /* update board state */
618 dev_context->brd_state = BRD_RUNNING; 629 dev_context->brd_state = BRD_RUNNING;
@@ -621,6 +632,9 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
621 dev_context->brd_state = BRD_UNKNOWN; 632 dev_context->brd_state = BRD_UNKNOWN;
622 } 633 }
623 } 634 }
635
636 iounmap(sync_addr);
637
624 return status; 638 return status;
625} 639}
626 640
@@ -1796,12 +1810,13 @@ static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
1796 * ======== wait_for_start ======== 1810 * ======== wait_for_start ========
1797 * Wait for the singal from DSP that it has started, or time out. 1811 * Wait for the singal from DSP that it has started, or time out.
1798 */ 1812 */
1799bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr) 1813bool wait_for_start(struct bridge_dev_context *dev_context,
1814 void __iomem *sync_addr)
1800{ 1815{
1801 u16 timeout = TIHELEN_ACKTIMEOUT; 1816 u16 timeout = TIHELEN_ACKTIMEOUT;
1802 1817
1803 /* Wait for response from board */ 1818 /* Wait for response from board */
1804 while (__raw_readw(dw_sync_addr) && --timeout) 1819 while (__raw_readw(sync_addr) && --timeout)
1805 udelay(10); 1820 udelay(10);
1806 1821
1807 /* If timed out: return false */ 1822 /* If timed out: return false */
diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.c b/drivers/staging/tidspbridge/hw/hw_mmu.c
index 71cb82293649..50244a474178 100644
--- a/drivers/staging/tidspbridge/hw/hw_mmu.c
+++ b/drivers/staging/tidspbridge/hw/hw_mmu.c
@@ -48,37 +48,12 @@ enum hw_mmu_page_size_t {
48}; 48};
49 49
50/* 50/*
51 * FUNCTION : mmu_flush_entry
52 *
53 * INPUTS:
54 *
55 * Identifier : base_address
56 * Type : const u32
57 * Description : Base Address of instance of MMU module
58 *
59 * RETURNS:
60 *
61 * Type : hw_status
62 * Description : 0 -- No errors occurred
63 * RET_BAD_NULL_PARAM -- A Pointer
64 * Parameter was set to NULL
65 *
66 * PURPOSE: : Flush the TLB entry pointed by the
67 * lock counter register
68 * even if this entry is set protected
69 *
70 * METHOD: : Check the Input parameter and Flush a
71 * single entry in the TLB.
72 */
73static hw_status mmu_flush_entry(const void __iomem *base_address);
74
75/*
76 * FUNCTION : mmu_set_cam_entry 51 * FUNCTION : mmu_set_cam_entry
77 * 52 *
78 * INPUTS: 53 * INPUTS:
79 * 54 *
80 * Identifier : base_address 55 * Identifier : base_address
81 * TypE : const u32 56 * Type : void __iomem *
82 * Description : Base Address of instance of MMU module 57 * Description : Base Address of instance of MMU module
83 * 58 *
84 * Identifier : page_sz 59 * Identifier : page_sz
@@ -112,7 +87,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address);
112 * 87 *
113 * METHOD: : Check the Input parameters and set the CAM entry. 88 * METHOD: : Check the Input parameters and set the CAM entry.
114 */ 89 */
115static hw_status mmu_set_cam_entry(const void __iomem *base_address, 90static hw_status mmu_set_cam_entry(void __iomem *base_address,
116 const u32 page_sz, 91 const u32 page_sz,
117 const u32 preserved_bit, 92 const u32 preserved_bit,
118 const u32 valid_bit, 93 const u32 valid_bit,
@@ -124,7 +99,7 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address,
124 * INPUTS: 99 * INPUTS:
125 * 100 *
126 * Identifier : base_address 101 * Identifier : base_address
127 * Type : const u32 102 * Type : void __iomem *
128 * Description : Base Address of instance of MMU module 103 * Description : Base Address of instance of MMU module
129 * 104 *
130 * Identifier : physical_addr 105 * Identifier : physical_addr
@@ -157,7 +132,7 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address,
157 * 132 *
158 * METHOD: : Check the Input parameters and set the RAM entry. 133 * METHOD: : Check the Input parameters and set the RAM entry.
159 */ 134 */
160static hw_status mmu_set_ram_entry(const void __iomem *base_address, 135static hw_status mmu_set_ram_entry(void __iomem *base_address,
161 const u32 physical_addr, 136 const u32 physical_addr,
162 enum hw_endianism_t endianism, 137 enum hw_endianism_t endianism,
163 enum hw_element_size_t element_size, 138 enum hw_element_size_t element_size,
@@ -165,7 +140,7 @@ static hw_status mmu_set_ram_entry(const void __iomem *base_address,
165 140
166/* HW FUNCTIONS */ 141/* HW FUNCTIONS */
167 142
168hw_status hw_mmu_enable(const void __iomem *base_address) 143hw_status hw_mmu_enable(void __iomem *base_address)
169{ 144{
170 hw_status status = 0; 145 hw_status status = 0;
171 146
@@ -174,7 +149,7 @@ hw_status hw_mmu_enable(const void __iomem *base_address)
174 return status; 149 return status;
175} 150}
176 151
177hw_status hw_mmu_disable(const void __iomem *base_address) 152hw_status hw_mmu_disable(void __iomem *base_address)
178{ 153{
179 hw_status status = 0; 154 hw_status status = 0;
180 155
@@ -183,7 +158,7 @@ hw_status hw_mmu_disable(const void __iomem *base_address)
183 return status; 158 return status;
184} 159}
185 160
186hw_status hw_mmu_num_locked_set(const void __iomem *base_address, 161hw_status hw_mmu_num_locked_set(void __iomem *base_address,
187 u32 num_locked_entries) 162 u32 num_locked_entries)
188{ 163{
189 hw_status status = 0; 164 hw_status status = 0;
@@ -193,7 +168,7 @@ hw_status hw_mmu_num_locked_set(const void __iomem *base_address,
193 return status; 168 return status;
194} 169}
195 170
196hw_status hw_mmu_victim_num_set(const void __iomem *base_address, 171hw_status hw_mmu_victim_num_set(void __iomem *base_address,
197 u32 victim_entry_num) 172 u32 victim_entry_num)
198{ 173{
199 hw_status status = 0; 174 hw_status status = 0;
@@ -203,7 +178,7 @@ hw_status hw_mmu_victim_num_set(const void __iomem *base_address,
203 return status; 178 return status;
204} 179}
205 180
206hw_status hw_mmu_event_ack(const void __iomem *base_address, u32 irq_mask) 181hw_status hw_mmu_event_ack(void __iomem *base_address, u32 irq_mask)
207{ 182{
208 hw_status status = 0; 183 hw_status status = 0;
209 184
@@ -212,7 +187,7 @@ hw_status hw_mmu_event_ack(const void __iomem *base_address, u32 irq_mask)
212 return status; 187 return status;
213} 188}
214 189
215hw_status hw_mmu_event_disable(const void __iomem *base_address, u32 irq_mask) 190hw_status hw_mmu_event_disable(void __iomem *base_address, u32 irq_mask)
216{ 191{
217 hw_status status = 0; 192 hw_status status = 0;
218 u32 irq_reg; 193 u32 irq_reg;
@@ -224,7 +199,7 @@ hw_status hw_mmu_event_disable(const void __iomem *base_address, u32 irq_mask)
224 return status; 199 return status;
225} 200}
226 201
227hw_status hw_mmu_event_enable(const void __iomem *base_address, u32 irq_mask) 202hw_status hw_mmu_event_enable(void __iomem *base_address, u32 irq_mask)
228{ 203{
229 hw_status status = 0; 204 hw_status status = 0;
230 u32 irq_reg; 205 u32 irq_reg;
@@ -236,7 +211,7 @@ hw_status hw_mmu_event_enable(const void __iomem *base_address, u32 irq_mask)
236 return status; 211 return status;
237} 212}
238 213
239hw_status hw_mmu_event_status(const void __iomem *base_address, u32 *irq_mask) 214hw_status hw_mmu_event_status(void __iomem *base_address, u32 *irq_mask)
240{ 215{
241 hw_status status = 0; 216 hw_status status = 0;
242 217
@@ -245,7 +220,7 @@ hw_status hw_mmu_event_status(const void __iomem *base_address, u32 *irq_mask)
245 return status; 220 return status;
246} 221}
247 222
248hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, u32 *addr) 223hw_status hw_mmu_fault_addr_read(void __iomem *base_address, u32 *addr)
249{ 224{
250 hw_status status = 0; 225 hw_status status = 0;
251 226
@@ -255,7 +230,7 @@ hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, u32 *addr)
255 return status; 230 return status;
256} 231}
257 232
258hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 ttb_phys_addr) 233hw_status hw_mmu_ttb_set(void __iomem *base_address, u32 ttb_phys_addr)
259{ 234{
260 hw_status status = 0; 235 hw_status status = 0;
261 u32 load_ttb; 236 u32 load_ttb;
@@ -267,7 +242,7 @@ hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 ttb_phys_addr)
267 return status; 242 return status;
268} 243}
269 244
270hw_status hw_mmu_twl_enable(const void __iomem *base_address) 245hw_status hw_mmu_twl_enable(void __iomem *base_address)
271{ 246{
272 hw_status status = 0; 247 hw_status status = 0;
273 248
@@ -276,7 +251,7 @@ hw_status hw_mmu_twl_enable(const void __iomem *base_address)
276 return status; 251 return status;
277} 252}
278 253
279hw_status hw_mmu_twl_disable(const void __iomem *base_address) 254hw_status hw_mmu_twl_disable(void __iomem *base_address)
280{ 255{
281 hw_status status = 0; 256 hw_status status = 0;
282 257
@@ -285,45 +260,7 @@ hw_status hw_mmu_twl_disable(const void __iomem *base_address)
285 return status; 260 return status;
286} 261}
287 262
288hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtual_addr, 263hw_status hw_mmu_tlb_add(void __iomem *base_address,
289 u32 page_sz)
290{
291 hw_status status = 0;
292 u32 virtual_addr_tag;
293 enum hw_mmu_page_size_t pg_size_bits;
294
295 switch (page_sz) {
296 case HW_PAGE_SIZE4KB:
297 pg_size_bits = HW_MMU_SMALL_PAGE;
298 break;
299
300 case HW_PAGE_SIZE64KB:
301 pg_size_bits = HW_MMU_LARGE_PAGE;
302 break;
303
304 case HW_PAGE_SIZE1MB:
305 pg_size_bits = HW_MMU_SECTION;
306 break;
307
308 case HW_PAGE_SIZE16MB:
309 pg_size_bits = HW_MMU_SUPERSECTION;
310 break;
311
312 default:
313 return -EINVAL;
314 }
315
316 /* Generate the 20-bit tag from virtual address */
317 virtual_addr_tag = ((virtual_addr & MMU_ADDR_MASK) >> 12);
318
319 mmu_set_cam_entry(base_address, pg_size_bits, 0, 0, virtual_addr_tag);
320
321 mmu_flush_entry(base_address);
322
323 return status;
324}
325
326hw_status hw_mmu_tlb_add(const void __iomem *base_address,
327 u32 physical_addr, 264 u32 physical_addr,
328 u32 virtual_addr, 265 u32 virtual_addr,
329 u32 page_sz, 266 u32 page_sz,
@@ -503,20 +440,8 @@ hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, u32 virtual_addr, u32 page_size)
503 return status; 440 return status;
504} 441}
505 442
506/* mmu_flush_entry */
507static hw_status mmu_flush_entry(const void __iomem *base_address)
508{
509 hw_status status = 0;
510 u32 flush_entry_data = 0x1;
511
512 /* write values to register */
513 MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32(base_address, flush_entry_data);
514
515 return status;
516}
517
518/* mmu_set_cam_entry */ 443/* mmu_set_cam_entry */
519static hw_status mmu_set_cam_entry(const void __iomem *base_address, 444static hw_status mmu_set_cam_entry(void __iomem *base_address,
520 const u32 page_sz, 445 const u32 page_sz,
521 const u32 preserved_bit, 446 const u32 preserved_bit,
522 const u32 valid_bit, 447 const u32 valid_bit,
@@ -536,7 +461,7 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address,
536} 461}
537 462
538/* mmu_set_ram_entry */ 463/* mmu_set_ram_entry */
539static hw_status mmu_set_ram_entry(const void __iomem *base_address, 464static hw_status mmu_set_ram_entry(void __iomem *base_address,
540 const u32 physical_addr, 465 const u32 physical_addr,
541 enum hw_endianism_t endianism, 466 enum hw_endianism_t endianism,
542 enum hw_element_size_t element_size, 467 enum hw_element_size_t element_size,
@@ -556,7 +481,7 @@ static hw_status mmu_set_ram_entry(const void __iomem *base_address,
556 481
557} 482}
558 483
559void hw_mmu_tlb_flush_all(const void __iomem *base) 484void hw_mmu_tlb_flush_all(void __iomem *base)
560{ 485{
561 __raw_writel(1, base + MMU_GFLUSH); 486 __raw_writel(1, base + MMU_GFLUSH);
562} 487}
diff --git a/drivers/staging/tidspbridge/hw/hw_mmu.h b/drivers/staging/tidspbridge/hw/hw_mmu.h
index 1458a2c6027b..1c50bb36edfe 100644
--- a/drivers/staging/tidspbridge/hw/hw_mmu.h
+++ b/drivers/staging/tidspbridge/hw/hw_mmu.h
@@ -42,44 +42,41 @@ struct hw_mmu_map_attrs_t {
42 bool donotlockmpupage; 42 bool donotlockmpupage;
43}; 43};
44 44
45extern hw_status hw_mmu_enable(const void __iomem *base_address); 45extern hw_status hw_mmu_enable(void __iomem *base_address);
46 46
47extern hw_status hw_mmu_disable(const void __iomem *base_address); 47extern hw_status hw_mmu_disable(void __iomem *base_address);
48 48
49extern hw_status hw_mmu_num_locked_set(const void __iomem *base_address, 49extern hw_status hw_mmu_num_locked_set(void __iomem *base_address,
50 u32 num_locked_entries); 50 u32 num_locked_entries);
51 51
52extern hw_status hw_mmu_victim_num_set(const void __iomem *base_address, 52extern hw_status hw_mmu_victim_num_set(void __iomem *base_address,
53 u32 victim_entry_num); 53 u32 victim_entry_num);
54 54
55/* For MMU faults */ 55/* For MMU faults */
56extern hw_status hw_mmu_event_ack(const void __iomem *base_address, 56extern hw_status hw_mmu_event_ack(void __iomem *base_address,
57 u32 irq_mask); 57 u32 irq_mask);
58 58
59extern hw_status hw_mmu_event_disable(const void __iomem *base_address, 59extern hw_status hw_mmu_event_disable(void __iomem *base_address,
60 u32 irq_mask); 60 u32 irq_mask);
61 61
62extern hw_status hw_mmu_event_enable(const void __iomem *base_address, 62extern hw_status hw_mmu_event_enable(void __iomem *base_address,
63 u32 irq_mask); 63 u32 irq_mask);
64 64
65extern hw_status hw_mmu_event_status(const void __iomem *base_address, 65extern hw_status hw_mmu_event_status(void __iomem *base_address,
66 u32 *irq_mask); 66 u32 *irq_mask);
67 67
68extern hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, 68extern hw_status hw_mmu_fault_addr_read(void __iomem *base_address,
69 u32 *addr); 69 u32 *addr);
70 70
71/* Set the TT base address */ 71/* Set the TT base address */
72extern hw_status hw_mmu_ttb_set(const void __iomem *base_address, 72extern hw_status hw_mmu_ttb_set(void __iomem *base_address,
73 u32 ttb_phys_addr); 73 u32 ttb_phys_addr);
74 74
75extern hw_status hw_mmu_twl_enable(const void __iomem *base_address); 75extern hw_status hw_mmu_twl_enable(void __iomem *base_address);
76 76
77extern hw_status hw_mmu_twl_disable(const void __iomem *base_address); 77extern hw_status hw_mmu_twl_disable(void __iomem *base_address);
78 78
79extern hw_status hw_mmu_tlb_flush(const void __iomem *base_address, 79extern hw_status hw_mmu_tlb_add(void __iomem *base_address,
80 u32 virtual_addr, u32 page_sz);
81
82extern hw_status hw_mmu_tlb_add(const void __iomem *base_address,
83 u32 physical_addr, 80 u32 physical_addr,
84 u32 virtual_addr, 81 u32 virtual_addr,
85 u32 page_sz, 82 u32 page_sz,
@@ -97,7 +94,7 @@ extern hw_status hw_mmu_pte_set(const u32 pg_tbl_va,
97extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, 94extern hw_status hw_mmu_pte_clear(const u32 pg_tbl_va,
98 u32 virtual_addr, u32 page_size); 95 u32 virtual_addr, u32 page_size);
99 96
100void hw_mmu_tlb_flush_all(const void __iomem *base); 97void hw_mmu_tlb_flush_all(void __iomem *base);
101 98
102static inline u32 hw_mmu_pte_addr_l1(u32 l1_base, u32 va) 99static inline u32 hw_mmu_pte_addr_l1(u32 l1_base, u32 va)
103{ 100{
diff --git a/drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h b/drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h
index 60a278136bdf..b32c75673ab4 100644
--- a/drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h
+++ b/drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h
@@ -53,8 +53,8 @@ struct cfg_hostres {
53 u32 chnl_buf_size; 53 u32 chnl_buf_size;
54 u32 num_chnls; 54 u32 num_chnls;
55 void __iomem *per_base; 55 void __iomem *per_base;
56 u32 per_pm_base; 56 void __iomem *per_pm_base;
57 u32 core_pm_base; 57 void __iomem *core_pm_base;
58 void __iomem *dmmu_base; 58 void __iomem *dmmu_base;
59}; 59};
60 60
diff --git a/drivers/staging/tidspbridge/include/dspbridge/host_os.h b/drivers/staging/tidspbridge/include/dspbridge/host_os.h
index ed00d3da3205..5e2f4d82d925 100644
--- a/drivers/staging/tidspbridge/include/dspbridge/host_os.h
+++ b/drivers/staging/tidspbridge/include/dspbridge/host_os.h
@@ -47,8 +47,8 @@
47#include <asm/cacheflush.h> 47#include <asm/cacheflush.h>
48#include <linux/dma-mapping.h> 48#include <linux/dma-mapping.h>
49 49
50/* TODO -- Remove, once BP defines them */ 50/* TODO -- Remove, once omap-iommu is used */
51#define INT_DSP_MMU_IRQ 28 51#define INT_DSP_MMU_IRQ (28 + NR_IRQS)
52 52
53#define PRCM_VDD1 1 53#define PRCM_VDD1 1
54 54
diff --git a/drivers/staging/tidspbridge/rmgr/drv.c b/drivers/staging/tidspbridge/rmgr/drv.c
index 6795205b0155..db1da28cecba 100644
--- a/drivers/staging/tidspbridge/rmgr/drv.c
+++ b/drivers/staging/tidspbridge/rmgr/drv.c
@@ -667,10 +667,10 @@ int drv_request_bridge_res_dsp(void **phost_resources)
667 OMAP_DSP_MEM3_SIZE); 667 OMAP_DSP_MEM3_SIZE);
668 host_res->per_base = ioremap(OMAP_PER_CM_BASE, 668 host_res->per_base = ioremap(OMAP_PER_CM_BASE,
669 OMAP_PER_CM_SIZE); 669 OMAP_PER_CM_SIZE);
670 host_res->per_pm_base = (u32) ioremap(OMAP_PER_PRM_BASE, 670 host_res->per_pm_base = ioremap(OMAP_PER_PRM_BASE,
671 OMAP_PER_PRM_SIZE); 671 OMAP_PER_PRM_SIZE);
672 host_res->core_pm_base = (u32) ioremap(OMAP_CORE_PRM_BASE, 672 host_res->core_pm_base = ioremap(OMAP_CORE_PRM_BASE,
673 OMAP_CORE_PRM_SIZE); 673 OMAP_CORE_PRM_SIZE);
674 host_res->dmmu_base = ioremap(OMAP_DMMU_BASE, 674 host_res->dmmu_base = ioremap(OMAP_DMMU_BASE,
675 OMAP_DMMU_SIZE); 675 OMAP_DMMU_SIZE);
676 676
diff --git a/drivers/staging/tidspbridge/rmgr/node.c b/drivers/staging/tidspbridge/rmgr/node.c
index c2fc6137c770..294e9b40f516 100644
--- a/drivers/staging/tidspbridge/rmgr/node.c
+++ b/drivers/staging/tidspbridge/rmgr/node.c
@@ -304,8 +304,7 @@ int node_allocate(struct proc_object *hprocessor,
304 u32 pul_value; 304 u32 pul_value;
305 u32 dynext_base; 305 u32 dynext_base;
306 u32 off_set = 0; 306 u32 off_set = 0;
307 u32 ul_stack_seg_addr, ul_stack_seg_val; 307 u32 ul_stack_seg_val;
308 u32 ul_gpp_mem_base;
309 struct cfg_hostres *host_res; 308 struct cfg_hostres *host_res;
310 struct bridge_dev_context *pbridge_context; 309 struct bridge_dev_context *pbridge_context;
311 u32 mapped_addr = 0; 310 u32 mapped_addr = 0;
@@ -581,6 +580,9 @@ func_cont:
581 if (strcmp((char *) 580 if (strcmp((char *)
582 pnode->dcd_props.obj_data.node_obj.ndb_props. 581 pnode->dcd_props.obj_data.node_obj.ndb_props.
583 stack_seg_name, STACKSEGLABEL) == 0) { 582 stack_seg_name, STACKSEGLABEL) == 0) {
583 void __iomem *stack_seg;
584 u32 stack_seg_pa;
585
584 status = 586 status =
585 hnode_mgr->nldr_fxns. 587 hnode_mgr->nldr_fxns.
586 get_fxn_addr(pnode->nldr_node_obj, "DYNEXT_BEG", 588 get_fxn_addr(pnode->nldr_node_obj, "DYNEXT_BEG",
@@ -608,14 +610,21 @@ func_cont:
608 goto func_end; 610 goto func_end;
609 } 611 }
610 612
611 ul_gpp_mem_base = (u32) host_res->mem_base[1];
612 off_set = pul_value - dynext_base; 613 off_set = pul_value - dynext_base;
613 ul_stack_seg_addr = ul_gpp_mem_base + off_set; 614 stack_seg_pa = host_res->mem_phys[1] + off_set;
614 ul_stack_seg_val = readl(ul_stack_seg_addr); 615 stack_seg = ioremap(stack_seg_pa, SZ_32);
616 if (!stack_seg) {
617 status = -ENOMEM;
618 goto func_end;
619 }
620
621 ul_stack_seg_val = readl(stack_seg);
622
623 iounmap(stack_seg);
615 624
616 dev_dbg(bridge, "%s: StackSegVal = 0x%x, StackSegAddr =" 625 dev_dbg(bridge, "%s: StackSegVal = 0x%x, StackSegAddr ="
617 " 0x%x\n", __func__, ul_stack_seg_val, 626 " 0x%x\n", __func__, ul_stack_seg_val,
618 ul_stack_seg_addr); 627 host_res->mem_base[1] + off_set);
619 628
620 pnode->create_args.asa.task_arg_obj.stack_seg = 629 pnode->create_args.asa.task_arg_obj.stack_seg =
621 ul_stack_seg_val; 630 ul_stack_seg_val;
diff --git a/drivers/staging/zram/zram_drv.c b/drivers/staging/zram/zram_drv.c
index 653b074035f7..6edefde23722 100644
--- a/drivers/staging/zram/zram_drv.c
+++ b/drivers/staging/zram/zram_drv.c
@@ -223,8 +223,13 @@ static int zram_bvec_read(struct zram *zram, struct bio_vec *bvec,
223 cmem = zs_map_object(zram->mem_pool, zram->table[index].handle, 223 cmem = zs_map_object(zram->mem_pool, zram->table[index].handle,
224 ZS_MM_RO); 224 ZS_MM_RO);
225 225
226 ret = lzo1x_decompress_safe(cmem, zram->table[index].size, 226 if (zram->table[index].size == PAGE_SIZE) {
227 memcpy(uncmem, cmem, PAGE_SIZE);
228 ret = LZO_E_OK;
229 } else {
230 ret = lzo1x_decompress_safe(cmem, zram->table[index].size,
227 uncmem, &clen); 231 uncmem, &clen);
232 }
228 233
229 if (is_partial_io(bvec)) { 234 if (is_partial_io(bvec)) {
230 memcpy(user_mem + bvec->bv_offset, uncmem + offset, 235 memcpy(user_mem + bvec->bv_offset, uncmem + offset,
@@ -342,8 +347,11 @@ static int zram_bvec_write(struct zram *zram, struct bio_vec *bvec, u32 index,
342 goto out; 347 goto out;
343 } 348 }
344 349
345 if (unlikely(clen > max_zpage_size)) 350 if (unlikely(clen > max_zpage_size)) {
346 zram_stat_inc(&zram->stats.bad_compress); 351 zram_stat_inc(&zram->stats.bad_compress);
352 src = uncmem;
353 clen = PAGE_SIZE;
354 }
347 355
348 handle = zs_malloc(zram->mem_pool, clen); 356 handle = zs_malloc(zram->mem_pool, clen);
349 if (!handle) { 357 if (!handle) {
diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h
index c0ae76ac4e0b..7806c24e5bc8 100644
--- a/include/linux/iio/iio.h
+++ b/include/linux/iio/iio.h
@@ -618,4 +618,20 @@ static inline struct dentry *iio_get_debugfs_dentry(struct iio_dev *indio_dev)
618}; 618};
619#endif 619#endif
620 620
621/**
622 * IIO_DEGREE_TO_RAD() - Convert degree to rad
623 * @deg: A value in degree
624 *
625 * Returns the given value converted from degree to rad
626 */
627#define IIO_DEGREE_TO_RAD(deg) (((deg) * 314159ULL + 9000000ULL) / 18000000ULL)
628
629/**
630 * IIO_G_TO_M_S_2() - Convert g to meter / second**2
631 * @g: A value in g
632 *
633 * Returns the given value converted from g to meter / second**2
634 */
635#define IIO_G_TO_M_S_2(g) ((g) * 980665ULL / 100000ULL)
636
621#endif /* _INDUSTRIAL_IO_H_ */ 637#endif /* _INDUSTRIAL_IO_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-28 00:34:11 -0400