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-rw-r--r--Documentation/ABI/testing/sysfs-bus-i2c-devices-pca954x20
-rw-r--r--Documentation/devicetree/bindings/eeprom/at24.txt1
-rw-r--r--Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt17
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-designware.txt9
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt5
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-riic.txt5
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-stm32.txt37
-rw-r--r--Documentation/i2c/busses/i2c-amd-mp223
-rw-r--r--Documentation/i2c/busses/i2c-piix42
-rw-r--r--MAINTAINERS13
-rw-r--r--drivers/i2c/algos/i2c-algo-bit.c22
-rw-r--r--drivers/i2c/busses/Kconfig25
-rw-r--r--drivers/i2c/busses/Makefile5
-rw-r--r--drivers/i2c/busses/i2c-amd-mp2-pci.c483
-rw-r--r--drivers/i2c/busses/i2c-amd-mp2-plat.c367
-rw-r--r--drivers/i2c/busses/i2c-amd-mp2.h219
-rw-r--r--drivers/i2c/busses/i2c-at91-core.c376
-rw-r--r--drivers/i2c/busses/i2c-at91-master.c (renamed from drivers/i2c/busses/i2c-at91.c)480
-rw-r--r--drivers/i2c/busses/i2c-at91-slave.c143
-rw-r--r--drivers/i2c/busses/i2c-at91.h174
-rw-r--r--drivers/i2c/busses/i2c-axxia.c57
-rw-r--r--drivers/i2c/busses/i2c-bcm-iproc.c764
-rw-r--r--drivers/i2c/busses/i2c-brcmstb.c1
-rw-r--r--drivers/i2c/busses/i2c-designware-common.c18
-rw-r--r--drivers/i2c/busses/i2c-designware-core.h2
-rw-r--r--drivers/i2c/busses/i2c-designware-platdrv.c5
-rw-r--r--drivers/i2c/busses/i2c-gpio.c2
-rw-r--r--drivers/i2c/busses/i2c-imx-lpi2c.c11
-rw-r--r--drivers/i2c/busses/i2c-isch.c1
-rw-r--r--drivers/i2c/busses/i2c-mt65xx.c255
-rw-r--r--drivers/i2c/busses/i2c-nomadik.c3
-rw-r--r--drivers/i2c/busses/i2c-ocores.c16
-rw-r--r--drivers/i2c/busses/i2c-omap.c76
-rw-r--r--drivers/i2c/busses/i2c-piix4.c15
-rw-r--r--drivers/i2c/busses/i2c-rcar.c30
-rw-r--r--drivers/i2c/busses/i2c-riic.c43
-rw-r--r--drivers/i2c/busses/i2c-stm32f7.c4
-rw-r--r--drivers/i2c/busses/i2c-stu300.c25
-rw-r--r--drivers/i2c/busses/i2c-tegra-bpmp.c25
-rw-r--r--drivers/i2c/i2c-core-base.c23
-rw-r--r--drivers/i2c/i2c-core-smbus.c29
-rw-r--r--drivers/i2c/i2c-core.h36
-rw-r--r--drivers/i2c/i2c-mux.c6
-rw-r--r--drivers/i2c/muxes/i2c-demux-pinctrl.c6
-rw-r--r--drivers/i2c/muxes/i2c-mux-pca9541.c8
-rw-r--r--drivers/i2c/muxes/i2c-mux-pca954x.c106
-rw-r--r--include/linux/i2c-algo-bit.h1
-rw-r--r--include/linux/i2c.h41
-rw-r--r--include/linux/platform_data/pca954x.h48
49 files changed, 3151 insertions, 932 deletions
diff --git a/Documentation/ABI/testing/sysfs-bus-i2c-devices-pca954x b/Documentation/ABI/testing/sysfs-bus-i2c-devices-pca954x
new file mode 100644
index 000000000000..0b0de8cd0d13
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-i2c-devices-pca954x
@@ -0,0 +1,20 @@
1What: /sys/bus/i2c/.../idle_state
2Date: January 2019
3KernelVersion: 5.2
4Contact: Robert Shearman <robert.shearman@att.com>
5Description:
6 Value that exists only for mux devices that can be
7 written to control the behaviour of the multiplexer on
8 idle. Possible values:
9 -2 - disconnect on idle, i.e. deselect the last used
10 channel, which is useful when there is a device
11 with an address that conflicts with another
12 device on another mux on the same parent bus.
13 -1 - leave the mux as-is, which is the most optimal
14 setting in terms of I2C operations and is the
15 default mode.
16 0..<nchans> - set the mux to a predetermined channel,
17 which is useful if there is one channel that is
18 used almost always, and you want to reduce the
19 latency for normal operations after rare
20 transactions on other channels
diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt
index 0e456bbc1213..22aead844d0f 100644
--- a/Documentation/devicetree/bindings/eeprom/at24.txt
+++ b/Documentation/devicetree/bindings/eeprom/at24.txt
@@ -50,6 +50,7 @@ Required properties:
50 50
51 "nxp,se97b" - the fallback is "atmel,24c02", 51 "nxp,se97b" - the fallback is "atmel,24c02",
52 "renesas,r1ex24002" - the fallback is "atmel,24c02" 52 "renesas,r1ex24002" - the fallback is "atmel,24c02"
53 "renesas,r1ex24016" - the fallback is "atmel,24c16"
53 "renesas,r1ex24128" - the fallback is "atmel,24c128" 54 "renesas,r1ex24128" - the fallback is "atmel,24c128"
54 "rohm,br24t01" - the fallback is "atmel,24c01" 55 "rohm,br24t01" - the fallback is "atmel,24c01"
55 56
diff --git a/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt b/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt
index 81f982ccca31..d12cc33cca6c 100644
--- a/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt
@@ -3,15 +3,12 @@ Broadcom iProc I2C controller
3Required properties: 3Required properties:
4 4
5- compatible: 5- compatible:
6 Must be "brcm,iproc-i2c" 6 Must be "brcm,iproc-i2c" or "brcm,iproc-nic-i2c"
7 7
8- reg: 8- reg:
9 Define the base and range of the I/O address space that contain the iProc 9 Define the base and range of the I/O address space that contain the iProc
10 I2C controller registers 10 I2C controller registers
11 11
12- interrupts:
13 Should contain the I2C interrupt
14
15- clock-frequency: 12- clock-frequency:
16 This is the I2C bus clock. Need to be either 100000 or 400000 13 This is the I2C bus clock. Need to be either 100000 or 400000
17 14
@@ -21,6 +18,18 @@ Required properties:
21- #size-cells: 18- #size-cells:
22 Always 0 19 Always 0
23 20
21Optional properties:
22
23- interrupts:
24 Should contain the I2C interrupt. For certain revisions of the I2C
25 controller, I2C interrupt is unwired to the interrupt controller. In such
26 case, this property should be left unspecified, and driver will fall back
27 to polling mode
28
29- brcm,ape-hsls-addr-mask:
30 Required for "brcm,iproc-nic-i2c". Host view of address mask into the
31 'APE' co-processor. Value must be unsigned, 32-bit
32
24Example: 33Example:
25 i2c0: i2c@18008000 { 34 i2c0: i2c@18008000 {
26 compatible = "brcm,iproc-i2c"; 35 compatible = "brcm,iproc-i2c";
diff --git a/Documentation/devicetree/bindings/i2c/i2c-designware.txt b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
index 3e4bcc2fb6f7..08be4d3846e5 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-designware.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
@@ -6,12 +6,21 @@ Required properties :
6 or "mscc,ocelot-i2c" with "snps,designware-i2c" for fallback 6 or "mscc,ocelot-i2c" with "snps,designware-i2c" for fallback
7 - reg : Offset and length of the register set for the device 7 - reg : Offset and length of the register set for the device
8 - interrupts : <IRQ> where IRQ is the interrupt number. 8 - interrupts : <IRQ> where IRQ is the interrupt number.
9 - clocks : phandles for the clocks, see the description of clock-names below.
10 The phandle for the "ic_clk" clock is required. The phandle for the "pclk"
11 clock is optional. If a single clock is specified but no clock-name, it is
12 the "ic_clk" clock. If both clocks are listed, the "ic_clk" must be first.
9 13
10Recommended properties : 14Recommended properties :
11 15
12 - clock-frequency : desired I2C bus clock frequency in Hz. 16 - clock-frequency : desired I2C bus clock frequency in Hz.
13 17
14Optional properties : 18Optional properties :
19
20 - clock-names : Contains the names of the clocks:
21 "ic_clk", for the core clock used to generate the external I2C clock.
22 "pclk", the interface clock, required for register access.
23
15 - reg : for "mscc,ocelot-i2c", a second register set to configure the SDA hold 24 - reg : for "mscc,ocelot-i2c", a second register set to configure the SDA hold
16 time, named ICPU_CFG:TWI_DELAY in the datasheet. 25 time, named ICPU_CFG:TWI_DELAY in the datasheet.
17 26
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
index ee4c32454198..68f6d73a8b73 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
@@ -12,13 +12,16 @@ Required properties:
12 "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623 12 "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
13 "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629 13 "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
14 "mediatek,mt8173-i2c": for MediaTek MT8173 14 "mediatek,mt8173-i2c": for MediaTek MT8173
15 "mediatek,mt8183-i2c": for MediaTek MT8183
16 "mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
15 - reg: physical base address of the controller and dma base, length of memory 17 - reg: physical base address of the controller and dma base, length of memory
16 mapped region. 18 mapped region.
17 - interrupts: interrupt number to the cpu. 19 - interrupts: interrupt number to the cpu.
18 - clock-div: the fixed value for frequency divider of clock source in i2c 20 - clock-div: the fixed value for frequency divider of clock source in i2c
19 module. Each IC may be different. 21 module. Each IC may be different.
20 - clocks: clock name from clock manager 22 - clocks: clock name from clock manager
21 - clock-names: Must include "main" and "dma", if enable have-pmic need include 23 - clock-names: Must include "main" and "dma", "arb" is for multi-master that
24 one bus has more than two i2c controllers, if enable have-pmic need include
22 "pmic" extra. 25 "pmic" extra.
23 26
24Optional properties: 27Optional properties:
diff --git a/Documentation/devicetree/bindings/i2c/i2c-riic.txt b/Documentation/devicetree/bindings/i2c/i2c-riic.txt
index 0bcc4716c319..e26fe3ad86a9 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-riic.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-riic.txt
@@ -1,7 +1,10 @@
1Device tree configuration for Renesas RIIC driver 1Device tree configuration for Renesas RIIC driver
2 2
3Required properties: 3Required properties:
4- compatible : "renesas,riic-<soctype>". "renesas,riic-rz" as fallback 4- compatible :
5 "renesas,riic-r7s72100" if the device is a part of a R7S72100 SoC.
6 "renesas,riic-r7s9210" if the device is a part of a R7S9210 SoC.
7 "renesas,riic-rz" for a generic RZ/A compatible device.
5- reg : address start and address range size of device 8- reg : address start and address range size of device
6- interrupts : 8 interrupts (TEI, RI, TI, SPI, STI, NAKI, ALI, TMOI) 9- interrupts : 8 interrupts (TEI, RI, TI, SPI, STI, NAKI, ALI, TMOI)
7- clock-frequency : frequency of bus clock in Hz 10- clock-frequency : frequency of bus clock in Hz
diff --git a/Documentation/devicetree/bindings/i2c/i2c-stm32.txt b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt
index 69240e189b01..f334738f7a35 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-stm32.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt
@@ -1,11 +1,11 @@
1* I2C controller embedded in STMicroelectronics STM32 I2C platform 1* I2C controller embedded in STMicroelectronics STM32 I2C platform
2 2
3Required properties : 3Required properties:
4- compatible : Must be one of the following 4- compatible: Must be one of the following
5 - "st,stm32f4-i2c" 5 - "st,stm32f4-i2c"
6 - "st,stm32f7-i2c" 6 - "st,stm32f7-i2c"
7- reg : Offset and length of the register set for the device 7- reg: Offset and length of the register set for the device
8- interrupts : Must contain the interrupt id for I2C event and then the 8- interrupts: Must contain the interrupt id for I2C event and then the
9 interrupt id for I2C error. 9 interrupt id for I2C error.
10- resets: Must contain the phandle to the reset controller. 10- resets: Must contain the phandle to the reset controller.
11- clocks: Must contain the input clock of the I2C instance. 11- clocks: Must contain the input clock of the I2C instance.
@@ -14,25 +14,26 @@ Required properties :
14- #address-cells = <1>; 14- #address-cells = <1>;
15- #size-cells = <0>; 15- #size-cells = <0>;
16 16
17Optional properties : 17Optional properties:
18- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified, 18- clock-frequency: Desired I2C bus clock frequency in Hz. If not specified,
19 the default 100 kHz frequency will be used. 19 the default 100 kHz frequency will be used.
20 For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are 20 For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are
21 100000 and 400000. 21 100000 and 400000.
22 For STM32F7 SoC, Standard-mode, Fast-mode and Fast-mode Plus are supported, 22 For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode, Fast-mode and Fast-mode
23 possible values are 100000, 400000 and 1000000. 23 Plus are supported, possible values are 100000, 400000 and 1000000.
24- i2c-scl-rising-time-ns : Only for STM32F7, I2C SCL Rising time for the board 24- i2c-scl-rising-time-ns: I2C SCL Rising time for the board (default: 25)
25 (default: 25) 25 For STM32F7, STM32H7 and STM32MP1 only.
26- i2c-scl-falling-time-ns : Only for STM32F7, I2C SCL Falling time for the board 26- i2c-scl-falling-time-ns: I2C SCL Falling time for the board (default: 10)
27 (default: 10) 27 For STM32F7, STM32H7 and STM32MP1 only.
28 I2C Timings are derived from these 2 values 28 I2C Timings are derived from these 2 values
29- st,syscfg-fmp: Only for STM32F7, use to set Fast Mode Plus bit within SYSCFG 29- st,syscfg-fmp: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode
30 whether Fast Mode Plus speed is selected by slave. 30 Plus speed is selected by slave.
31 1st cell : phandle to syscfg 31 1st cell: phandle to syscfg
32 2nd cell : register offset within SYSCFG 32 2nd cell: register offset within SYSCFG
33 3rd cell : register bitmask for FMP bit 33 3rd cell: register bitmask for FMP bit
34 For STM32F7, STM32H7 and STM32MP1 only.
34 35
35Example : 36Example:
36 37
37 i2c@40005400 { 38 i2c@40005400 {
38 compatible = "st,stm32f4-i2c"; 39 compatible = "st,stm32f4-i2c";
diff --git a/Documentation/i2c/busses/i2c-amd-mp2 b/Documentation/i2c/busses/i2c-amd-mp2
new file mode 100644
index 000000000000..6571487171f4
--- /dev/null
+++ b/Documentation/i2c/busses/i2c-amd-mp2
@@ -0,0 +1,23 @@
1Kernel driver i2c-amd-mp2
2
3Supported adapters:
4 * AMD MP2 PCIe interface
5
6Datasheet: not publicly available.
7
8Authors:
9 Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
10 Nehal Shah <nehal-bakulchandra.shah@amd.com>
11 Elie Morisse <syniurge@gmail.com>
12
13Description
14-----------
15
16The MP2 is an ARM processor programmed as an I2C controller and communicating
17with the x86 host through PCI.
18
19If you see something like this:
20
2103:00.7 MP2 I2C controller: Advanced Micro Devices, Inc. [AMD] Device 15e6
22
23in your 'lspci -v', then this driver is for your device.
diff --git a/Documentation/i2c/busses/i2c-piix4 b/Documentation/i2c/busses/i2c-piix4
index aa959fd22450..2703bc3acad0 100644
--- a/Documentation/i2c/busses/i2c-piix4
+++ b/Documentation/i2c/busses/i2c-piix4
@@ -15,6 +15,8 @@ Supported adapters:
15 http://support.amd.com/us/Embedded_TechDocs/44413.pdf 15 http://support.amd.com/us/Embedded_TechDocs/44413.pdf
16 * AMD Hudson-2, ML, CZ 16 * AMD Hudson-2, ML, CZ
17 Datasheet: Not publicly available 17 Datasheet: Not publicly available
18 * Hygon CZ
19 Datasheet: Not publicly available
18 * Standard Microsystems (SMSC) SLC90E66 (Victory66) southbridge 20 * Standard Microsystems (SMSC) SLC90E66 (Victory66) southbridge
19 Datasheet: Publicly available at the SMSC website http://www.smsc.com 21 Datasheet: Publicly available at the SMSC website http://www.smsc.com
20 22
diff --git a/MAINTAINERS b/MAINTAINERS
index ae4063ef5533..a3143515e134 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -826,6 +826,14 @@ F: drivers/gpu/drm/amd/include/vi_structs.h
826F: drivers/gpu/drm/amd/include/v9_structs.h 826F: drivers/gpu/drm/amd/include/v9_structs.h
827F: include/uapi/linux/kfd_ioctl.h 827F: include/uapi/linux/kfd_ioctl.h
828 828
829AMD MP2 I2C DRIVER
830M: Elie Morisse <syniurge@gmail.com>
831M: Nehal Shah <nehal-bakulchandra.shah@amd.com>
832M: Shyam Sundar S K <shyam-sundar.s-k@amd.com>
833L: linux-i2c@vger.kernel.org
834S: Maintained
835F: drivers/i2c/busses/i2c-amd-mp2*
836
829AMD POWERPLAY 837AMD POWERPLAY
830M: Rex Zhu <rex.zhu@amd.com> 838M: Rex Zhu <rex.zhu@amd.com>
831M: Evan Quan <evan.quan@amd.com> 839M: Evan Quan <evan.quan@amd.com>
@@ -2582,7 +2590,7 @@ F: include/linux/dmaengine.h
2582F: include/linux/async_tx.h 2590F: include/linux/async_tx.h
2583 2591
2584AT24 EEPROM DRIVER 2592AT24 EEPROM DRIVER
2585M: Bartosz Golaszewski <brgl@bgdev.pl> 2593M: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2586L: linux-i2c@vger.kernel.org 2594L: linux-i2c@vger.kernel.org
2587T: git git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git 2595T: git git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git
2588S: Maintained 2596S: Maintained
@@ -10207,7 +10215,8 @@ MICROCHIP I2C DRIVER
10207M: Ludovic Desroches <ludovic.desroches@microchip.com> 10215M: Ludovic Desroches <ludovic.desroches@microchip.com>
10208L: linux-i2c@vger.kernel.org 10216L: linux-i2c@vger.kernel.org
10209S: Supported 10217S: Supported
10210F: drivers/i2c/busses/i2c-at91.c 10218F: drivers/i2c/busses/i2c-at91.h
10219F: drivers/i2c/busses/i2c-at91-*.c
10211 10220
10212MICROCHIP ISC DRIVER 10221MICROCHIP ISC DRIVER
10213M: Eugen Hristev <eugen.hristev@microchip.com> 10222M: Eugen Hristev <eugen.hristev@microchip.com>
diff --git a/drivers/i2c/algos/i2c-algo-bit.c b/drivers/i2c/algos/i2c-algo-bit.c
index 5e5990a83da5..913db013fe90 100644
--- a/drivers/i2c/algos/i2c-algo-bit.c
+++ b/drivers/i2c/algos/i2c-algo-bit.c
@@ -603,6 +603,23 @@ bailout:
603 return ret; 603 return ret;
604} 604}
605 605
606/*
607 * We print a warning when we are not flagged to support atomic transfers but
608 * will try anyhow. That's what the I2C core would do as well. Sadly, we can't
609 * modify the algorithm struct at probe time because this struct is exported
610 * 'const'.
611 */
612static int bit_xfer_atomic(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[],
613 int num)
614{
615 struct i2c_algo_bit_data *adap = i2c_adap->algo_data;
616
617 if (!adap->can_do_atomic)
618 dev_warn(&i2c_adap->dev, "not flagged for atomic transfers\n");
619
620 return bit_xfer(i2c_adap, msgs, num);
621}
622
606static u32 bit_func(struct i2c_adapter *adap) 623static u32 bit_func(struct i2c_adapter *adap)
607{ 624{
608 return I2C_FUNC_I2C | I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_EMUL | 625 return I2C_FUNC_I2C | I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_EMUL |
@@ -615,8 +632,9 @@ static u32 bit_func(struct i2c_adapter *adap)
615/* -----exported algorithm data: ------------------------------------- */ 632/* -----exported algorithm data: ------------------------------------- */
616 633
617const struct i2c_algorithm i2c_bit_algo = { 634const struct i2c_algorithm i2c_bit_algo = {
618 .master_xfer = bit_xfer, 635 .master_xfer = bit_xfer,
619 .functionality = bit_func, 636 .master_xfer_atomic = bit_xfer_atomic,
637 .functionality = bit_func,
620}; 638};
621EXPORT_SYMBOL(i2c_bit_algo); 639EXPORT_SYMBOL(i2c_bit_algo);
622 640
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index f8979abb9a19..26186439db6b 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -77,6 +77,16 @@ config I2C_AMD8111
77 This driver can also be built as a module. If so, the module 77 This driver can also be built as a module. If so, the module
78 will be called i2c-amd8111. 78 will be called i2c-amd8111.
79 79
80config I2C_AMD_MP2
81 tristate "AMD MP2 PCIe"
82 depends on PCI && ACPI
83 help
84 If you say yes to this option, support will be included for the AMD
85 MP2 PCIe I2C adapter.
86
87 This driver can also be built as modules. If so, the modules will
88 be called i2c-amd-mp2-pci and i2c-amd-mp2-plat.
89
80config I2C_HIX5HD2 90config I2C_HIX5HD2
81 tristate "Hix5hd2 high-speed I2C driver" 91 tristate "Hix5hd2 high-speed I2C driver"
82 depends on ARCH_HISI || ARCH_HIX5HD2 || COMPILE_TEST 92 depends on ARCH_HISI || ARCH_HIX5HD2 || COMPILE_TEST
@@ -176,6 +186,7 @@ config I2C_PIIX4
176 AMD Hudson-2 186 AMD Hudson-2
177 AMD ML 187 AMD ML
178 AMD CZ 188 AMD CZ
189 Hygon CZ
179 Serverworks OSB4 190 Serverworks OSB4
180 Serverworks CSB5 191 Serverworks CSB5
181 Serverworks CSB6 192 Serverworks CSB6
@@ -388,6 +399,19 @@ config I2C_AT91
388 the latency to fill the transmission register is too long. If you 399 the latency to fill the transmission register is too long. If you
389 are facing this situation, use the i2c-gpio driver. 400 are facing this situation, use the i2c-gpio driver.
390 401
402config I2C_AT91_SLAVE_EXPERIMENTAL
403 tristate "Microchip AT91 I2C experimental slave mode"
404 depends on I2C_AT91
405 select I2C_SLAVE
406 help
407 If you say yes to this option, support for the slave mode will be
408 added. Caution: do not use it for production. This feature has not
409 been tested in a heavy way, help wanted.
410 There are known bugs:
411 - It can hang, on a SAMA5D4, after several transfers.
412 - There are some mismtaches with a SAMA5D4 as slave and a SAMA5D2 as
413 master.
414
391config I2C_AU1550 415config I2C_AU1550
392 tristate "Au1550/Au1200/Au1300 SMBus interface" 416 tristate "Au1550/Au1200/Au1300 SMBus interface"
393 depends on MIPS_ALCHEMY 417 depends on MIPS_ALCHEMY
@@ -425,6 +449,7 @@ config I2C_BCM_IPROC
425 tristate "Broadcom iProc I2C controller" 449 tristate "Broadcom iProc I2C controller"
426 depends on ARCH_BCM_IPROC || COMPILE_TEST 450 depends on ARCH_BCM_IPROC || COMPILE_TEST
427 default ARCH_BCM_IPROC 451 default ARCH_BCM_IPROC
452 select I2C_SLAVE
428 help 453 help
429 If you say yes to this option, support will be included for the 454 If you say yes to this option, support will be included for the
430 Broadcom iProc I2C controller. 455 Broadcom iProc I2C controller.
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 5f0cb6915969..a3245231b0b7 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -33,8 +33,13 @@ obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o
33 33
34# Embedded system I2C/SMBus host controller drivers 34# Embedded system I2C/SMBus host controller drivers
35obj-$(CONFIG_I2C_ALTERA) += i2c-altera.o 35obj-$(CONFIG_I2C_ALTERA) += i2c-altera.o
36obj-$(CONFIG_I2C_AMD_MP2) += i2c-amd-mp2-pci.o i2c-amd-mp2-plat.o
36obj-$(CONFIG_I2C_ASPEED) += i2c-aspeed.o 37obj-$(CONFIG_I2C_ASPEED) += i2c-aspeed.o
37obj-$(CONFIG_I2C_AT91) += i2c-at91.o 38obj-$(CONFIG_I2C_AT91) += i2c-at91.o
39i2c-at91-objs := i2c-at91-core.o i2c-at91-master.o
40ifeq ($(CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL),y)
41 i2c-at91-objs += i2c-at91-slave.o
42endif
38obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o 43obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o
39obj-$(CONFIG_I2C_AXXIA) += i2c-axxia.o 44obj-$(CONFIG_I2C_AXXIA) += i2c-axxia.o
40obj-$(CONFIG_I2C_BCM2835) += i2c-bcm2835.o 45obj-$(CONFIG_I2C_BCM2835) += i2c-bcm2835.o
diff --git a/drivers/i2c/busses/i2c-amd-mp2-pci.c b/drivers/i2c/busses/i2c-amd-mp2-pci.c
new file mode 100644
index 000000000000..455e1f36a2a3
--- /dev/null
+++ b/drivers/i2c/busses/i2c-amd-mp2-pci.c
@@ -0,0 +1,483 @@
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * AMD MP2 PCIe communication driver
4 *
5 * Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
6 * Elie Morisse <syniurge@gmail.com>
7 */
8
9#include <linux/dma-mapping.h>
10#include <linux/interrupt.h>
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/slab.h>
14
15#include "i2c-amd-mp2.h"
16
17#include <linux/io-64-nonatomic-lo-hi.h>
18
19static void amd_mp2_c2p_mutex_lock(struct amd_i2c_common *i2c_common)
20{
21 struct amd_mp2_dev *privdata = i2c_common->mp2_dev;
22
23 /* there is only one data mailbox for two i2c adapters */
24 mutex_lock(&privdata->c2p_lock);
25 privdata->c2p_lock_busid = i2c_common->bus_id;
26}
27
28static void amd_mp2_c2p_mutex_unlock(struct amd_i2c_common *i2c_common)
29{
30 struct amd_mp2_dev *privdata = i2c_common->mp2_dev;
31
32 if (unlikely(privdata->c2p_lock_busid != i2c_common->bus_id)) {
33 dev_warn(ndev_dev(privdata),
34 "bus %d attempting to unlock C2P locked by bus %d\n",
35 i2c_common->bus_id, privdata->c2p_lock_busid);
36 return;
37 }
38
39 mutex_unlock(&privdata->c2p_lock);
40}
41
42static int amd_mp2_cmd(struct amd_i2c_common *i2c_common,
43 union i2c_cmd_base i2c_cmd_base)
44{
45 struct amd_mp2_dev *privdata = i2c_common->mp2_dev;
46 void __iomem *reg;
47
48 i2c_common->reqcmd = i2c_cmd_base.s.i2c_cmd;
49
50 reg = privdata->mmio + ((i2c_cmd_base.s.bus_id == 1) ?
51 AMD_C2P_MSG1 : AMD_C2P_MSG0);
52 writel(i2c_cmd_base.ul, reg);
53
54 return 0;
55}
56
57int amd_mp2_bus_enable_set(struct amd_i2c_common *i2c_common, bool enable)
58{
59 struct amd_mp2_dev *privdata = i2c_common->mp2_dev;
60 union i2c_cmd_base i2c_cmd_base;
61
62 dev_dbg(ndev_dev(privdata), "%s id: %d\n", __func__,
63 i2c_common->bus_id);
64
65 i2c_cmd_base.ul = 0;
66 i2c_cmd_base.s.i2c_cmd = enable ? i2c_enable : i2c_disable;
67 i2c_cmd_base.s.bus_id = i2c_common->bus_id;
68 i2c_cmd_base.s.i2c_speed = i2c_common->i2c_speed;
69
70 amd_mp2_c2p_mutex_lock(i2c_common);
71
72 return amd_mp2_cmd(i2c_common, i2c_cmd_base);
73}
74EXPORT_SYMBOL_GPL(amd_mp2_bus_enable_set);
75
76static void amd_mp2_cmd_rw_fill(struct amd_i2c_common *i2c_common,
77 union i2c_cmd_base *i2c_cmd_base,
78 enum i2c_cmd reqcmd)
79{
80 i2c_cmd_base->s.i2c_cmd = reqcmd;
81 i2c_cmd_base->s.bus_id = i2c_common->bus_id;
82 i2c_cmd_base->s.i2c_speed = i2c_common->i2c_speed;
83 i2c_cmd_base->s.slave_addr = i2c_common->msg->addr;
84 i2c_cmd_base->s.length = i2c_common->msg->len;
85}
86
87int amd_mp2_rw(struct amd_i2c_common *i2c_common, enum i2c_cmd reqcmd)
88{
89 struct amd_mp2_dev *privdata = i2c_common->mp2_dev;
90 union i2c_cmd_base i2c_cmd_base;
91
92 amd_mp2_cmd_rw_fill(i2c_common, &i2c_cmd_base, reqcmd);
93 amd_mp2_c2p_mutex_lock(i2c_common);
94
95 if (i2c_common->msg->len <= 32) {
96 i2c_cmd_base.s.mem_type = use_c2pmsg;
97 if (reqcmd == i2c_write)
98 memcpy_toio(privdata->mmio + AMD_C2P_MSG2,
99 i2c_common->msg->buf,
100 i2c_common->msg->len);
101 } else {
102 i2c_cmd_base.s.mem_type = use_dram;
103 writeq((u64)i2c_common->dma_addr,
104 privdata->mmio + AMD_C2P_MSG2);
105 }
106
107 return amd_mp2_cmd(i2c_common, i2c_cmd_base);
108}
109EXPORT_SYMBOL_GPL(amd_mp2_rw);
110
111static void amd_mp2_pci_check_rw_event(struct amd_i2c_common *i2c_common)
112{
113 struct amd_mp2_dev *privdata = i2c_common->mp2_dev;
114 int len = i2c_common->eventval.r.length;
115 u32 slave_addr = i2c_common->eventval.r.slave_addr;
116 bool err = false;
117
118 if (unlikely(len != i2c_common->msg->len)) {
119 dev_err(ndev_dev(privdata),
120 "length %d in event doesn't match buffer length %d!\n",
121 len, i2c_common->msg->len);
122 err = true;
123 }
124
125 if (unlikely(slave_addr != i2c_common->msg->addr)) {
126 dev_err(ndev_dev(privdata),
127 "unexpected slave address %x (expected: %x)!\n",
128 slave_addr, i2c_common->msg->addr);
129 err = true;
130 }
131
132 if (!err)
133 i2c_common->cmd_success = true;
134}
135
136static void __amd_mp2_process_event(struct amd_i2c_common *i2c_common)
137{
138 struct amd_mp2_dev *privdata = i2c_common->mp2_dev;
139 enum status_type sts = i2c_common->eventval.r.status;
140 enum response_type res = i2c_common->eventval.r.response;
141 int len = i2c_common->eventval.r.length;
142
143 if (res != command_success) {
144 if (res != command_failed)
145 dev_err(ndev_dev(privdata), "invalid response to i2c command!\n");
146 return;
147 }
148
149 switch (i2c_common->reqcmd) {
150 case i2c_read:
151 if (sts == i2c_readcomplete_event) {
152 amd_mp2_pci_check_rw_event(i2c_common);
153 if (len <= 32)
154 memcpy_fromio(i2c_common->msg->buf,
155 privdata->mmio + AMD_C2P_MSG2,
156 len);
157 } else if (sts != i2c_readfail_event) {
158 dev_err(ndev_dev(privdata),
159 "invalid i2c status after read (%d)!\n", sts);
160 }
161 break;
162 case i2c_write:
163 if (sts == i2c_writecomplete_event)
164 amd_mp2_pci_check_rw_event(i2c_common);
165 else if (sts != i2c_writefail_event)
166 dev_err(ndev_dev(privdata),
167 "invalid i2c status after write (%d)!\n", sts);
168 break;
169 case i2c_enable:
170 if (sts == i2c_busenable_complete)
171 i2c_common->cmd_success = true;
172 else if (sts != i2c_busenable_failed)
173 dev_err(ndev_dev(privdata),
174 "invalid i2c status after bus enable (%d)!\n",
175 sts);
176 break;
177 case i2c_disable:
178 if (sts == i2c_busdisable_complete)
179 i2c_common->cmd_success = true;
180 else if (sts != i2c_busdisable_failed)
181 dev_err(ndev_dev(privdata),
182 "invalid i2c status after bus disable (%d)!\n",
183 sts);
184 break;
185 default:
186 break;
187 }
188}
189
190void amd_mp2_process_event(struct amd_i2c_common *i2c_common)
191{
192 struct amd_mp2_dev *privdata = i2c_common->mp2_dev;
193
194 if (unlikely(i2c_common->reqcmd == i2c_none)) {
195 dev_warn(ndev_dev(privdata),
196 "received msg but no cmd was sent (bus = %d)!\n",
197 i2c_common->bus_id);
198 return;
199 }
200
201 __amd_mp2_process_event(i2c_common);
202
203 i2c_common->reqcmd = i2c_none;
204 amd_mp2_c2p_mutex_unlock(i2c_common);
205}
206EXPORT_SYMBOL_GPL(amd_mp2_process_event);
207
208static irqreturn_t amd_mp2_irq_isr(int irq, void *dev)
209{
210 struct amd_mp2_dev *privdata = dev;
211 struct amd_i2c_common *i2c_common;
212 u32 val;
213 unsigned int bus_id;
214 void __iomem *reg;
215 enum irqreturn ret = IRQ_NONE;
216
217 for (bus_id = 0; bus_id < 2; bus_id++) {
218 i2c_common = privdata->busses[bus_id];
219 if (!i2c_common)
220 continue;
221
222 reg = privdata->mmio + ((bus_id == 0) ?
223 AMD_P2C_MSG1 : AMD_P2C_MSG2);
224 val = readl(reg);
225 if (val != 0) {
226 writel(0, reg);
227 writel(0, privdata->mmio + AMD_P2C_MSG_INTEN);
228 i2c_common->eventval.ul = val;
229 i2c_common->cmd_completion(i2c_common);
230
231 ret = IRQ_HANDLED;
232 }
233 }
234
235 if (ret != IRQ_HANDLED) {
236 val = readl(privdata->mmio + AMD_P2C_MSG_INTEN);
237 if (val != 0) {
238 writel(0, privdata->mmio + AMD_P2C_MSG_INTEN);
239 dev_warn(ndev_dev(privdata),
240 "received irq without message\n");
241 ret = IRQ_HANDLED;
242 }
243 }
244
245 return ret;
246}
247
248void amd_mp2_rw_timeout(struct amd_i2c_common *i2c_common)
249{
250 i2c_common->reqcmd = i2c_none;
251 amd_mp2_c2p_mutex_unlock(i2c_common);
252}
253EXPORT_SYMBOL_GPL(amd_mp2_rw_timeout);
254
255int amd_mp2_register_cb(struct amd_i2c_common *i2c_common)
256{
257 struct amd_mp2_dev *privdata = i2c_common->mp2_dev;
258
259 if (i2c_common->bus_id > 1)
260 return -EINVAL;
261
262 if (privdata->busses[i2c_common->bus_id]) {
263 dev_err(ndev_dev(privdata),
264 "Bus %d already taken!\n", i2c_common->bus_id);
265 return -EINVAL;
266 }
267
268 privdata->busses[i2c_common->bus_id] = i2c_common;
269
270 return 0;
271}
272EXPORT_SYMBOL_GPL(amd_mp2_register_cb);
273
274int amd_mp2_unregister_cb(struct amd_i2c_common *i2c_common)
275{
276 struct amd_mp2_dev *privdata = i2c_common->mp2_dev;
277
278 privdata->busses[i2c_common->bus_id] = NULL;
279
280 return 0;
281}
282EXPORT_SYMBOL_GPL(amd_mp2_unregister_cb);
283
284static void amd_mp2_clear_reg(struct amd_mp2_dev *privdata)
285{
286 int reg;
287
288 for (reg = AMD_C2P_MSG0; reg <= AMD_C2P_MSG9; reg += 4)
289 writel(0, privdata->mmio + reg);
290
291 for (reg = AMD_P2C_MSG1; reg <= AMD_P2C_MSG2; reg += 4)
292 writel(0, privdata->mmio + reg);
293}
294
295static int amd_mp2_pci_init(struct amd_mp2_dev *privdata,
296 struct pci_dev *pci_dev)
297{
298 int rc;
299
300 pci_set_drvdata(pci_dev, privdata);
301
302 rc = pcim_enable_device(pci_dev);
303 if (rc) {
304 dev_err(ndev_dev(privdata), "Failed to enable MP2 PCI device\n");
305 goto err_pci_enable;
306 }
307
308 rc = pcim_iomap_regions(pci_dev, 1 << 2, pci_name(pci_dev));
309 if (rc) {
310 dev_err(ndev_dev(privdata), "I/O memory remapping failed\n");
311 goto err_pci_enable;
312 }
313 privdata->mmio = pcim_iomap_table(pci_dev)[2];
314
315 pci_set_master(pci_dev);
316
317 rc = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64));
318 if (rc) {
319 rc = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
320 if (rc)
321 goto err_dma_mask;
322 }
323
324 /* Set up intx irq */
325 writel(0, privdata->mmio + AMD_P2C_MSG_INTEN);
326 pci_intx(pci_dev, 1);
327 rc = devm_request_irq(&pci_dev->dev, pci_dev->irq, amd_mp2_irq_isr,
328 IRQF_SHARED, dev_name(&pci_dev->dev), privdata);
329 if (rc)
330 dev_err(&pci_dev->dev, "Failure requesting irq %i: %d\n",
331 pci_dev->irq, rc);
332
333 return rc;
334
335err_dma_mask:
336 pci_clear_master(pci_dev);
337err_pci_enable:
338 pci_set_drvdata(pci_dev, NULL);
339 return rc;
340}
341
342static int amd_mp2_pci_probe(struct pci_dev *pci_dev,
343 const struct pci_device_id *id)
344{
345 struct amd_mp2_dev *privdata;
346 int rc;
347
348 privdata = devm_kzalloc(&pci_dev->dev, sizeof(*privdata), GFP_KERNEL);
349 if (!privdata)
350 return -ENOMEM;
351
352 rc = amd_mp2_pci_init(privdata, pci_dev);
353 if (rc)
354 return rc;
355
356 mutex_init(&privdata->c2p_lock);
357 privdata->pci_dev = pci_dev;
358
359 pm_runtime_set_autosuspend_delay(&pci_dev->dev, 1000);
360 pm_runtime_use_autosuspend(&pci_dev->dev);
361 pm_runtime_put_autosuspend(&pci_dev->dev);
362 pm_runtime_allow(&pci_dev->dev);
363
364 privdata->probed = true;
365
366 dev_info(&pci_dev->dev, "MP2 device registered.\n");
367 return 0;
368}
369
370static void amd_mp2_pci_remove(struct pci_dev *pci_dev)
371{
372 struct amd_mp2_dev *privdata = pci_get_drvdata(pci_dev);
373
374 pm_runtime_forbid(&pci_dev->dev);
375 pm_runtime_get_noresume(&pci_dev->dev);
376
377 pci_intx(pci_dev, 0);
378 pci_clear_master(pci_dev);
379
380 amd_mp2_clear_reg(privdata);
381}
382
383#ifdef CONFIG_PM
384static int amd_mp2_pci_suspend(struct device *dev)
385{
386 struct pci_dev *pci_dev = to_pci_dev(dev);
387 struct amd_mp2_dev *privdata = pci_get_drvdata(pci_dev);
388 struct amd_i2c_common *i2c_common;
389 unsigned int bus_id;
390 int ret = 0;
391
392 for (bus_id = 0; bus_id < 2; bus_id++) {
393 i2c_common = privdata->busses[bus_id];
394 if (i2c_common)
395 i2c_common->suspend(i2c_common);
396 }
397
398 ret = pci_save_state(pci_dev);
399 if (ret) {
400 dev_err(ndev_dev(privdata),
401 "pci_save_state failed = %d\n", ret);
402 return ret;
403 }
404
405 pci_disable_device(pci_dev);
406 return ret;
407}
408
409static int amd_mp2_pci_resume(struct device *dev)
410{
411 struct pci_dev *pci_dev = to_pci_dev(dev);
412 struct amd_mp2_dev *privdata = pci_get_drvdata(pci_dev);
413 struct amd_i2c_common *i2c_common;
414 unsigned int bus_id;
415 int ret = 0;
416
417 pci_restore_state(pci_dev);
418 ret = pci_enable_device(pci_dev);
419 if (ret < 0) {
420 dev_err(ndev_dev(privdata),
421 "pci_enable_device failed = %d\n", ret);
422 return ret;
423 }
424
425 for (bus_id = 0; bus_id < 2; bus_id++) {
426 i2c_common = privdata->busses[bus_id];
427 if (i2c_common) {
428 ret = i2c_common->resume(i2c_common);
429 if (ret < 0)
430 return ret;
431 }
432 }
433
434 return ret;
435}
436
437static UNIVERSAL_DEV_PM_OPS(amd_mp2_pci_pm_ops, amd_mp2_pci_suspend,
438 amd_mp2_pci_resume, NULL);
439#endif /* CONFIG_PM */
440
441static const struct pci_device_id amd_mp2_pci_tbl[] = {
442 {PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MP2)},
443 {0}
444};
445MODULE_DEVICE_TABLE(pci, amd_mp2_pci_tbl);
446
447static struct pci_driver amd_mp2_pci_driver = {
448 .name = "i2c_amd_mp2",
449 .id_table = amd_mp2_pci_tbl,
450 .probe = amd_mp2_pci_probe,
451 .remove = amd_mp2_pci_remove,
452#ifdef CONFIG_PM
453 .driver = {
454 .pm = &amd_mp2_pci_pm_ops,
455 },
456#endif
457};
458module_pci_driver(amd_mp2_pci_driver);
459
460static int amd_mp2_device_match(struct device *dev, void *data)
461{
462 return 1;
463}
464
465struct amd_mp2_dev *amd_mp2_find_device(void)
466{
467 struct device *dev;
468 struct pci_dev *pci_dev;
469
470 dev = driver_find_device(&amd_mp2_pci_driver.driver, NULL, NULL,
471 amd_mp2_device_match);
472 if (!dev)
473 return NULL;
474
475 pci_dev = to_pci_dev(dev);
476 return (struct amd_mp2_dev *)pci_get_drvdata(pci_dev);
477}
478EXPORT_SYMBOL_GPL(amd_mp2_find_device);
479
480MODULE_DESCRIPTION("AMD(R) PCI-E MP2 I2C Controller Driver");
481MODULE_AUTHOR("Shyam Sundar S K <Shyam-sundar.S-k@amd.com>");
482MODULE_AUTHOR("Elie Morisse <syniurge@gmail.com>");
483MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/i2c/busses/i2c-amd-mp2-plat.c b/drivers/i2c/busses/i2c-amd-mp2-plat.c
new file mode 100644
index 000000000000..f5b3f00c6559
--- /dev/null
+++ b/drivers/i2c/busses/i2c-amd-mp2-plat.c
@@ -0,0 +1,367 @@
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * AMD MP2 platform driver
4 *
5 * Setup the I2C adapters enumerated in the ACPI namespace.
6 * MP2 controllers have 2 separate busses, up to 2 I2C adapters may be listed.
7 *
8 * Authors: Nehal Bakulchandra Shah <Nehal-bakulchandra.shah@amd.com>
9 * Elie Morisse <syniurge@gmail.com>
10 */
11
12#include <linux/acpi.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/slab.h>
17#include <linux/types.h>
18
19#include "i2c-amd-mp2.h"
20
21#define AMD_MP2_I2C_MAX_RW_LENGTH ((1 << 12) - 1)
22#define AMD_I2C_TIMEOUT (msecs_to_jiffies(250))
23
24/**
25 * struct amd_i2c_dev - MP2 bus/i2c adapter context
26 * @common: shared context with the MP2 PCI driver
27 * @pdev: platform driver node
28 * @adap: i2c adapter
29 * @cmd_complete: xfer completion object
30 */
31struct amd_i2c_dev {
32 struct amd_i2c_common common;
33 struct platform_device *pdev;
34 struct i2c_adapter adap;
35 struct completion cmd_complete;
36};
37
38#define amd_i2c_dev_common(__common) \
39 container_of(__common, struct amd_i2c_dev, common)
40
41static int i2c_amd_dma_map(struct amd_i2c_common *i2c_common)
42{
43 struct device *dev_pci = &i2c_common->mp2_dev->pci_dev->dev;
44 struct amd_i2c_dev *i2c_dev = amd_i2c_dev_common(i2c_common);
45 enum dma_data_direction dma_direction =
46 i2c_common->msg->flags & I2C_M_RD ?
47 DMA_FROM_DEVICE : DMA_TO_DEVICE;
48
49 i2c_common->dma_buf = i2c_get_dma_safe_msg_buf(i2c_common->msg, 0);
50 i2c_common->dma_addr = dma_map_single(dev_pci, i2c_common->dma_buf,
51 i2c_common->msg->len,
52 dma_direction);
53
54 if (unlikely(dma_mapping_error(dev_pci, i2c_common->dma_addr))) {
55 dev_err(&i2c_dev->pdev->dev,
56 "Error while mapping dma buffer %p\n",
57 i2c_common->dma_buf);
58 return -EIO;
59 }
60
61 return 0;
62}
63
64static void i2c_amd_dma_unmap(struct amd_i2c_common *i2c_common)
65{
66 struct device *dev_pci = &i2c_common->mp2_dev->pci_dev->dev;
67 enum dma_data_direction dma_direction =
68 i2c_common->msg->flags & I2C_M_RD ?
69 DMA_FROM_DEVICE : DMA_TO_DEVICE;
70
71 dma_unmap_single(dev_pci, i2c_common->dma_addr,
72 i2c_common->msg->len, dma_direction);
73
74 i2c_put_dma_safe_msg_buf(i2c_common->dma_buf, i2c_common->msg, true);
75}
76
77static void i2c_amd_start_cmd(struct amd_i2c_dev *i2c_dev)
78{
79 struct amd_i2c_common *i2c_common = &i2c_dev->common;
80
81 reinit_completion(&i2c_dev->cmd_complete);
82 i2c_common->cmd_success = false;
83}
84
85static void i2c_amd_cmd_completion(struct amd_i2c_common *i2c_common)
86{
87 struct amd_i2c_dev *i2c_dev = amd_i2c_dev_common(i2c_common);
88 union i2c_event *event = &i2c_common->eventval;
89
90 if (event->r.status == i2c_readcomplete_event)
91 dev_dbg(&i2c_dev->pdev->dev, "%s readdata:%*ph\n",
92 __func__, event->r.length,
93 i2c_common->msg->buf);
94
95 complete(&i2c_dev->cmd_complete);
96}
97
98static int i2c_amd_check_cmd_completion(struct amd_i2c_dev *i2c_dev)
99{
100 struct amd_i2c_common *i2c_common = &i2c_dev->common;
101 unsigned long timeout;
102
103 timeout = wait_for_completion_timeout(&i2c_dev->cmd_complete,
104 i2c_dev->adap.timeout);
105
106 if ((i2c_common->reqcmd == i2c_read ||
107 i2c_common->reqcmd == i2c_write) &&
108 i2c_common->msg->len > 32)
109 i2c_amd_dma_unmap(i2c_common);
110
111 if (timeout == 0) {
112 amd_mp2_rw_timeout(i2c_common);
113 return -ETIMEDOUT;
114 }
115
116 amd_mp2_process_event(i2c_common);
117
118 if (!i2c_common->cmd_success)
119 return -EIO;
120
121 return 0;
122}
123
124static int i2c_amd_enable_set(struct amd_i2c_dev *i2c_dev, bool enable)
125{
126 struct amd_i2c_common *i2c_common = &i2c_dev->common;
127
128 i2c_amd_start_cmd(i2c_dev);
129 amd_mp2_bus_enable_set(i2c_common, enable);
130
131 return i2c_amd_check_cmd_completion(i2c_dev);
132}
133
134static int i2c_amd_xfer_msg(struct amd_i2c_dev *i2c_dev, struct i2c_msg *pmsg)
135{
136 struct amd_i2c_common *i2c_common = &i2c_dev->common;
137
138 i2c_amd_start_cmd(i2c_dev);
139 i2c_common->msg = pmsg;
140
141 if (pmsg->len > 32)
142 if (i2c_amd_dma_map(i2c_common))
143 return -EIO;
144
145 if (pmsg->flags & I2C_M_RD)
146 amd_mp2_rw(i2c_common, i2c_read);
147 else
148 amd_mp2_rw(i2c_common, i2c_write);
149
150 return i2c_amd_check_cmd_completion(i2c_dev);
151}
152
153static int i2c_amd_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
154{
155 struct amd_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
156 int i;
157 struct i2c_msg *pmsg;
158 int err;
159
160 /* the adapter might have been deleted while waiting for the bus lock */
161 if (unlikely(!i2c_dev->common.mp2_dev))
162 return -EINVAL;
163
164 amd_mp2_pm_runtime_get(i2c_dev->common.mp2_dev);
165
166 for (i = 0; i < num; i++) {
167 pmsg = &msgs[i];
168 err = i2c_amd_xfer_msg(i2c_dev, pmsg);
169 if (err)
170 break;
171 }
172
173 amd_mp2_pm_runtime_put(i2c_dev->common.mp2_dev);
174 return err ? err : num;
175}
176
177static u32 i2c_amd_func(struct i2c_adapter *a)
178{
179 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
180}
181
182static const struct i2c_algorithm i2c_amd_algorithm = {
183 .master_xfer = i2c_amd_xfer,
184 .functionality = i2c_amd_func,
185};
186
187#ifdef CONFIG_PM
188static int i2c_amd_suspend(struct amd_i2c_common *i2c_common)
189{
190 struct amd_i2c_dev *i2c_dev = amd_i2c_dev_common(i2c_common);
191
192 i2c_amd_enable_set(i2c_dev, false);
193 return 0;
194}
195
196static int i2c_amd_resume(struct amd_i2c_common *i2c_common)
197{
198 struct amd_i2c_dev *i2c_dev = amd_i2c_dev_common(i2c_common);
199
200 return i2c_amd_enable_set(i2c_dev, true);
201}
202#endif
203
204static enum speed_enum i2c_amd_get_bus_speed(struct platform_device *pdev)
205{
206 u32 acpi_speed;
207 int i;
208 static const u32 supported_speeds[] = {
209 0, 100000, 400000, 1000000, 1400000, 3400000
210 };
211
212 acpi_speed = i2c_acpi_find_bus_speed(&pdev->dev);
213 /* round down to the lowest standard speed */
214 for (i = 1; i < ARRAY_SIZE(supported_speeds); i++) {
215 if (acpi_speed < supported_speeds[i])
216 break;
217 }
218 acpi_speed = supported_speeds[i - 1];
219
220 switch (acpi_speed) {
221 case 100000:
222 return speed100k;
223 case 400000:
224 return speed400k;
225 case 1000000:
226 return speed1000k;
227 case 1400000:
228 return speed1400k;
229 case 3400000:
230 return speed3400k;
231 default:
232 return speed400k;
233 }
234}
235
236static const struct i2c_adapter_quirks amd_i2c_dev_quirks = {
237 .max_read_len = AMD_MP2_I2C_MAX_RW_LENGTH,
238 .max_write_len = AMD_MP2_I2C_MAX_RW_LENGTH,
239};
240
241static int i2c_amd_probe(struct platform_device *pdev)
242{
243 int ret;
244 struct amd_i2c_dev *i2c_dev;
245 acpi_handle handle = ACPI_HANDLE(&pdev->dev);
246 struct acpi_device *adev;
247 struct amd_mp2_dev *mp2_dev;
248 const char *uid;
249
250 if (acpi_bus_get_device(handle, &adev))
251 return -ENODEV;
252
253 /* The ACPI namespace doesn't contain information about which MP2 PCI
254 * device an AMDI0011 ACPI device is related to, so assume that there's
255 * only one MP2 PCI device per system.
256 */
257 mp2_dev = amd_mp2_find_device();
258 if (!mp2_dev || !mp2_dev->probed)
259 /* The MP2 PCI device should get probed later */
260 return -EPROBE_DEFER;
261
262 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
263 if (!i2c_dev)
264 return -ENOMEM;
265
266 i2c_dev->common.mp2_dev = mp2_dev;
267 i2c_dev->pdev = pdev;
268 platform_set_drvdata(pdev, i2c_dev);
269
270 i2c_dev->common.cmd_completion = &i2c_amd_cmd_completion;
271#ifdef CONFIG_PM
272 i2c_dev->common.suspend = &i2c_amd_suspend;
273 i2c_dev->common.resume = &i2c_amd_resume;
274#endif
275
276 uid = adev->pnp.unique_id;
277 if (!uid) {
278 dev_err(&pdev->dev, "missing UID/bus id!\n");
279 return -EINVAL;
280 } else if (strcmp(uid, "0") == 0) {
281 i2c_dev->common.bus_id = 0;
282 } else if (strcmp(uid, "1") == 0) {
283 i2c_dev->common.bus_id = 1;
284 } else {
285 dev_err(&pdev->dev, "incorrect UID/bus id \"%s\"!\n", uid);
286 return -EINVAL;
287 }
288 dev_dbg(&pdev->dev, "bus id is %u\n", i2c_dev->common.bus_id);
289
290 /* Register the adapter */
291 amd_mp2_pm_runtime_get(mp2_dev);
292
293 i2c_dev->common.reqcmd = i2c_none;
294 if (amd_mp2_register_cb(&i2c_dev->common))
295 return -EINVAL;
296 device_link_add(&i2c_dev->pdev->dev, &mp2_dev->pci_dev->dev,
297 DL_FLAG_AUTOREMOVE_CONSUMER);
298
299 i2c_dev->common.i2c_speed = i2c_amd_get_bus_speed(pdev);
300
301 /* Setup i2c adapter description */
302 i2c_dev->adap.owner = THIS_MODULE;
303 i2c_dev->adap.algo = &i2c_amd_algorithm;
304 i2c_dev->adap.quirks = &amd_i2c_dev_quirks;
305 i2c_dev->adap.dev.parent = &pdev->dev;
306 i2c_dev->adap.algo_data = i2c_dev;
307 i2c_dev->adap.timeout = AMD_I2C_TIMEOUT;
308 ACPI_COMPANION_SET(&i2c_dev->adap.dev, ACPI_COMPANION(&pdev->dev));
309 i2c_dev->adap.dev.of_node = pdev->dev.of_node;
310 snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
311 "AMD MP2 i2c bus %u", i2c_dev->common.bus_id);
312 i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
313
314 init_completion(&i2c_dev->cmd_complete);
315
316 /* Enable the bus */
317 if (i2c_amd_enable_set(i2c_dev, true))
318 dev_err(&pdev->dev, "initial bus enable failed\n");
319
320 /* Attach to the i2c layer */
321 ret = i2c_add_adapter(&i2c_dev->adap);
322
323 amd_mp2_pm_runtime_put(mp2_dev);
324
325 if (ret < 0)
326 dev_err(&pdev->dev, "i2c add adapter failed = %d\n", ret);
327
328 return ret;
329}
330
331static int i2c_amd_remove(struct platform_device *pdev)
332{
333 struct amd_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
334 struct amd_i2c_common *i2c_common = &i2c_dev->common;
335
336 i2c_lock_bus(&i2c_dev->adap, I2C_LOCK_ROOT_ADAPTER);
337
338 i2c_amd_enable_set(i2c_dev, false);
339 amd_mp2_unregister_cb(i2c_common);
340 i2c_common->mp2_dev = NULL;
341
342 i2c_unlock_bus(&i2c_dev->adap, I2C_LOCK_ROOT_ADAPTER);
343
344 i2c_del_adapter(&i2c_dev->adap);
345 return 0;
346}
347
348static const struct acpi_device_id i2c_amd_acpi_match[] = {
349 { "AMDI0011" },
350 { },
351};
352MODULE_DEVICE_TABLE(acpi, i2c_amd_acpi_match);
353
354static struct platform_driver i2c_amd_plat_driver = {
355 .probe = i2c_amd_probe,
356 .remove = i2c_amd_remove,
357 .driver = {
358 .name = "i2c_amd_mp2",
359 .acpi_match_table = ACPI_PTR(i2c_amd_acpi_match),
360 },
361};
362module_platform_driver(i2c_amd_plat_driver);
363
364MODULE_DESCRIPTION("AMD(R) MP2 I2C Platform Driver");
365MODULE_AUTHOR("Nehal Shah <nehal-bakulchandra.shah@amd.com>");
366MODULE_AUTHOR("Elie Morisse <syniurge@gmail.com>");
367MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/i2c/busses/i2c-amd-mp2.h b/drivers/i2c/busses/i2c-amd-mp2.h
new file mode 100644
index 000000000000..058362edebaa
--- /dev/null
+++ b/drivers/i2c/busses/i2c-amd-mp2.h
@@ -0,0 +1,219 @@
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/*
3 * AMD MP2 I2C adapter driver
4 *
5 * Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
6 * Elie Morisse <syniurge@gmail.com>
7 */
8
9#ifndef I2C_AMD_PCI_MP2_H
10#define I2C_AMD_PCI_MP2_H
11
12#include <linux/i2c.h>
13#include <linux/pci.h>
14#include <linux/pm_runtime.h>
15
16#define PCI_DEVICE_ID_AMD_MP2 0x15E6
17
18struct amd_i2c_common;
19struct amd_mp2_dev;
20
21enum {
22 /* MP2 C2P Message Registers */
23 AMD_C2P_MSG0 = 0x10500, /* MP2 Message for I2C0 */
24 AMD_C2P_MSG1 = 0x10504, /* MP2 Message for I2C1 */
25 AMD_C2P_MSG2 = 0x10508, /* DRAM Address Lo / Data 0 */
26 AMD_C2P_MSG3 = 0x1050c, /* DRAM Address HI / Data 1 */
27 AMD_C2P_MSG4 = 0x10510, /* Data 2 */
28 AMD_C2P_MSG5 = 0x10514, /* Data 3 */
29 AMD_C2P_MSG6 = 0x10518, /* Data 4 */
30 AMD_C2P_MSG7 = 0x1051c, /* Data 5 */
31 AMD_C2P_MSG8 = 0x10520, /* Data 6 */
32 AMD_C2P_MSG9 = 0x10524, /* Data 7 */
33
34 /* MP2 P2C Message Registers */
35 AMD_P2C_MSG0 = 0x10680, /* Do not use */
36 AMD_P2C_MSG1 = 0x10684, /* I2C0 interrupt register */
37 AMD_P2C_MSG2 = 0x10688, /* I2C1 interrupt register */
38 AMD_P2C_MSG3 = 0x1068C, /* MP2 debug info */
39 AMD_P2C_MSG_INTEN = 0x10690, /* MP2 interrupt gen register */
40 AMD_P2C_MSG_INTSTS = 0x10694, /* Interrupt status */
41};
42
43/* Command register data structures */
44
45#define i2c_none (-1)
46enum i2c_cmd {
47 i2c_read = 0,
48 i2c_write,
49 i2c_enable,
50 i2c_disable,
51 number_of_sensor_discovered,
52 is_mp2_active,
53 invalid_cmd = 0xF,
54};
55
56enum speed_enum {
57 speed100k = 0,
58 speed400k = 1,
59 speed1000k = 2,
60 speed1400k = 3,
61 speed3400k = 4
62};
63
64enum mem_type {
65 use_dram = 0,
66 use_c2pmsg = 1,
67};
68
69/**
70 * union i2c_cmd_base : bit access of C2P commands
71 * @i2c_cmd: bit 0..3 i2c R/W command
72 * @bus_id: bit 4..7 i2c bus index
73 * @slave_addr: bit 8..15 slave address
74 * @length: bit 16..27 read/write length
75 * @i2c_speed: bit 28..30 bus speed
76 * @mem_type: bit 31 0-DRAM; 1-C2P msg o/p
77 */
78union i2c_cmd_base {
79 u32 ul;
80 struct {
81 enum i2c_cmd i2c_cmd : 4;
82 u8 bus_id : 4;
83 u32 slave_addr : 8;
84 u32 length : 12;
85 enum speed_enum i2c_speed : 3;
86 enum mem_type mem_type : 1;
87 } s;
88};
89
90enum response_type {
91 invalid_response = 0,
92 command_success = 1,
93 command_failed = 2,
94};
95
96enum status_type {
97 i2c_readcomplete_event = 0,
98 i2c_readfail_event = 1,
99 i2c_writecomplete_event = 2,
100 i2c_writefail_event = 3,
101 i2c_busenable_complete = 4,
102 i2c_busenable_failed = 5,
103 i2c_busdisable_complete = 6,
104 i2c_busdisable_failed = 7,
105 invalid_data_length = 8,
106 invalid_slave_address = 9,
107 invalid_i2cbus_id = 10,
108 invalid_dram_addr = 11,
109 invalid_command = 12,
110 mp2_active = 13,
111 numberof_sensors_discovered_resp = 14,
112 i2c_bus_notinitialized
113};
114
115/**
116 * union i2c_event : bit access of P2C events
117 * @response: bit 0..1 i2c response type
118 * @status: bit 2..6 status_type
119 * @mem_type: bit 7 0-DRAM; 1-C2P msg o/p
120 * @bus_id: bit 8..11 i2c bus id
121 * @length: bit 12..23 message length
122 * @slave_addr: bit 24-31 slave address
123 */
124union i2c_event {
125 u32 ul;
126 struct {
127 enum response_type response : 2;
128 enum status_type status : 5;
129 enum mem_type mem_type : 1;
130 u8 bus_id : 4;
131 u32 length : 12;
132 u32 slave_addr : 8;
133 } r;
134};
135
136/**
137 * struct amd_i2c_common - per bus/i2c adapter context, shared
138 * between the pci and the platform driver
139 * @eventval: MP2 event value set by the IRQ handler
140 * @mp2_dev: MP2 pci device this adapter is part of
141 * @msg: i2c message
142 * @cmd_completion: function called by the IRQ handler to signal
143 * the platform driver
144 * @reqcmd: requested i2c command type
145 * @cmd_success: set to true if the MP2 responded to a command with
146 * the expected status and response type
147 * @bus_id: bus index
148 * @i2c_speed: i2c bus speed determined by the slowest slave
149 * @dma_buf: if msg length > 32, holds the DMA buffer virtual address
150 * @dma_addr: if msg length > 32, holds the DMA buffer address
151 */
152struct amd_i2c_common {
153 union i2c_event eventval;
154 struct amd_mp2_dev *mp2_dev;
155 struct i2c_msg *msg;
156 void (*cmd_completion)(struct amd_i2c_common *i2c_common);
157 enum i2c_cmd reqcmd;
158 u8 cmd_success;
159 u8 bus_id;
160 enum speed_enum i2c_speed;
161 u8 *dma_buf;
162 dma_addr_t dma_addr;
163#ifdef CONFIG_PM
164 int (*suspend)(struct amd_i2c_common *i2c_common);
165 int (*resume)(struct amd_i2c_common *i2c_common);
166#endif /* CONFIG_PM */
167};
168
169/**
170 * struct amd_mp2_dev - per PCI device context
171 * @pci_dev: PCI driver node
172 * @busses: MP2 devices may have up to two busses,
173 * each bus corresponding to an i2c adapter
174 * @mmio: iommapped registers
175 * @c2p_lock: controls access to the C2P mailbox shared between
176 * the two adapters
177 * @c2p_lock_busid: id of the adapter which locked c2p_lock
178 */
179struct amd_mp2_dev {
180 struct pci_dev *pci_dev;
181 struct amd_i2c_common *busses[2];
182 void __iomem *mmio;
183 struct mutex c2p_lock;
184 u8 c2p_lock_busid;
185 unsigned int probed;
186};
187
188#define ndev_pdev(ndev) ((ndev)->pci_dev)
189#define ndev_name(ndev) pci_name(ndev_pdev(ndev))
190#define ndev_dev(ndev) (&ndev_pdev(ndev)->dev)
191#define work_amd_i2c_common(__work) \
192 container_of(__work, struct amd_i2c_common, work.work)
193
194/* PCIe communication driver */
195
196int amd_mp2_rw(struct amd_i2c_common *i2c_common, enum i2c_cmd reqcmd);
197int amd_mp2_bus_enable_set(struct amd_i2c_common *i2c_common, bool enable);
198
199void amd_mp2_process_event(struct amd_i2c_common *i2c_common);
200
201void amd_mp2_rw_timeout(struct amd_i2c_common *i2c_common);
202
203int amd_mp2_register_cb(struct amd_i2c_common *i2c_common);
204int amd_mp2_unregister_cb(struct amd_i2c_common *i2c_common);
205
206struct amd_mp2_dev *amd_mp2_find_device(void);
207
208static inline void amd_mp2_pm_runtime_get(struct amd_mp2_dev *mp2_dev)
209{
210 pm_runtime_get_sync(&mp2_dev->pci_dev->dev);
211}
212
213static inline void amd_mp2_pm_runtime_put(struct amd_mp2_dev *mp2_dev)
214{
215 pm_runtime_mark_last_busy(&mp2_dev->pci_dev->dev);
216 pm_runtime_put_autosuspend(&mp2_dev->pci_dev->dev);
217}
218
219#endif
diff --git a/drivers/i2c/busses/i2c-at91-core.c b/drivers/i2c/busses/i2c-at91-core.c
new file mode 100644
index 000000000000..8d55cdd69ff4
--- /dev/null
+++ b/drivers/i2c/busses/i2c-at91-core.c
@@ -0,0 +1,376 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
4 *
5 * Copyright (C) 2011 Weinmann Medical GmbH
6 * Author: Nikolaus Voss <n.voss@weinmann.de>
7 *
8 * Evolved from original work by:
9 * Copyright (C) 2004 Rick Bronson
10 * Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
11 *
12 * Borrowed heavily from original work by:
13 * Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
14 */
15
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/i2c.h>
19#include <linux/io.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/pinctrl/consumer.h>
26
27#include "i2c-at91.h"
28
29unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
30{
31 return readl_relaxed(dev->base + reg);
32}
33
34void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
35{
36 writel_relaxed(val, dev->base + reg);
37}
38
39void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
40{
41 at91_twi_write(dev, AT91_TWI_IDR, AT91_TWI_INT_MASK);
42}
43
44void at91_twi_irq_save(struct at91_twi_dev *dev)
45{
46 dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & AT91_TWI_INT_MASK;
47 at91_disable_twi_interrupts(dev);
48}
49
50void at91_twi_irq_restore(struct at91_twi_dev *dev)
51{
52 at91_twi_write(dev, AT91_TWI_IER, dev->imr);
53}
54
55void at91_init_twi_bus(struct at91_twi_dev *dev)
56{
57 at91_disable_twi_interrupts(dev);
58 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
59 if (dev->slave_detected)
60 at91_init_twi_bus_slave(dev);
61 else
62 at91_init_twi_bus_master(dev);
63}
64
65static struct at91_twi_pdata at91rm9200_config = {
66 .clk_max_div = 5,
67 .clk_offset = 3,
68 .has_unre_flag = true,
69 .has_alt_cmd = false,
70 .has_hold_field = false,
71};
72
73static struct at91_twi_pdata at91sam9261_config = {
74 .clk_max_div = 5,
75 .clk_offset = 4,
76 .has_unre_flag = false,
77 .has_alt_cmd = false,
78 .has_hold_field = false,
79};
80
81static struct at91_twi_pdata at91sam9260_config = {
82 .clk_max_div = 7,
83 .clk_offset = 4,
84 .has_unre_flag = false,
85 .has_alt_cmd = false,
86 .has_hold_field = false,
87};
88
89static struct at91_twi_pdata at91sam9g20_config = {
90 .clk_max_div = 7,
91 .clk_offset = 4,
92 .has_unre_flag = false,
93 .has_alt_cmd = false,
94 .has_hold_field = false,
95};
96
97static struct at91_twi_pdata at91sam9g10_config = {
98 .clk_max_div = 7,
99 .clk_offset = 4,
100 .has_unre_flag = false,
101 .has_alt_cmd = false,
102 .has_hold_field = false,
103};
104
105static const struct platform_device_id at91_twi_devtypes[] = {
106 {
107 .name = "i2c-at91rm9200",
108 .driver_data = (unsigned long) &at91rm9200_config,
109 }, {
110 .name = "i2c-at91sam9261",
111 .driver_data = (unsigned long) &at91sam9261_config,
112 }, {
113 .name = "i2c-at91sam9260",
114 .driver_data = (unsigned long) &at91sam9260_config,
115 }, {
116 .name = "i2c-at91sam9g20",
117 .driver_data = (unsigned long) &at91sam9g20_config,
118 }, {
119 .name = "i2c-at91sam9g10",
120 .driver_data = (unsigned long) &at91sam9g10_config,
121 }, {
122 /* sentinel */
123 }
124};
125
126#if defined(CONFIG_OF)
127static struct at91_twi_pdata at91sam9x5_config = {
128 .clk_max_div = 7,
129 .clk_offset = 4,
130 .has_unre_flag = false,
131 .has_alt_cmd = false,
132 .has_hold_field = false,
133};
134
135static struct at91_twi_pdata sama5d4_config = {
136 .clk_max_div = 7,
137 .clk_offset = 4,
138 .has_unre_flag = false,
139 .has_alt_cmd = false,
140 .has_hold_field = true,
141};
142
143static struct at91_twi_pdata sama5d2_config = {
144 .clk_max_div = 7,
145 .clk_offset = 4,
146 .has_unre_flag = true,
147 .has_alt_cmd = true,
148 .has_hold_field = true,
149};
150
151static const struct of_device_id atmel_twi_dt_ids[] = {
152 {
153 .compatible = "atmel,at91rm9200-i2c",
154 .data = &at91rm9200_config,
155 }, {
156 .compatible = "atmel,at91sam9260-i2c",
157 .data = &at91sam9260_config,
158 }, {
159 .compatible = "atmel,at91sam9261-i2c",
160 .data = &at91sam9261_config,
161 }, {
162 .compatible = "atmel,at91sam9g20-i2c",
163 .data = &at91sam9g20_config,
164 }, {
165 .compatible = "atmel,at91sam9g10-i2c",
166 .data = &at91sam9g10_config,
167 }, {
168 .compatible = "atmel,at91sam9x5-i2c",
169 .data = &at91sam9x5_config,
170 }, {
171 .compatible = "atmel,sama5d4-i2c",
172 .data = &sama5d4_config,
173 }, {
174 .compatible = "atmel,sama5d2-i2c",
175 .data = &sama5d2_config,
176 }, {
177 /* sentinel */
178 }
179};
180MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
181#endif
182
183static struct at91_twi_pdata *at91_twi_get_driver_data(
184 struct platform_device *pdev)
185{
186 if (pdev->dev.of_node) {
187 const struct of_device_id *match;
188 match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
189 if (!match)
190 return NULL;
191 return (struct at91_twi_pdata *)match->data;
192 }
193 return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
194}
195
196static int at91_twi_probe(struct platform_device *pdev)
197{
198 struct at91_twi_dev *dev;
199 struct resource *mem;
200 int rc;
201 u32 phy_addr;
202
203 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
204 if (!dev)
205 return -ENOMEM;
206
207 dev->dev = &pdev->dev;
208
209 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
210 if (!mem)
211 return -ENODEV;
212 phy_addr = mem->start;
213
214 dev->pdata = at91_twi_get_driver_data(pdev);
215 if (!dev->pdata)
216 return -ENODEV;
217
218 dev->base = devm_ioremap_resource(&pdev->dev, mem);
219 if (IS_ERR(dev->base))
220 return PTR_ERR(dev->base);
221
222 dev->irq = platform_get_irq(pdev, 0);
223 if (dev->irq < 0)
224 return dev->irq;
225
226 platform_set_drvdata(pdev, dev);
227
228 dev->clk = devm_clk_get(dev->dev, NULL);
229 if (IS_ERR(dev->clk)) {
230 dev_err(dev->dev, "no clock defined\n");
231 return -ENODEV;
232 }
233 clk_prepare_enable(dev->clk);
234
235 snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
236 i2c_set_adapdata(&dev->adapter, dev);
237 dev->adapter.owner = THIS_MODULE;
238 dev->adapter.class = I2C_CLASS_DEPRECATED;
239 dev->adapter.dev.parent = dev->dev;
240 dev->adapter.nr = pdev->id;
241 dev->adapter.timeout = AT91_I2C_TIMEOUT;
242 dev->adapter.dev.of_node = pdev->dev.of_node;
243
244 dev->slave_detected = i2c_detect_slave_mode(&pdev->dev);
245
246 if (dev->slave_detected)
247 rc = at91_twi_probe_slave(pdev, phy_addr, dev);
248 else
249 rc = at91_twi_probe_master(pdev, phy_addr, dev);
250 if (rc)
251 return rc;
252
253 at91_init_twi_bus(dev);
254
255 pm_runtime_set_autosuspend_delay(dev->dev, AUTOSUSPEND_TIMEOUT);
256 pm_runtime_use_autosuspend(dev->dev);
257 pm_runtime_set_active(dev->dev);
258 pm_runtime_enable(dev->dev);
259
260 rc = i2c_add_numbered_adapter(&dev->adapter);
261 if (rc) {
262 clk_disable_unprepare(dev->clk);
263
264 pm_runtime_disable(dev->dev);
265 pm_runtime_set_suspended(dev->dev);
266
267 return rc;
268 }
269
270 dev_info(dev->dev, "AT91 i2c bus driver (hw version: %#x).\n",
271 at91_twi_read(dev, AT91_TWI_VER));
272 return 0;
273}
274
275static int at91_twi_remove(struct platform_device *pdev)
276{
277 struct at91_twi_dev *dev = platform_get_drvdata(pdev);
278
279 i2c_del_adapter(&dev->adapter);
280 clk_disable_unprepare(dev->clk);
281
282 pm_runtime_disable(dev->dev);
283 pm_runtime_set_suspended(dev->dev);
284
285 return 0;
286}
287
288#ifdef CONFIG_PM
289
290static int at91_twi_runtime_suspend(struct device *dev)
291{
292 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
293
294 clk_disable_unprepare(twi_dev->clk);
295
296 pinctrl_pm_select_sleep_state(dev);
297
298 return 0;
299}
300
301static int at91_twi_runtime_resume(struct device *dev)
302{
303 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
304
305 pinctrl_pm_select_default_state(dev);
306
307 return clk_prepare_enable(twi_dev->clk);
308}
309
310static int at91_twi_suspend_noirq(struct device *dev)
311{
312 if (!pm_runtime_status_suspended(dev))
313 at91_twi_runtime_suspend(dev);
314
315 return 0;
316}
317
318static int at91_twi_resume_noirq(struct device *dev)
319{
320 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
321 int ret;
322
323 if (!pm_runtime_status_suspended(dev)) {
324 ret = at91_twi_runtime_resume(dev);
325 if (ret)
326 return ret;
327 }
328
329 pm_runtime_mark_last_busy(dev);
330 pm_request_autosuspend(dev);
331
332 at91_init_twi_bus(twi_dev);
333
334 return 0;
335}
336
337static const struct dev_pm_ops at91_twi_pm = {
338 .suspend_noirq = at91_twi_suspend_noirq,
339 .resume_noirq = at91_twi_resume_noirq,
340 .runtime_suspend = at91_twi_runtime_suspend,
341 .runtime_resume = at91_twi_runtime_resume,
342};
343
344#define at91_twi_pm_ops (&at91_twi_pm)
345#else
346#define at91_twi_pm_ops NULL
347#endif
348
349static struct platform_driver at91_twi_driver = {
350 .probe = at91_twi_probe,
351 .remove = at91_twi_remove,
352 .id_table = at91_twi_devtypes,
353 .driver = {
354 .name = "at91_i2c",
355 .of_match_table = of_match_ptr(atmel_twi_dt_ids),
356 .pm = at91_twi_pm_ops,
357 },
358};
359
360static int __init at91_twi_init(void)
361{
362 return platform_driver_register(&at91_twi_driver);
363}
364
365static void __exit at91_twi_exit(void)
366{
367 platform_driver_unregister(&at91_twi_driver);
368}
369
370subsys_initcall(at91_twi_init);
371module_exit(at91_twi_exit);
372
373MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>");
374MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
375MODULE_LICENSE("GPL");
376MODULE_ALIAS("platform:at91_i2c");
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91-master.c
index 3f3e8b3bf5ff..e87232f2e708 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91-master.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * i2c Support for Atmel's AT91 Two-Wire Interface (TWI) 3 * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
3 * 4 *
@@ -10,11 +11,6 @@
10 * 11 *
11 * Borrowed heavily from original work by: 12 * Borrowed heavily from original work by:
12 * Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com> 13 * Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 */ 14 */
19 15
20#include <linux/clk.h> 16#include <linux/clk.h>
@@ -25,159 +21,16 @@
25#include <linux/i2c.h> 21#include <linux/i2c.h>
26#include <linux/interrupt.h> 22#include <linux/interrupt.h>
27#include <linux/io.h> 23#include <linux/io.h>
28#include <linux/module.h>
29#include <linux/of.h> 24#include <linux/of.h>
30#include <linux/of_device.h> 25#include <linux/of_device.h>
31#include <linux/platform_device.h> 26#include <linux/platform_device.h>
32#include <linux/slab.h>
33#include <linux/platform_data/dma-atmel.h> 27#include <linux/platform_data/dma-atmel.h>
34#include <linux/pm_runtime.h> 28#include <linux/pm_runtime.h>
35#include <linux/pinctrl/consumer.h>
36
37#define DEFAULT_TWI_CLK_HZ 100000 /* max 400 Kbits/s */
38#define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */
39#define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if transfer size is bigger than this threshold */
40#define AUTOSUSPEND_TIMEOUT 2000
41#define AT91_I2C_MAX_ALT_CMD_DATA_SIZE 256
42
43/* AT91 TWI register definitions */
44#define AT91_TWI_CR 0x0000 /* Control Register */
45#define AT91_TWI_START BIT(0) /* Send a Start Condition */
46#define AT91_TWI_STOP BIT(1) /* Send a Stop Condition */
47#define AT91_TWI_MSEN BIT(2) /* Master Transfer Enable */
48#define AT91_TWI_MSDIS BIT(3) /* Master Transfer Disable */
49#define AT91_TWI_SVEN BIT(4) /* Slave Transfer Enable */
50#define AT91_TWI_SVDIS BIT(5) /* Slave Transfer Disable */
51#define AT91_TWI_QUICK BIT(6) /* SMBus quick command */
52#define AT91_TWI_SWRST BIT(7) /* Software Reset */
53#define AT91_TWI_ACMEN BIT(16) /* Alternative Command Mode Enable */
54#define AT91_TWI_ACMDIS BIT(17) /* Alternative Command Mode Disable */
55#define AT91_TWI_THRCLR BIT(24) /* Transmit Holding Register Clear */
56#define AT91_TWI_RHRCLR BIT(25) /* Receive Holding Register Clear */
57#define AT91_TWI_LOCKCLR BIT(26) /* Lock Clear */
58#define AT91_TWI_FIFOEN BIT(28) /* FIFO Enable */
59#define AT91_TWI_FIFODIS BIT(29) /* FIFO Disable */
60
61#define AT91_TWI_MMR 0x0004 /* Master Mode Register */
62#define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */
63#define AT91_TWI_MREAD BIT(12) /* Master Read Direction */
64
65#define AT91_TWI_IADR 0x000c /* Internal Address Register */
66
67#define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */
68#define AT91_TWI_CWGR_HOLD_MAX 0x1f
69#define AT91_TWI_CWGR_HOLD(x) (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
70
71#define AT91_TWI_SR 0x0020 /* Status Register */
72#define AT91_TWI_TXCOMP BIT(0) /* Transmission Complete */
73#define AT91_TWI_RXRDY BIT(1) /* Receive Holding Register Ready */
74#define AT91_TWI_TXRDY BIT(2) /* Transmit Holding Register Ready */
75#define AT91_TWI_OVRE BIT(6) /* Overrun Error */
76#define AT91_TWI_UNRE BIT(7) /* Underrun Error */
77#define AT91_TWI_NACK BIT(8) /* Not Acknowledged */
78#define AT91_TWI_LOCK BIT(23) /* TWI Lock due to Frame Errors */
79
80#define AT91_TWI_INT_MASK \
81 (AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK)
82
83#define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */
84#define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */
85#define AT91_TWI_IMR 0x002c /* Interrupt Mask Register */
86#define AT91_TWI_RHR 0x0030 /* Receive Holding Register */
87#define AT91_TWI_THR 0x0034 /* Transmit Holding Register */
88
89#define AT91_TWI_ACR 0x0040 /* Alternative Command Register */
90#define AT91_TWI_ACR_DATAL(len) ((len) & 0xff)
91#define AT91_TWI_ACR_DIR BIT(8)
92
93#define AT91_TWI_FMR 0x0050 /* FIFO Mode Register */
94#define AT91_TWI_FMR_TXRDYM(mode) (((mode) & 0x3) << 0)
95#define AT91_TWI_FMR_TXRDYM_MASK (0x3 << 0)
96#define AT91_TWI_FMR_RXRDYM(mode) (((mode) & 0x3) << 4)
97#define AT91_TWI_FMR_RXRDYM_MASK (0x3 << 4)
98#define AT91_TWI_ONE_DATA 0x0
99#define AT91_TWI_TWO_DATA 0x1
100#define AT91_TWI_FOUR_DATA 0x2
101
102#define AT91_TWI_FLR 0x0054 /* FIFO Level Register */
103
104#define AT91_TWI_FSR 0x0060 /* FIFO Status Register */
105#define AT91_TWI_FIER 0x0064 /* FIFO Interrupt Enable Register */
106#define AT91_TWI_FIDR 0x0068 /* FIFO Interrupt Disable Register */
107#define AT91_TWI_FIMR 0x006c /* FIFO Interrupt Mask Register */
108
109#define AT91_TWI_VER 0x00fc /* Version Register */
110
111struct at91_twi_pdata {
112 unsigned clk_max_div;
113 unsigned clk_offset;
114 bool has_unre_flag;
115 bool has_alt_cmd;
116 bool has_hold_field;
117 struct at_dma_slave dma_slave;
118};
119
120struct at91_twi_dma {
121 struct dma_chan *chan_rx;
122 struct dma_chan *chan_tx;
123 struct scatterlist sg[2];
124 struct dma_async_tx_descriptor *data_desc;
125 enum dma_data_direction direction;
126 bool buf_mapped;
127 bool xfer_in_progress;
128};
129 29
130struct at91_twi_dev { 30#include "i2c-at91.h"
131 struct device *dev;
132 void __iomem *base;
133 struct completion cmd_complete;
134 struct clk *clk;
135 u8 *buf;
136 size_t buf_len;
137 struct i2c_msg *msg;
138 int irq;
139 unsigned imr;
140 unsigned transfer_status;
141 struct i2c_adapter adapter;
142 unsigned twi_cwgr_reg;
143 struct at91_twi_pdata *pdata;
144 bool use_dma;
145 bool use_alt_cmd;
146 bool recv_len_abort;
147 u32 fifo_size;
148 struct at91_twi_dma dma;
149};
150
151static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
152{
153 return readl_relaxed(dev->base + reg);
154}
155
156static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
157{
158 writel_relaxed(val, dev->base + reg);
159}
160
161static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
162{
163 at91_twi_write(dev, AT91_TWI_IDR, AT91_TWI_INT_MASK);
164}
165 31
166static void at91_twi_irq_save(struct at91_twi_dev *dev) 32void at91_init_twi_bus_master(struct at91_twi_dev *dev)
167{ 33{
168 dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & AT91_TWI_INT_MASK;
169 at91_disable_twi_interrupts(dev);
170}
171
172static void at91_twi_irq_restore(struct at91_twi_dev *dev)
173{
174 at91_twi_write(dev, AT91_TWI_IER, dev->imr);
175}
176
177static void at91_init_twi_bus(struct at91_twi_dev *dev)
178{
179 at91_disable_twi_interrupts(dev);
180 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
181 /* FIFO should be enabled immediately after the software reset */ 34 /* FIFO should be enabled immediately after the software reset */
182 if (dev->fifo_size) 35 if (dev->fifo_size)
183 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_FIFOEN); 36 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_FIFOEN);
@@ -190,16 +43,18 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
190 * Calculate symmetric clock as stated in datasheet: 43 * Calculate symmetric clock as stated in datasheet:
191 * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset)) 44 * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset))
192 */ 45 */
193static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk) 46static void at91_calc_twi_clock(struct at91_twi_dev *dev)
194{ 47{
195 int ckdiv, cdiv, div, hold = 0; 48 int ckdiv, cdiv, div, hold = 0;
196 struct at91_twi_pdata *pdata = dev->pdata; 49 struct at91_twi_pdata *pdata = dev->pdata;
197 int offset = pdata->clk_offset; 50 int offset = pdata->clk_offset;
198 int max_ckdiv = pdata->clk_max_div; 51 int max_ckdiv = pdata->clk_max_div;
199 u32 twd_hold_time_ns = 0; 52 struct i2c_timings timings, *t = &timings;
53
54 i2c_parse_fw_timings(dev->dev, t, true);
200 55
201 div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk), 56 div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
202 2 * twi_clk) - offset); 57 2 * t->bus_freq_hz) - offset);
203 ckdiv = fls(div >> 8); 58 ckdiv = fls(div >> 8);
204 cdiv = div >> ckdiv; 59 cdiv = div >> ckdiv;
205 60
@@ -211,15 +66,12 @@ static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
211 } 66 }
212 67
213 if (pdata->has_hold_field) { 68 if (pdata->has_hold_field) {
214 of_property_read_u32(dev->dev->of_node, "i2c-sda-hold-time-ns",
215 &twd_hold_time_ns);
216
217 /* 69 /*
218 * hold time = HOLD + 3 x T_peripheral_clock 70 * hold time = HOLD + 3 x T_peripheral_clock
219 * Use clk rate in kHz to prevent overflows when computing 71 * Use clk rate in kHz to prevent overflows when computing
220 * hold. 72 * hold.
221 */ 73 */
222 hold = DIV_ROUND_UP(twd_hold_time_ns 74 hold = DIV_ROUND_UP(t->sda_hold_ns
223 * (clk_get_rate(dev->clk) / 1000), 1000000); 75 * (clk_get_rate(dev->clk) / 1000), 1000000);
224 hold -= 3; 76 hold -= 3;
225 if (hold < 0) 77 if (hold < 0)
@@ -236,7 +88,7 @@ static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
236 | AT91_TWI_CWGR_HOLD(hold); 88 | AT91_TWI_CWGR_HOLD(hold);
237 89
238 dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n", 90 dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n",
239 cdiv, ckdiv, hold, twd_hold_time_ns); 91 cdiv, ckdiv, hold, t->sda_hold_ns);
240} 92}
241 93
242static void at91_twi_dma_cleanup(struct at91_twi_dev *dev) 94static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
@@ -833,124 +685,6 @@ static const struct i2c_algorithm at91_twi_algorithm = {
833 .functionality = at91_twi_func, 685 .functionality = at91_twi_func,
834}; 686};
835 687
836static struct at91_twi_pdata at91rm9200_config = {
837 .clk_max_div = 5,
838 .clk_offset = 3,
839 .has_unre_flag = true,
840 .has_alt_cmd = false,
841 .has_hold_field = false,
842};
843
844static struct at91_twi_pdata at91sam9261_config = {
845 .clk_max_div = 5,
846 .clk_offset = 4,
847 .has_unre_flag = false,
848 .has_alt_cmd = false,
849 .has_hold_field = false,
850};
851
852static struct at91_twi_pdata at91sam9260_config = {
853 .clk_max_div = 7,
854 .clk_offset = 4,
855 .has_unre_flag = false,
856 .has_alt_cmd = false,
857 .has_hold_field = false,
858};
859
860static struct at91_twi_pdata at91sam9g20_config = {
861 .clk_max_div = 7,
862 .clk_offset = 4,
863 .has_unre_flag = false,
864 .has_alt_cmd = false,
865 .has_hold_field = false,
866};
867
868static struct at91_twi_pdata at91sam9g10_config = {
869 .clk_max_div = 7,
870 .clk_offset = 4,
871 .has_unre_flag = false,
872 .has_alt_cmd = false,
873 .has_hold_field = false,
874};
875
876static const struct platform_device_id at91_twi_devtypes[] = {
877 {
878 .name = "i2c-at91rm9200",
879 .driver_data = (unsigned long) &at91rm9200_config,
880 }, {
881 .name = "i2c-at91sam9261",
882 .driver_data = (unsigned long) &at91sam9261_config,
883 }, {
884 .name = "i2c-at91sam9260",
885 .driver_data = (unsigned long) &at91sam9260_config,
886 }, {
887 .name = "i2c-at91sam9g20",
888 .driver_data = (unsigned long) &at91sam9g20_config,
889 }, {
890 .name = "i2c-at91sam9g10",
891 .driver_data = (unsigned long) &at91sam9g10_config,
892 }, {
893 /* sentinel */
894 }
895};
896
897#if defined(CONFIG_OF)
898static struct at91_twi_pdata at91sam9x5_config = {
899 .clk_max_div = 7,
900 .clk_offset = 4,
901 .has_unre_flag = false,
902 .has_alt_cmd = false,
903 .has_hold_field = false,
904};
905
906static struct at91_twi_pdata sama5d4_config = {
907 .clk_max_div = 7,
908 .clk_offset = 4,
909 .has_unre_flag = false,
910 .has_alt_cmd = false,
911 .has_hold_field = true,
912};
913
914static struct at91_twi_pdata sama5d2_config = {
915 .clk_max_div = 7,
916 .clk_offset = 4,
917 .has_unre_flag = true,
918 .has_alt_cmd = true,
919 .has_hold_field = true,
920};
921
922static const struct of_device_id atmel_twi_dt_ids[] = {
923 {
924 .compatible = "atmel,at91rm9200-i2c",
925 .data = &at91rm9200_config,
926 } , {
927 .compatible = "atmel,at91sam9260-i2c",
928 .data = &at91sam9260_config,
929 } , {
930 .compatible = "atmel,at91sam9261-i2c",
931 .data = &at91sam9261_config,
932 } , {
933 .compatible = "atmel,at91sam9g20-i2c",
934 .data = &at91sam9g20_config,
935 } , {
936 .compatible = "atmel,at91sam9g10-i2c",
937 .data = &at91sam9g10_config,
938 }, {
939 .compatible = "atmel,at91sam9x5-i2c",
940 .data = &at91sam9x5_config,
941 }, {
942 .compatible = "atmel,sama5d4-i2c",
943 .data = &sama5d4_config,
944 }, {
945 .compatible = "atmel,sama5d2-i2c",
946 .data = &sama5d2_config,
947 }, {
948 /* sentinel */
949 }
950};
951MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
952#endif
953
954static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr) 688static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
955{ 689{
956 int ret = 0; 690 int ret = 0;
@@ -1033,74 +767,24 @@ error:
1033 return ret; 767 return ret;
1034} 768}
1035 769
1036static struct at91_twi_pdata *at91_twi_get_driver_data( 770int at91_twi_probe_master(struct platform_device *pdev,
1037 struct platform_device *pdev) 771 u32 phy_addr, struct at91_twi_dev *dev)
1038{ 772{
1039 if (pdev->dev.of_node) {
1040 const struct of_device_id *match;
1041 match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
1042 if (!match)
1043 return NULL;
1044 return (struct at91_twi_pdata *)match->data;
1045 }
1046 return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
1047}
1048
1049static int at91_twi_probe(struct platform_device *pdev)
1050{
1051 struct at91_twi_dev *dev;
1052 struct resource *mem;
1053 int rc; 773 int rc;
1054 u32 phy_addr;
1055 u32 bus_clk_rate;
1056 774
1057 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1058 if (!dev)
1059 return -ENOMEM;
1060 init_completion(&dev->cmd_complete); 775 init_completion(&dev->cmd_complete);
1061 dev->dev = &pdev->dev;
1062
1063 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1064 if (!mem)
1065 return -ENODEV;
1066 phy_addr = mem->start;
1067
1068 dev->pdata = at91_twi_get_driver_data(pdev);
1069 if (!dev->pdata)
1070 return -ENODEV;
1071
1072 dev->base = devm_ioremap_resource(&pdev->dev, mem);
1073 if (IS_ERR(dev->base))
1074 return PTR_ERR(dev->base);
1075
1076 dev->irq = platform_get_irq(pdev, 0);
1077 if (dev->irq < 0)
1078 return dev->irq;
1079 776
1080 rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0, 777 rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0,
1081 dev_name(dev->dev), dev); 778 dev_name(dev->dev), dev);
1082 if (rc) { 779 if (rc) {
1083 dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc); 780 dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
1084 return rc; 781 return rc;
1085 } 782 }
1086 783
1087 platform_set_drvdata(pdev, dev);
1088
1089 dev->clk = devm_clk_get(dev->dev, NULL);
1090 if (IS_ERR(dev->clk)) {
1091 dev_err(dev->dev, "no clock defined\n");
1092 return -ENODEV;
1093 }
1094 rc = clk_prepare_enable(dev->clk);
1095 if (rc)
1096 return rc;
1097
1098 if (dev->dev->of_node) { 784 if (dev->dev->of_node) {
1099 rc = at91_twi_configure_dma(dev, phy_addr); 785 rc = at91_twi_configure_dma(dev, phy_addr);
1100 if (rc == -EPROBE_DEFER) { 786 if (rc == -EPROBE_DEFER)
1101 clk_disable_unprepare(dev->clk);
1102 return rc; 787 return rc;
1103 }
1104 } 788 }
1105 789
1106 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size", 790 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
@@ -1108,144 +792,10 @@ static int at91_twi_probe(struct platform_device *pdev)
1108 dev_info(dev->dev, "Using FIFO (%u data)\n", dev->fifo_size); 792 dev_info(dev->dev, "Using FIFO (%u data)\n", dev->fifo_size);
1109 } 793 }
1110 794
1111 rc = of_property_read_u32(dev->dev->of_node, "clock-frequency", 795 at91_calc_twi_clock(dev);
1112 &bus_clk_rate);
1113 if (rc)
1114 bus_clk_rate = DEFAULT_TWI_CLK_HZ;
1115
1116 at91_calc_twi_clock(dev, bus_clk_rate);
1117 at91_init_twi_bus(dev);
1118 796
1119 snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
1120 i2c_set_adapdata(&dev->adapter, dev);
1121 dev->adapter.owner = THIS_MODULE;
1122 dev->adapter.class = I2C_CLASS_DEPRECATED;
1123 dev->adapter.algo = &at91_twi_algorithm; 797 dev->adapter.algo = &at91_twi_algorithm;
1124 dev->adapter.quirks = &at91_twi_quirks; 798 dev->adapter.quirks = &at91_twi_quirks;
1125 dev->adapter.dev.parent = dev->dev;
1126 dev->adapter.nr = pdev->id;
1127 dev->adapter.timeout = AT91_I2C_TIMEOUT;
1128 dev->adapter.dev.of_node = pdev->dev.of_node;
1129
1130 pm_runtime_set_autosuspend_delay(dev->dev, AUTOSUSPEND_TIMEOUT);
1131 pm_runtime_use_autosuspend(dev->dev);
1132 pm_runtime_set_active(dev->dev);
1133 pm_runtime_enable(dev->dev);
1134
1135 rc = i2c_add_numbered_adapter(&dev->adapter);
1136 if (rc) {
1137 clk_disable_unprepare(dev->clk);
1138
1139 pm_runtime_disable(dev->dev);
1140 pm_runtime_set_suspended(dev->dev);
1141
1142 return rc;
1143 }
1144
1145 dev_info(dev->dev, "AT91 i2c bus driver (hw version: %#x).\n",
1146 at91_twi_read(dev, AT91_TWI_VER));
1147 return 0;
1148}
1149
1150static int at91_twi_remove(struct platform_device *pdev)
1151{
1152 struct at91_twi_dev *dev = platform_get_drvdata(pdev);
1153
1154 i2c_del_adapter(&dev->adapter);
1155 clk_disable_unprepare(dev->clk);
1156
1157 pm_runtime_disable(dev->dev);
1158 pm_runtime_set_suspended(dev->dev);
1159
1160 return 0;
1161}
1162
1163#ifdef CONFIG_PM
1164
1165static int at91_twi_runtime_suspend(struct device *dev)
1166{
1167 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
1168
1169 clk_disable_unprepare(twi_dev->clk);
1170
1171 pinctrl_pm_select_sleep_state(dev);
1172
1173 return 0;
1174}
1175
1176static int at91_twi_runtime_resume(struct device *dev)
1177{
1178 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
1179
1180 pinctrl_pm_select_default_state(dev);
1181
1182 return clk_prepare_enable(twi_dev->clk);
1183}
1184
1185static int at91_twi_suspend_noirq(struct device *dev)
1186{
1187 if (!pm_runtime_status_suspended(dev))
1188 at91_twi_runtime_suspend(dev);
1189
1190 return 0;
1191}
1192
1193static int at91_twi_resume_noirq(struct device *dev)
1194{
1195 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
1196 int ret;
1197
1198 if (!pm_runtime_status_suspended(dev)) {
1199 ret = at91_twi_runtime_resume(dev);
1200 if (ret)
1201 return ret;
1202 }
1203
1204 pm_runtime_mark_last_busy(dev);
1205 pm_request_autosuspend(dev);
1206
1207 at91_init_twi_bus(twi_dev);
1208 799
1209 return 0; 800 return 0;
1210} 801}
1211
1212static const struct dev_pm_ops at91_twi_pm = {
1213 .suspend_noirq = at91_twi_suspend_noirq,
1214 .resume_noirq = at91_twi_resume_noirq,
1215 .runtime_suspend = at91_twi_runtime_suspend,
1216 .runtime_resume = at91_twi_runtime_resume,
1217};
1218
1219#define at91_twi_pm_ops (&at91_twi_pm)
1220#else
1221#define at91_twi_pm_ops NULL
1222#endif
1223
1224static struct platform_driver at91_twi_driver = {
1225 .probe = at91_twi_probe,
1226 .remove = at91_twi_remove,
1227 .id_table = at91_twi_devtypes,
1228 .driver = {
1229 .name = "at91_i2c",
1230 .of_match_table = of_match_ptr(atmel_twi_dt_ids),
1231 .pm = at91_twi_pm_ops,
1232 },
1233};
1234
1235static int __init at91_twi_init(void)
1236{
1237 return platform_driver_register(&at91_twi_driver);
1238}
1239
1240static void __exit at91_twi_exit(void)
1241{
1242 platform_driver_unregister(&at91_twi_driver);
1243}
1244
1245subsys_initcall(at91_twi_init);
1246module_exit(at91_twi_exit);
1247
1248MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>");
1249MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
1250MODULE_LICENSE("GPL");
1251MODULE_ALIAS("platform:at91_i2c");
diff --git a/drivers/i2c/busses/i2c-at91-slave.c b/drivers/i2c/busses/i2c-at91-slave.c
new file mode 100644
index 000000000000..d6eeea5166c0
--- /dev/null
+++ b/drivers/i2c/busses/i2c-at91-slave.c
@@ -0,0 +1,143 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * i2c slave support for Atmel's AT91 Two-Wire Interface (TWI)
4 *
5 * Copyright (C) 2017 Juergen Fitschen <me@jue.yt>
6 */
7
8#include <linux/err.h>
9#include <linux/i2c.h>
10#include <linux/interrupt.h>
11#include <linux/pm_runtime.h>
12
13#include "i2c-at91.h"
14
15static irqreturn_t atmel_twi_interrupt_slave(int irq, void *dev_id)
16{
17 struct at91_twi_dev *dev = dev_id;
18 const unsigned status = at91_twi_read(dev, AT91_TWI_SR);
19 const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR);
20 u8 value;
21
22 if (!irqstatus)
23 return IRQ_NONE;
24
25 /* slave address has been detected on I2C bus */
26 if (irqstatus & AT91_TWI_SVACC) {
27 if (status & AT91_TWI_SVREAD) {
28 i2c_slave_event(dev->slave,
29 I2C_SLAVE_READ_REQUESTED, &value);
30 writeb_relaxed(value, dev->base + AT91_TWI_THR);
31 at91_twi_write(dev, AT91_TWI_IER,
32 AT91_TWI_TXRDY | AT91_TWI_EOSACC);
33 } else {
34 i2c_slave_event(dev->slave,
35 I2C_SLAVE_WRITE_REQUESTED, &value);
36 at91_twi_write(dev, AT91_TWI_IER,
37 AT91_TWI_RXRDY | AT91_TWI_EOSACC);
38 }
39 at91_twi_write(dev, AT91_TWI_IDR, AT91_TWI_SVACC);
40 }
41
42 /* byte transmitted to remote master */
43 if (irqstatus & AT91_TWI_TXRDY) {
44 i2c_slave_event(dev->slave, I2C_SLAVE_READ_PROCESSED, &value);
45 writeb_relaxed(value, dev->base + AT91_TWI_THR);
46 }
47
48 /* byte received from remote master */
49 if (irqstatus & AT91_TWI_RXRDY) {
50 value = readb_relaxed(dev->base + AT91_TWI_RHR);
51 i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
52 }
53
54 /* master sent stop */
55 if (irqstatus & AT91_TWI_EOSACC) {
56 at91_twi_write(dev, AT91_TWI_IDR,
57 AT91_TWI_TXRDY | AT91_TWI_RXRDY | AT91_TWI_EOSACC);
58 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_SVACC);
59 i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &value);
60 }
61
62 return IRQ_HANDLED;
63}
64
65static int at91_reg_slave(struct i2c_client *slave)
66{
67 struct at91_twi_dev *dev = i2c_get_adapdata(slave->adapter);
68
69 if (dev->slave)
70 return -EBUSY;
71
72 if (slave->flags & I2C_CLIENT_TEN)
73 return -EAFNOSUPPORT;
74
75 /* Make sure twi_clk doesn't get turned off! */
76 pm_runtime_get_sync(dev->dev);
77
78 dev->slave = slave;
79 dev->smr = AT91_TWI_SMR_SADR(slave->addr);
80
81 at91_init_twi_bus(dev);
82 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_SVACC);
83
84 dev_info(dev->dev, "entered slave mode (ADR=%d)\n", slave->addr);
85
86 return 0;
87}
88
89static int at91_unreg_slave(struct i2c_client *slave)
90{
91 struct at91_twi_dev *dev = i2c_get_adapdata(slave->adapter);
92
93 WARN_ON(!dev->slave);
94
95 dev_info(dev->dev, "leaving slave mode\n");
96
97 dev->slave = NULL;
98 dev->smr = 0;
99
100 at91_init_twi_bus(dev);
101
102 pm_runtime_put(dev->dev);
103
104 return 0;
105}
106
107static u32 at91_twi_func(struct i2c_adapter *adapter)
108{
109 return I2C_FUNC_SLAVE | I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
110 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
111}
112
113static const struct i2c_algorithm at91_twi_algorithm_slave = {
114 .reg_slave = at91_reg_slave,
115 .unreg_slave = at91_unreg_slave,
116 .functionality = at91_twi_func,
117};
118
119int at91_twi_probe_slave(struct platform_device *pdev,
120 u32 phy_addr, struct at91_twi_dev *dev)
121{
122 int rc;
123
124 rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt_slave,
125 0, dev_name(dev->dev), dev);
126 if (rc) {
127 dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
128 return rc;
129 }
130
131 dev->adapter.algo = &at91_twi_algorithm_slave;
132
133 return 0;
134}
135
136void at91_init_twi_bus_slave(struct at91_twi_dev *dev)
137{
138 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSDIS);
139 if (dev->slave_detected && dev->smr) {
140 at91_twi_write(dev, AT91_TWI_SMR, dev->smr);
141 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVEN);
142 }
143}
diff --git a/drivers/i2c/busses/i2c-at91.h b/drivers/i2c/busses/i2c-at91.h
new file mode 100644
index 000000000000..499b506f6128
--- /dev/null
+++ b/drivers/i2c/busses/i2c-at91.h
@@ -0,0 +1,174 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
4 *
5 * Copyright (C) 2011 Weinmann Medical GmbH
6 * Author: Nikolaus Voss <n.voss@weinmann.de>
7 *
8 * Evolved from original work by:
9 * Copyright (C) 2004 Rick Bronson
10 * Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
11 *
12 * Borrowed heavily from original work by:
13 * Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
14 */
15
16#include <linux/clk.h>
17#include <linux/completion.h>
18#include <linux/dma-mapping.h>
19#include <linux/dmaengine.h>
20#include <linux/i2c.h>
21#include <linux/platform_data/dma-atmel.h>
22#include <linux/platform_device.h>
23
24#define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */
25#define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if transfer size is bigger than this threshold */
26#define AUTOSUSPEND_TIMEOUT 2000
27#define AT91_I2C_MAX_ALT_CMD_DATA_SIZE 256
28
29/* AT91 TWI register definitions */
30#define AT91_TWI_CR 0x0000 /* Control Register */
31#define AT91_TWI_START BIT(0) /* Send a Start Condition */
32#define AT91_TWI_STOP BIT(1) /* Send a Stop Condition */
33#define AT91_TWI_MSEN BIT(2) /* Master Transfer Enable */
34#define AT91_TWI_MSDIS BIT(3) /* Master Transfer Disable */
35#define AT91_TWI_SVEN BIT(4) /* Slave Transfer Enable */
36#define AT91_TWI_SVDIS BIT(5) /* Slave Transfer Disable */
37#define AT91_TWI_QUICK BIT(6) /* SMBus quick command */
38#define AT91_TWI_SWRST BIT(7) /* Software Reset */
39#define AT91_TWI_ACMEN BIT(16) /* Alternative Command Mode Enable */
40#define AT91_TWI_ACMDIS BIT(17) /* Alternative Command Mode Disable */
41#define AT91_TWI_THRCLR BIT(24) /* Transmit Holding Register Clear */
42#define AT91_TWI_RHRCLR BIT(25) /* Receive Holding Register Clear */
43#define AT91_TWI_LOCKCLR BIT(26) /* Lock Clear */
44#define AT91_TWI_FIFOEN BIT(28) /* FIFO Enable */
45#define AT91_TWI_FIFODIS BIT(29) /* FIFO Disable */
46
47#define AT91_TWI_MMR 0x0004 /* Master Mode Register */
48#define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */
49#define AT91_TWI_MREAD BIT(12) /* Master Read Direction */
50
51#define AT91_TWI_SMR 0x0008 /* Slave Mode Register */
52#define AT91_TWI_SMR_SADR_MAX 0x007f
53#define AT91_TWI_SMR_SADR(x) (((x) & AT91_TWI_SMR_SADR_MAX) << 16)
54
55#define AT91_TWI_IADR 0x000c /* Internal Address Register */
56
57#define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */
58#define AT91_TWI_CWGR_HOLD_MAX 0x1f
59#define AT91_TWI_CWGR_HOLD(x) (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
60
61#define AT91_TWI_SR 0x0020 /* Status Register */
62#define AT91_TWI_TXCOMP BIT(0) /* Transmission Complete */
63#define AT91_TWI_RXRDY BIT(1) /* Receive Holding Register Ready */
64#define AT91_TWI_TXRDY BIT(2) /* Transmit Holding Register Ready */
65#define AT91_TWI_SVREAD BIT(3) /* Slave Read */
66#define AT91_TWI_SVACC BIT(4) /* Slave Access */
67#define AT91_TWI_OVRE BIT(6) /* Overrun Error */
68#define AT91_TWI_UNRE BIT(7) /* Underrun Error */
69#define AT91_TWI_NACK BIT(8) /* Not Acknowledged */
70#define AT91_TWI_EOSACC BIT(11) /* End Of Slave Access */
71#define AT91_TWI_LOCK BIT(23) /* TWI Lock due to Frame Errors */
72
73#define AT91_TWI_INT_MASK \
74 (AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK \
75 | AT91_TWI_SVACC | AT91_TWI_EOSACC)
76
77#define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */
78#define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */
79#define AT91_TWI_IMR 0x002c /* Interrupt Mask Register */
80#define AT91_TWI_RHR 0x0030 /* Receive Holding Register */
81#define AT91_TWI_THR 0x0034 /* Transmit Holding Register */
82
83#define AT91_TWI_ACR 0x0040 /* Alternative Command Register */
84#define AT91_TWI_ACR_DATAL(len) ((len) & 0xff)
85#define AT91_TWI_ACR_DIR BIT(8)
86
87#define AT91_TWI_FMR 0x0050 /* FIFO Mode Register */
88#define AT91_TWI_FMR_TXRDYM(mode) (((mode) & 0x3) << 0)
89#define AT91_TWI_FMR_TXRDYM_MASK (0x3 << 0)
90#define AT91_TWI_FMR_RXRDYM(mode) (((mode) & 0x3) << 4)
91#define AT91_TWI_FMR_RXRDYM_MASK (0x3 << 4)
92#define AT91_TWI_ONE_DATA 0x0
93#define AT91_TWI_TWO_DATA 0x1
94#define AT91_TWI_FOUR_DATA 0x2
95
96#define AT91_TWI_FLR 0x0054 /* FIFO Level Register */
97
98#define AT91_TWI_FSR 0x0060 /* FIFO Status Register */
99#define AT91_TWI_FIER 0x0064 /* FIFO Interrupt Enable Register */
100#define AT91_TWI_FIDR 0x0068 /* FIFO Interrupt Disable Register */
101#define AT91_TWI_FIMR 0x006c /* FIFO Interrupt Mask Register */
102
103#define AT91_TWI_VER 0x00fc /* Version Register */
104
105struct at91_twi_pdata {
106 unsigned clk_max_div;
107 unsigned clk_offset;
108 bool has_unre_flag;
109 bool has_alt_cmd;
110 bool has_hold_field;
111 struct at_dma_slave dma_slave;
112};
113
114struct at91_twi_dma {
115 struct dma_chan *chan_rx;
116 struct dma_chan *chan_tx;
117 struct scatterlist sg[2];
118 struct dma_async_tx_descriptor *data_desc;
119 enum dma_data_direction direction;
120 bool buf_mapped;
121 bool xfer_in_progress;
122};
123
124struct at91_twi_dev {
125 struct device *dev;
126 void __iomem *base;
127 struct completion cmd_complete;
128 struct clk *clk;
129 u8 *buf;
130 size_t buf_len;
131 struct i2c_msg *msg;
132 int irq;
133 unsigned imr;
134 unsigned transfer_status;
135 struct i2c_adapter adapter;
136 unsigned twi_cwgr_reg;
137 struct at91_twi_pdata *pdata;
138 bool use_dma;
139 bool use_alt_cmd;
140 bool recv_len_abort;
141 u32 fifo_size;
142 struct at91_twi_dma dma;
143 bool slave_detected;
144#ifdef CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL
145 unsigned smr;
146 struct i2c_client *slave;
147#endif
148};
149
150unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg);
151void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val);
152void at91_disable_twi_interrupts(struct at91_twi_dev *dev);
153void at91_twi_irq_save(struct at91_twi_dev *dev);
154void at91_twi_irq_restore(struct at91_twi_dev *dev);
155void at91_init_twi_bus(struct at91_twi_dev *dev);
156
157void at91_init_twi_bus_master(struct at91_twi_dev *dev);
158int at91_twi_probe_master(struct platform_device *pdev, u32 phy_addr,
159 struct at91_twi_dev *dev);
160
161#ifdef CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL
162void at91_init_twi_bus_slave(struct at91_twi_dev *dev);
163int at91_twi_probe_slave(struct platform_device *pdev, u32 phy_addr,
164 struct at91_twi_dev *dev);
165
166#else
167static inline void at91_init_twi_bus_slave(struct at91_twi_dev *dev) {}
168static inline int at91_twi_probe_slave(struct platform_device *pdev,
169 u32 phy_addr, struct at91_twi_dev *dev)
170{
171 return -EINVAL;
172}
173
174#endif
diff --git a/drivers/i2c/busses/i2c-axxia.c b/drivers/i2c/busses/i2c-axxia.c
index bf564391091f..1c7b41f45c83 100644
--- a/drivers/i2c/busses/i2c-axxia.c
+++ b/drivers/i2c/busses/i2c-axxia.c
@@ -99,6 +99,7 @@
99 * @adapter: core i2c abstraction 99 * @adapter: core i2c abstraction
100 * @i2c_clk: clock reference for i2c input clock 100 * @i2c_clk: clock reference for i2c input clock
101 * @bus_clk_rate: current i2c bus clock rate 101 * @bus_clk_rate: current i2c bus clock rate
102 * @last: a flag indicating is this is last message in transfer
102 */ 103 */
103struct axxia_i2c_dev { 104struct axxia_i2c_dev {
104 void __iomem *base; 105 void __iomem *base;
@@ -112,6 +113,7 @@ struct axxia_i2c_dev {
112 struct i2c_adapter adapter; 113 struct i2c_adapter adapter;
113 struct clk *i2c_clk; 114 struct clk *i2c_clk;
114 u32 bus_clk_rate; 115 u32 bus_clk_rate;
116 bool last;
115}; 117};
116 118
117static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask) 119static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask)
@@ -324,15 +326,14 @@ static irqreturn_t axxia_i2c_isr(int irq, void *_dev)
324 /* Stop completed */ 326 /* Stop completed */
325 i2c_int_disable(idev, ~MST_STATUS_TSS); 327 i2c_int_disable(idev, ~MST_STATUS_TSS);
326 complete(&idev->msg_complete); 328 complete(&idev->msg_complete);
327 } else if (status & MST_STATUS_SNS) { 329 } else if (status & (MST_STATUS_SNS | MST_STATUS_SS)) {
328 /* Transfer done */ 330 /* Transfer done */
329 i2c_int_disable(idev, ~MST_STATUS_TSS); 331 int mask = idev->last ? ~0 : ~MST_STATUS_TSS;
332
333 i2c_int_disable(idev, mask);
330 if (i2c_m_rd(idev->msg_r) && idev->msg_xfrd_r < idev->msg_r->len) 334 if (i2c_m_rd(idev->msg_r) && idev->msg_xfrd_r < idev->msg_r->len)
331 axxia_i2c_empty_rx_fifo(idev); 335 axxia_i2c_empty_rx_fifo(idev);
332 complete(&idev->msg_complete); 336 complete(&idev->msg_complete);
333 } else if (status & MST_STATUS_SS) {
334 /* Auto/Sequence transfer done */
335 complete(&idev->msg_complete);
336 } else if (status & MST_STATUS_TSS) { 337 } else if (status & MST_STATUS_TSS) {
337 /* Transfer timeout */ 338 /* Transfer timeout */
338 idev->msg_err = -ETIMEDOUT; 339 idev->msg_err = -ETIMEDOUT;
@@ -405,6 +406,7 @@ static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[])
405 idev->msg_r = &msgs[1]; 406 idev->msg_r = &msgs[1];
406 idev->msg_xfrd = 0; 407 idev->msg_xfrd = 0;
407 idev->msg_xfrd_r = 0; 408 idev->msg_xfrd_r = 0;
409 idev->last = true;
408 axxia_i2c_fill_tx_fifo(idev); 410 axxia_i2c_fill_tx_fifo(idev);
409 411
410 writel(CMD_SEQUENCE, idev->base + MST_COMMAND); 412 writel(CMD_SEQUENCE, idev->base + MST_COMMAND);
@@ -415,10 +417,6 @@ static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[])
415 time_left = wait_for_completion_timeout(&idev->msg_complete, 417 time_left = wait_for_completion_timeout(&idev->msg_complete,
416 I2C_XFER_TIMEOUT); 418 I2C_XFER_TIMEOUT);
417 419
418 i2c_int_disable(idev, int_mask);
419
420 axxia_i2c_empty_rx_fifo(idev);
421
422 if (idev->msg_err == -ENXIO) { 420 if (idev->msg_err == -ENXIO) {
423 if (axxia_i2c_handle_seq_nak(idev)) 421 if (axxia_i2c_handle_seq_nak(idev))
424 axxia_i2c_init(idev); 422 axxia_i2c_init(idev);
@@ -438,9 +436,10 @@ static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[])
438 return idev->msg_err; 436 return idev->msg_err;
439} 437}
440 438
441static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg) 439static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg,
440 bool last)
442{ 441{
443 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SNS; 442 u32 int_mask = MST_STATUS_ERR;
444 u32 rx_xfer, tx_xfer; 443 u32 rx_xfer, tx_xfer;
445 unsigned long time_left; 444 unsigned long time_left;
446 unsigned int wt_value; 445 unsigned int wt_value;
@@ -449,6 +448,7 @@ static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
449 idev->msg_r = msg; 448 idev->msg_r = msg;
450 idev->msg_xfrd = 0; 449 idev->msg_xfrd = 0;
451 idev->msg_xfrd_r = 0; 450 idev->msg_xfrd_r = 0;
451 idev->last = last;
452 reinit_completion(&idev->msg_complete); 452 reinit_completion(&idev->msg_complete);
453 453
454 axxia_i2c_set_addr(idev, msg); 454 axxia_i2c_set_addr(idev, msg);
@@ -478,8 +478,13 @@ static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
478 if (idev->msg_err) 478 if (idev->msg_err)
479 goto out; 479 goto out;
480 480
481 /* Start manual mode */ 481 if (!last) {
482 writel(CMD_MANUAL, idev->base + MST_COMMAND); 482 writel(CMD_MANUAL, idev->base + MST_COMMAND);
483 int_mask |= MST_STATUS_SNS;
484 } else {
485 writel(CMD_AUTO, idev->base + MST_COMMAND);
486 int_mask |= MST_STATUS_SS;
487 }
483 488
484 writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL); 489 writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL);
485 490
@@ -507,28 +512,6 @@ out:
507 return idev->msg_err; 512 return idev->msg_err;
508} 513}
509 514
510static int axxia_i2c_stop(struct axxia_i2c_dev *idev)
511{
512 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SCC | MST_STATUS_TSS;
513 unsigned long time_left;
514
515 reinit_completion(&idev->msg_complete);
516
517 /* Issue stop */
518 writel(0xb, idev->base + MST_COMMAND);
519 i2c_int_enable(idev, int_mask);
520 time_left = wait_for_completion_timeout(&idev->msg_complete,
521 I2C_STOP_TIMEOUT);
522 i2c_int_disable(idev, int_mask);
523 if (time_left == 0)
524 return -ETIMEDOUT;
525
526 if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
527 dev_warn(idev->dev, "busy after stop\n");
528
529 return 0;
530}
531
532/* This function checks if the msgs[] array contains messages compatible with 515/* This function checks if the msgs[] array contains messages compatible with
533 * Sequence mode of operation. This mode assumes there will be exactly one 516 * Sequence mode of operation. This mode assumes there will be exactly one
534 * write of non-zero length followed by exactly one read of non-zero length, 517 * write of non-zero length followed by exactly one read of non-zero length,
@@ -558,9 +541,7 @@ axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
558 i2c_int_enable(idev, MST_STATUS_TSS); 541 i2c_int_enable(idev, MST_STATUS_TSS);
559 542
560 for (i = 0; ret == 0 && i < num; ++i) 543 for (i = 0; ret == 0 && i < num; ++i)
561 ret = axxia_i2c_xfer_msg(idev, &msgs[i]); 544 ret = axxia_i2c_xfer_msg(idev, &msgs[i], i == (num - 1));
562
563 axxia_i2c_stop(idev);
564 545
565 return ret ? : i; 546 return ret ? : i;
566} 547}
diff --git a/drivers/i2c/busses/i2c-bcm-iproc.c b/drivers/i2c/busses/i2c-bcm-iproc.c
index 4c8c3bc4669c..a845b8decac8 100644
--- a/drivers/i2c/busses/i2c-bcm-iproc.c
+++ b/drivers/i2c/busses/i2c-bcm-iproc.c
@@ -17,17 +17,38 @@
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/of_device.h>
20#include <linux/platform_device.h> 21#include <linux/platform_device.h>
21#include <linux/slab.h> 22#include <linux/slab.h>
22 23
24#define IDM_CTRL_DIRECT_OFFSET 0x00
23#define CFG_OFFSET 0x00 25#define CFG_OFFSET 0x00
24#define CFG_RESET_SHIFT 31 26#define CFG_RESET_SHIFT 31
25#define CFG_EN_SHIFT 30 27#define CFG_EN_SHIFT 30
28#define CFG_SLAVE_ADDR_0_SHIFT 28
26#define CFG_M_RETRY_CNT_SHIFT 16 29#define CFG_M_RETRY_CNT_SHIFT 16
27#define CFG_M_RETRY_CNT_MASK 0x0f 30#define CFG_M_RETRY_CNT_MASK 0x0f
28 31
29#define TIM_CFG_OFFSET 0x04 32#define TIM_CFG_OFFSET 0x04
30#define TIM_CFG_MODE_400_SHIFT 31 33#define TIM_CFG_MODE_400_SHIFT 31
34#define TIM_RAND_SLAVE_STRETCH_SHIFT 24
35#define TIM_RAND_SLAVE_STRETCH_MASK 0x7f
36#define TIM_PERIODIC_SLAVE_STRETCH_SHIFT 16
37#define TIM_PERIODIC_SLAVE_STRETCH_MASK 0x7f
38
39#define S_CFG_SMBUS_ADDR_OFFSET 0x08
40#define S_CFG_EN_NIC_SMB_ADDR3_SHIFT 31
41#define S_CFG_NIC_SMB_ADDR3_SHIFT 24
42#define S_CFG_NIC_SMB_ADDR3_MASK 0x7f
43#define S_CFG_EN_NIC_SMB_ADDR2_SHIFT 23
44#define S_CFG_NIC_SMB_ADDR2_SHIFT 16
45#define S_CFG_NIC_SMB_ADDR2_MASK 0x7f
46#define S_CFG_EN_NIC_SMB_ADDR1_SHIFT 15
47#define S_CFG_NIC_SMB_ADDR1_SHIFT 8
48#define S_CFG_NIC_SMB_ADDR1_MASK 0x7f
49#define S_CFG_EN_NIC_SMB_ADDR0_SHIFT 7
50#define S_CFG_NIC_SMB_ADDR0_SHIFT 0
51#define S_CFG_NIC_SMB_ADDR0_MASK 0x7f
31 52
32#define M_FIFO_CTRL_OFFSET 0x0c 53#define M_FIFO_CTRL_OFFSET 0x0c
33#define M_FIFO_RX_FLUSH_SHIFT 31 54#define M_FIFO_RX_FLUSH_SHIFT 31
@@ -37,6 +58,14 @@
37#define M_FIFO_RX_THLD_SHIFT 8 58#define M_FIFO_RX_THLD_SHIFT 8
38#define M_FIFO_RX_THLD_MASK 0x3f 59#define M_FIFO_RX_THLD_MASK 0x3f
39 60
61#define S_FIFO_CTRL_OFFSET 0x10
62#define S_FIFO_RX_FLUSH_SHIFT 31
63#define S_FIFO_TX_FLUSH_SHIFT 30
64#define S_FIFO_RX_CNT_SHIFT 16
65#define S_FIFO_RX_CNT_MASK 0x7f
66#define S_FIFO_RX_THLD_SHIFT 8
67#define S_FIFO_RX_THLD_MASK 0x3f
68
40#define M_CMD_OFFSET 0x30 69#define M_CMD_OFFSET 0x30
41#define M_CMD_START_BUSY_SHIFT 31 70#define M_CMD_START_BUSY_SHIFT 31
42#define M_CMD_STATUS_SHIFT 25 71#define M_CMD_STATUS_SHIFT 25
@@ -46,6 +75,8 @@
46#define M_CMD_STATUS_NACK_ADDR 0x2 75#define M_CMD_STATUS_NACK_ADDR 0x2
47#define M_CMD_STATUS_NACK_DATA 0x3 76#define M_CMD_STATUS_NACK_DATA 0x3
48#define M_CMD_STATUS_TIMEOUT 0x4 77#define M_CMD_STATUS_TIMEOUT 0x4
78#define M_CMD_STATUS_FIFO_UNDERRUN 0x5
79#define M_CMD_STATUS_RX_FIFO_FULL 0x6
49#define M_CMD_PROTOCOL_SHIFT 9 80#define M_CMD_PROTOCOL_SHIFT 9
50#define M_CMD_PROTOCOL_MASK 0xf 81#define M_CMD_PROTOCOL_MASK 0xf
51#define M_CMD_PROTOCOL_BLK_WR 0x7 82#define M_CMD_PROTOCOL_BLK_WR 0x7
@@ -54,17 +85,36 @@
54#define M_CMD_RD_CNT_SHIFT 0 85#define M_CMD_RD_CNT_SHIFT 0
55#define M_CMD_RD_CNT_MASK 0xff 86#define M_CMD_RD_CNT_MASK 0xff
56 87
88#define S_CMD_OFFSET 0x34
89#define S_CMD_START_BUSY_SHIFT 31
90#define S_CMD_STATUS_SHIFT 23
91#define S_CMD_STATUS_MASK 0x07
92#define S_CMD_STATUS_SUCCESS 0x0
93#define S_CMD_STATUS_TIMEOUT 0x5
94
57#define IE_OFFSET 0x38 95#define IE_OFFSET 0x38
58#define IE_M_RX_FIFO_FULL_SHIFT 31 96#define IE_M_RX_FIFO_FULL_SHIFT 31
59#define IE_M_RX_THLD_SHIFT 30 97#define IE_M_RX_THLD_SHIFT 30
60#define IE_M_START_BUSY_SHIFT 28 98#define IE_M_START_BUSY_SHIFT 28
61#define IE_M_TX_UNDERRUN_SHIFT 27 99#define IE_M_TX_UNDERRUN_SHIFT 27
100#define IE_S_RX_FIFO_FULL_SHIFT 26
101#define IE_S_RX_THLD_SHIFT 25
102#define IE_S_RX_EVENT_SHIFT 24
103#define IE_S_START_BUSY_SHIFT 23
104#define IE_S_TX_UNDERRUN_SHIFT 22
105#define IE_S_RD_EVENT_SHIFT 21
62 106
63#define IS_OFFSET 0x3c 107#define IS_OFFSET 0x3c
64#define IS_M_RX_FIFO_FULL_SHIFT 31 108#define IS_M_RX_FIFO_FULL_SHIFT 31
65#define IS_M_RX_THLD_SHIFT 30 109#define IS_M_RX_THLD_SHIFT 30
66#define IS_M_START_BUSY_SHIFT 28 110#define IS_M_START_BUSY_SHIFT 28
67#define IS_M_TX_UNDERRUN_SHIFT 27 111#define IS_M_TX_UNDERRUN_SHIFT 27
112#define IS_S_RX_FIFO_FULL_SHIFT 26
113#define IS_S_RX_THLD_SHIFT 25
114#define IS_S_RX_EVENT_SHIFT 24
115#define IS_S_START_BUSY_SHIFT 23
116#define IS_S_TX_UNDERRUN_SHIFT 22
117#define IS_S_RD_EVENT_SHIFT 21
68 118
69#define M_TX_OFFSET 0x40 119#define M_TX_OFFSET 0x40
70#define M_TX_WR_STATUS_SHIFT 31 120#define M_TX_WR_STATUS_SHIFT 31
@@ -78,19 +128,71 @@
78#define M_RX_DATA_SHIFT 0 128#define M_RX_DATA_SHIFT 0
79#define M_RX_DATA_MASK 0xff 129#define M_RX_DATA_MASK 0xff
80 130
131#define S_TX_OFFSET 0x48
132#define S_TX_WR_STATUS_SHIFT 31
133#define S_TX_DATA_SHIFT 0
134#define S_TX_DATA_MASK 0xff
135
136#define S_RX_OFFSET 0x4c
137#define S_RX_STATUS_SHIFT 30
138#define S_RX_STATUS_MASK 0x03
139#define S_RX_PEC_ERR_SHIFT 29
140#define S_RX_DATA_SHIFT 0
141#define S_RX_DATA_MASK 0xff
142
81#define I2C_TIMEOUT_MSEC 50000 143#define I2C_TIMEOUT_MSEC 50000
82#define M_TX_RX_FIFO_SIZE 64 144#define M_TX_RX_FIFO_SIZE 64
145#define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1)
146
147#define M_RX_MAX_READ_LEN 255
148#define M_RX_FIFO_THLD_VALUE 50
149
150#define IE_M_ALL_INTERRUPT_SHIFT 27
151#define IE_M_ALL_INTERRUPT_MASK 0x1e
152
153#define SLAVE_READ_WRITE_BIT_MASK 0x1
154#define SLAVE_READ_WRITE_BIT_SHIFT 0x1
155#define SLAVE_MAX_SIZE_TRANSACTION 64
156#define SLAVE_CLOCK_STRETCH_TIME 25
157
158#define IE_S_ALL_INTERRUPT_SHIFT 21
159#define IE_S_ALL_INTERRUPT_MASK 0x3f
160
161enum i2c_slave_read_status {
162 I2C_SLAVE_RX_FIFO_EMPTY = 0,
163 I2C_SLAVE_RX_START,
164 I2C_SLAVE_RX_DATA,
165 I2C_SLAVE_RX_END,
166};
167
168enum i2c_slave_xfer_dir {
169 I2C_SLAVE_DIR_READ = 0,
170 I2C_SLAVE_DIR_WRITE,
171 I2C_SLAVE_DIR_NONE,
172};
83 173
84enum bus_speed_index { 174enum bus_speed_index {
85 I2C_SPD_100K = 0, 175 I2C_SPD_100K = 0,
86 I2C_SPD_400K, 176 I2C_SPD_400K,
87}; 177};
88 178
179enum bcm_iproc_i2c_type {
180 IPROC_I2C,
181 IPROC_I2C_NIC
182};
183
89struct bcm_iproc_i2c_dev { 184struct bcm_iproc_i2c_dev {
90 struct device *device; 185 struct device *device;
186 enum bcm_iproc_i2c_type type;
91 int irq; 187 int irq;
92 188
93 void __iomem *base; 189 void __iomem *base;
190 void __iomem *idm_base;
191
192 u32 ape_addr_mask;
193
194 /* lock for indirect access through IDM */
195 spinlock_t idm_lock;
94 196
95 struct i2c_adapter adapter; 197 struct i2c_adapter adapter;
96 unsigned int bus_speed; 198 unsigned int bus_speed;
@@ -100,68 +202,332 @@ struct bcm_iproc_i2c_dev {
100 202
101 struct i2c_msg *msg; 203 struct i2c_msg *msg;
102 204
205 struct i2c_client *slave;
206 enum i2c_slave_xfer_dir xfer_dir;
207
103 /* bytes that have been transferred */ 208 /* bytes that have been transferred */
104 unsigned int tx_bytes; 209 unsigned int tx_bytes;
210 /* bytes that have been read */
211 unsigned int rx_bytes;
212 unsigned int thld_bytes;
105}; 213};
106 214
107/* 215/*
108 * Can be expanded in the future if more interrupt status bits are utilized 216 * Can be expanded in the future if more interrupt status bits are utilized
109 */ 217 */
110#define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)) 218#define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\
219 | BIT(IS_M_RX_THLD_SHIFT))
111 220
112static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data) 221#define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
222 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT))
223
224static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
225static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
226static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
227 bool enable);
228
229static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
230 u32 offset)
113{ 231{
114 struct bcm_iproc_i2c_dev *iproc_i2c = data; 232 u32 val;
115 u32 status = readl(iproc_i2c->base + IS_OFFSET);
116 233
117 status &= ISR_MASK; 234 if (iproc_i2c->idm_base) {
235 spin_lock(&iproc_i2c->idm_lock);
236 writel(iproc_i2c->ape_addr_mask,
237 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
238 val = readl(iproc_i2c->base + offset);
239 spin_unlock(&iproc_i2c->idm_lock);
240 } else {
241 val = readl(iproc_i2c->base + offset);
242 }
118 243
119 if (!status) 244 return val;
120 return IRQ_NONE; 245}
121 246
122 /* TX FIFO is empty and we have more data to send */ 247static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
123 if (status & BIT(IS_M_TX_UNDERRUN_SHIFT)) { 248 u32 offset, u32 val)
124 struct i2c_msg *msg = iproc_i2c->msg; 249{
125 unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes; 250 if (iproc_i2c->idm_base) {
126 unsigned int i; 251 spin_lock(&iproc_i2c->idm_lock);
127 u32 val; 252 writel(iproc_i2c->ape_addr_mask,
128 253 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
129 /* can only fill up to the FIFO size */ 254 writel(val, iproc_i2c->base + offset);
130 tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE); 255 spin_unlock(&iproc_i2c->idm_lock);
131 for (i = 0; i < tx_bytes; i++) { 256 } else {
132 /* start from where we left over */ 257 writel(val, iproc_i2c->base + offset);
133 unsigned int idx = iproc_i2c->tx_bytes + i; 258 }
259}
134 260
135 val = msg->buf[idx]; 261static void bcm_iproc_i2c_slave_init(
262 struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
263{
264 u32 val;
136 265
137 /* mark the last byte */ 266 if (need_reset) {
138 if (idx == msg->len - 1) { 267 /* put controller in reset */
139 u32 tmp; 268 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
269 val |= BIT(CFG_RESET_SHIFT);
270 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
140 271
141 val |= BIT(M_TX_WR_STATUS_SHIFT); 272 /* wait 100 usec per spec */
273 udelay(100);
274
275 /* bring controller out of reset */
276 val &= ~(BIT(CFG_RESET_SHIFT));
277 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
278 }
279
280 /* flush TX/RX FIFOs */
281 val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
282 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
283
284 /* Maximum slave stretch time */
285 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
286 val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
287 val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
288 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
289
290 /* Configure the slave address */
291 val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
292 val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
293 val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
294 val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
295 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
296
297 /* clear all pending slave interrupts */
298 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
299
300 /* Enable interrupt register for any READ event */
301 val = BIT(IE_S_RD_EVENT_SHIFT);
302 /* Enable interrupt register to indicate a valid byte in receive fifo */
303 val |= BIT(IE_S_RX_EVENT_SHIFT);
304 /* Enable interrupt register for the Slave BUSY command */
305 val |= BIT(IE_S_START_BUSY_SHIFT);
306 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
307
308 iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;
309}
310
311static void bcm_iproc_i2c_check_slave_status(
312 struct bcm_iproc_i2c_dev *iproc_i2c)
313{
314 u32 val;
315
316 val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
317 val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
318
319 if (val == S_CMD_STATUS_TIMEOUT) {
320 dev_err(iproc_i2c->device, "slave random stretch time timeout\n");
321
322 /* re-initialize i2c for recovery */
323 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
324 bcm_iproc_i2c_slave_init(iproc_i2c, true);
325 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
326 }
327}
328
329static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
330 u32 status)
331{
332 u8 value;
333 u32 val;
334 u32 rd_status;
335 u32 tmp;
336
337 /* Start of transaction. check address and populate the direction */
338 if (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_NONE) {
339 tmp = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
340 rd_status = (tmp >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
341 /* This condition checks whether the request is a new request */
342 if (((rd_status == I2C_SLAVE_RX_START) &&
343 (status & BIT(IS_S_RX_EVENT_SHIFT))) ||
344 ((rd_status == I2C_SLAVE_RX_END) &&
345 (status & BIT(IS_S_RD_EVENT_SHIFT)))) {
346
347 /* Last bit is W/R bit.
348 * If 1 then its a read request(by master).
349 */
350 iproc_i2c->xfer_dir = tmp & SLAVE_READ_WRITE_BIT_MASK;
351 if (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_WRITE)
352 i2c_slave_event(iproc_i2c->slave,
353 I2C_SLAVE_READ_REQUESTED, &value);
354 else
355 i2c_slave_event(iproc_i2c->slave,
356 I2C_SLAVE_WRITE_REQUESTED, &value);
357 }
358 }
359
360 /* read request from master */
361 if ((status & BIT(IS_S_RD_EVENT_SHIFT)) &&
362 (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_WRITE)) {
363 i2c_slave_event(iproc_i2c->slave,
364 I2C_SLAVE_READ_PROCESSED, &value);
365 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
366
367 val = BIT(S_CMD_START_BUSY_SHIFT);
368 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
369 }
370
371 /* write request from master */
372 if ((status & BIT(IS_S_RX_EVENT_SHIFT)) &&
373 (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_READ)) {
374 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
375 /* Its a write request by Master to Slave.
376 * We read data present in receive FIFO
377 */
378 value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
379 i2c_slave_event(iproc_i2c->slave,
380 I2C_SLAVE_WRITE_RECEIVED, &value);
381
382 /* check the status for the last byte of the transaction */
383 rd_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
384 if (rd_status == I2C_SLAVE_RX_END)
385 iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;
386
387 dev_dbg(iproc_i2c->device, "\nread value = 0x%x\n", value);
388 }
389
390 /* Stop */
391 if (status & BIT(IS_S_START_BUSY_SHIFT)) {
392 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
393 iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;
394 }
395
396 /* clear interrupt status */
397 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
398
399 bcm_iproc_i2c_check_slave_status(iproc_i2c);
400 return true;
401}
402
403static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
404{
405 struct i2c_msg *msg = iproc_i2c->msg;
406
407 /* Read valid data from RX FIFO */
408 while (iproc_i2c->rx_bytes < msg->len) {
409 if (!((iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET) >> M_FIFO_RX_CNT_SHIFT)
410 & M_FIFO_RX_CNT_MASK))
411 break;
412
413 msg->buf[iproc_i2c->rx_bytes] =
414 (iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET) >>
415 M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
416 iproc_i2c->rx_bytes++;
417 }
418}
419
420static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
421{
422 struct i2c_msg *msg = iproc_i2c->msg;
423 unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
424 unsigned int i;
425 u32 val;
426
427 /* can only fill up to the FIFO size */
428 tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
429 for (i = 0; i < tx_bytes; i++) {
430 /* start from where we left over */
431 unsigned int idx = iproc_i2c->tx_bytes + i;
432
433 val = msg->buf[idx];
434
435 /* mark the last byte */
436 if (idx == msg->len - 1) {
437 val |= BIT(M_TX_WR_STATUS_SHIFT);
438
439 if (iproc_i2c->irq) {
440 u32 tmp;
142 441
143 /* 442 /*
144 * Since this is the last byte, we should 443 * Since this is the last byte, we should now
145 * now disable TX FIFO underrun interrupt 444 * disable TX FIFO underrun interrupt
146 */ 445 */
147 tmp = readl(iproc_i2c->base + IE_OFFSET); 446 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
148 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT); 447 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
149 writel(tmp, iproc_i2c->base + IE_OFFSET); 448 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
449 tmp);
150 } 450 }
451 }
452
453 /* load data into TX FIFO */
454 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
455 }
151 456
152 /* load data into TX FIFO */ 457 /* update number of transferred bytes */
153 writel(val, iproc_i2c->base + M_TX_OFFSET); 458 iproc_i2c->tx_bytes += tx_bytes;
459}
460
461static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
462{
463 struct i2c_msg *msg = iproc_i2c->msg;
464 u32 bytes_left, val;
465
466 bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
467 bytes_left = msg->len - iproc_i2c->rx_bytes;
468 if (bytes_left == 0) {
469 if (iproc_i2c->irq) {
470 /* finished reading all data, disable rx thld event */
471 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
472 val &= ~BIT(IS_M_RX_THLD_SHIFT);
473 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
154 } 474 }
155 /* update number of transferred bytes */ 475 } else if (bytes_left < iproc_i2c->thld_bytes) {
156 iproc_i2c->tx_bytes += tx_bytes; 476 /* set bytes left as threshold */
477 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
478 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
479 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
480 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
481 iproc_i2c->thld_bytes = bytes_left;
157 } 482 }
483 /*
484 * bytes_left >= iproc_i2c->thld_bytes,
485 * hence no need to change the THRESHOLD SET.
486 * It will remain as iproc_i2c->thld_bytes itself
487 */
488}
489
490static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
491 u32 status)
492{
493 /* TX FIFO is empty and we have more data to send */
494 if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))
495 bcm_iproc_i2c_send(iproc_i2c);
158 496
497 /* RX FIFO threshold is reached and data needs to be read out */
498 if (status & BIT(IS_M_RX_THLD_SHIFT))
499 bcm_iproc_i2c_read(iproc_i2c);
500
501 /* transfer is done */
159 if (status & BIT(IS_M_START_BUSY_SHIFT)) { 502 if (status & BIT(IS_M_START_BUSY_SHIFT)) {
160 iproc_i2c->xfer_is_done = 1; 503 iproc_i2c->xfer_is_done = 1;
161 complete(&iproc_i2c->done); 504 if (iproc_i2c->irq)
505 complete(&iproc_i2c->done);
162 } 506 }
507}
163 508
164 writel(status, iproc_i2c->base + IS_OFFSET); 509static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
510{
511 struct bcm_iproc_i2c_dev *iproc_i2c = data;
512 u32 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
513 bool ret;
514 u32 sl_status = status & ISR_MASK_SLAVE;
515
516 if (sl_status) {
517 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, sl_status);
518 if (ret)
519 return IRQ_HANDLED;
520 else
521 return IRQ_NONE;
522 }
523
524 status &= ISR_MASK;
525 if (!status)
526 return IRQ_NONE;
527
528 /* process all master based events */
529 bcm_iproc_i2c_process_m_event(iproc_i2c, status);
530 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
165 531
166 return IRQ_HANDLED; 532 return IRQ_HANDLED;
167} 533}
@@ -171,26 +537,29 @@ static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
171 u32 val; 537 u32 val;
172 538
173 /* put controller in reset */ 539 /* put controller in reset */
174 val = readl(iproc_i2c->base + CFG_OFFSET); 540 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
175 val |= 1 << CFG_RESET_SHIFT; 541 val |= BIT(CFG_RESET_SHIFT);
176 val &= ~(1 << CFG_EN_SHIFT); 542 val &= ~(BIT(CFG_EN_SHIFT));
177 writel(val, iproc_i2c->base + CFG_OFFSET); 543 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
178 544
179 /* wait 100 usec per spec */ 545 /* wait 100 usec per spec */
180 udelay(100); 546 udelay(100);
181 547
182 /* bring controller out of reset */ 548 /* bring controller out of reset */
183 val &= ~(1 << CFG_RESET_SHIFT); 549 val &= ~(BIT(CFG_RESET_SHIFT));
184 writel(val, iproc_i2c->base + CFG_OFFSET); 550 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
185 551
186 /* flush TX/RX FIFOs and set RX FIFO threshold to zero */ 552 /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
187 val = (1 << M_FIFO_RX_FLUSH_SHIFT) | (1 << M_FIFO_TX_FLUSH_SHIFT); 553 val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
188 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); 554 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
189 /* disable all interrupts */ 555 /* disable all interrupts */
190 writel(0, iproc_i2c->base + IE_OFFSET); 556 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
557 val &= ~(IE_M_ALL_INTERRUPT_MASK <<
558 IE_M_ALL_INTERRUPT_SHIFT);
559 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
191 560
192 /* clear all pending interrupts */ 561 /* clear all pending interrupts */
193 writel(0xffffffff, iproc_i2c->base + IS_OFFSET); 562 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff);
194 563
195 return 0; 564 return 0;
196} 565}
@@ -200,12 +569,12 @@ static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
200{ 569{
201 u32 val; 570 u32 val;
202 571
203 val = readl(iproc_i2c->base + CFG_OFFSET); 572 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
204 if (enable) 573 if (enable)
205 val |= BIT(CFG_EN_SHIFT); 574 val |= BIT(CFG_EN_SHIFT);
206 else 575 else
207 val &= ~BIT(CFG_EN_SHIFT); 576 val &= ~BIT(CFG_EN_SHIFT);
208 writel(val, iproc_i2c->base + CFG_OFFSET); 577 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
209} 578}
210 579
211static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c, 580static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
@@ -213,7 +582,7 @@ static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
213{ 582{
214 u32 val; 583 u32 val;
215 584
216 val = readl(iproc_i2c->base + M_CMD_OFFSET); 585 val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
217 val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK; 586 val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
218 587
219 switch (val) { 588 switch (val) {
@@ -236,6 +605,14 @@ static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
236 dev_dbg(iproc_i2c->device, "bus timeout\n"); 605 dev_dbg(iproc_i2c->device, "bus timeout\n");
237 return -ETIMEDOUT; 606 return -ETIMEDOUT;
238 607
608 case M_CMD_STATUS_FIFO_UNDERRUN:
609 dev_dbg(iproc_i2c->device, "FIFO under-run\n");
610 return -ENXIO;
611
612 case M_CMD_STATUS_RX_FIFO_FULL:
613 dev_dbg(iproc_i2c->device, "RX FIFO full\n");
614 return -ETIMEDOUT;
615
239 default: 616 default:
240 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val); 617 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
241 618
@@ -248,18 +625,76 @@ static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
248 } 625 }
249} 626}
250 627
628static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
629 struct i2c_msg *msg,
630 u32 cmd)
631{
632 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
633 u32 val, status;
634 int ret;
635
636 iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd);
637
638 if (iproc_i2c->irq) {
639 time_left = wait_for_completion_timeout(&iproc_i2c->done,
640 time_left);
641 /* disable all interrupts */
642 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
643 /* read it back to flush the write */
644 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
645 /* make sure the interrupt handler isn't running */
646 synchronize_irq(iproc_i2c->irq);
647
648 } else { /* polling mode */
649 unsigned long timeout = jiffies + time_left;
650
651 do {
652 status = iproc_i2c_rd_reg(iproc_i2c,
653 IS_OFFSET) & ISR_MASK;
654 bcm_iproc_i2c_process_m_event(iproc_i2c, status);
655 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
656
657 if (time_after(jiffies, timeout)) {
658 time_left = 0;
659 break;
660 }
661
662 cpu_relax();
663 cond_resched();
664 } while (!iproc_i2c->xfer_is_done);
665 }
666
667 if (!time_left && !iproc_i2c->xfer_is_done) {
668 dev_err(iproc_i2c->device, "transaction timed out\n");
669
670 /* flush both TX/RX FIFOs */
671 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
672 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
673 return -ETIMEDOUT;
674 }
675
676 ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
677 if (ret) {
678 /* flush both TX/RX FIFOs */
679 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
680 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
681 return ret;
682 }
683
684 return 0;
685}
686
251static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, 687static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
252 struct i2c_msg *msg) 688 struct i2c_msg *msg)
253{ 689{
254 int ret, i; 690 int i;
255 u8 addr; 691 u8 addr;
256 u32 val; 692 u32 val, tmp, val_intr_en;
257 unsigned int tx_bytes; 693 unsigned int tx_bytes;
258 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
259 694
260 /* check if bus is busy */ 695 /* check if bus is busy */
261 if (!!(readl(iproc_i2c->base + M_CMD_OFFSET) & 696 if (!!(iproc_i2c_rd_reg(iproc_i2c,
262 BIT(M_CMD_START_BUSY_SHIFT))) { 697 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
263 dev_warn(iproc_i2c->device, "bus is busy\n"); 698 dev_warn(iproc_i2c->device, "bus is busy\n");
264 return -EBUSY; 699 return -EBUSY;
265 } 700 }
@@ -268,7 +703,7 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
268 703
269 /* format and load slave address into the TX FIFO */ 704 /* format and load slave address into the TX FIFO */
270 addr = i2c_8bit_addr_from_msg(msg); 705 addr = i2c_8bit_addr_from_msg(msg);
271 writel(addr, iproc_i2c->base + M_TX_OFFSET); 706 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr);
272 707
273 /* 708 /*
274 * For a write transaction, load data into the TX FIFO. Only allow 709 * For a write transaction, load data into the TX FIFO. Only allow
@@ -282,15 +717,17 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
282 717
283 /* mark the last byte */ 718 /* mark the last byte */
284 if (i == msg->len - 1) 719 if (i == msg->len - 1)
285 val |= 1 << M_TX_WR_STATUS_SHIFT; 720 val |= BIT(M_TX_WR_STATUS_SHIFT);
286 721
287 writel(val, iproc_i2c->base + M_TX_OFFSET); 722 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
288 } 723 }
289 iproc_i2c->tx_bytes = tx_bytes; 724 iproc_i2c->tx_bytes = tx_bytes;
290 } 725 }
291 726
292 /* mark as incomplete before starting the transaction */ 727 /* mark as incomplete before starting the transaction */
293 reinit_completion(&iproc_i2c->done); 728 if (iproc_i2c->irq)
729 reinit_completion(&iproc_i2c->done);
730
294 iproc_i2c->xfer_is_done = 0; 731 iproc_i2c->xfer_is_done = 0;
295 732
296 /* 733 /*
@@ -298,7 +735,7 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
298 * transaction is done, i.e., the internal start_busy bit, transitions 735 * transaction is done, i.e., the internal start_busy bit, transitions
299 * from 1 to 0. 736 * from 1 to 0.
300 */ 737 */
301 val = BIT(IE_M_START_BUSY_SHIFT); 738 val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
302 739
303 /* 740 /*
304 * If TX data size is larger than the TX FIFO, need to enable TX 741 * If TX data size is larger than the TX FIFO, need to enable TX
@@ -307,9 +744,7 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
307 */ 744 */
308 if (!(msg->flags & I2C_M_RD) && 745 if (!(msg->flags & I2C_M_RD) &&
309 msg->len > iproc_i2c->tx_bytes) 746 msg->len > iproc_i2c->tx_bytes)
310 val |= BIT(IE_M_TX_UNDERRUN_SHIFT); 747 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
311
312 writel(val, iproc_i2c->base + IE_OFFSET);
313 748
314 /* 749 /*
315 * Now we can activate the transfer. For a read operation, specify the 750 * Now we can activate the transfer. For a read operation, specify the
@@ -317,54 +752,31 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
317 */ 752 */
318 val = BIT(M_CMD_START_BUSY_SHIFT); 753 val = BIT(M_CMD_START_BUSY_SHIFT);
319 if (msg->flags & I2C_M_RD) { 754 if (msg->flags & I2C_M_RD) {
755 iproc_i2c->rx_bytes = 0;
756 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)
757 iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;
758 else
759 iproc_i2c->thld_bytes = msg->len;
760
761 /* set threshold value */
762 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
763 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
764 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
765 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp);
766
767 /* enable the RX threshold interrupt */
768 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
769
320 val |= (M_CMD_PROTOCOL_BLK_RD << M_CMD_PROTOCOL_SHIFT) | 770 val |= (M_CMD_PROTOCOL_BLK_RD << M_CMD_PROTOCOL_SHIFT) |
321 (msg->len << M_CMD_RD_CNT_SHIFT); 771 (msg->len << M_CMD_RD_CNT_SHIFT);
322 } else { 772 } else {
323 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT); 773 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
324 } 774 }
325 writel(val, iproc_i2c->base + M_CMD_OFFSET);
326
327 time_left = wait_for_completion_timeout(&iproc_i2c->done, time_left);
328
329 /* disable all interrupts */
330 writel(0, iproc_i2c->base + IE_OFFSET);
331 /* read it back to flush the write */
332 readl(iproc_i2c->base + IE_OFFSET);
333
334 /* make sure the interrupt handler isn't running */
335 synchronize_irq(iproc_i2c->irq);
336 775
337 if (!time_left && !iproc_i2c->xfer_is_done) { 776 if (iproc_i2c->irq)
338 dev_err(iproc_i2c->device, "transaction timed out\n"); 777 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);
339 778
340 /* flush FIFOs */ 779 return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
341 val = (1 << M_FIFO_RX_FLUSH_SHIFT) |
342 (1 << M_FIFO_TX_FLUSH_SHIFT);
343 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
344 return -ETIMEDOUT;
345 }
346
347 ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
348 if (ret) {
349 /* flush both TX/RX FIFOs */
350 val = (1 << M_FIFO_RX_FLUSH_SHIFT) |
351 (1 << M_FIFO_TX_FLUSH_SHIFT);
352 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
353 return ret;
354 }
355
356 /*
357 * For a read operation, we now need to load the data from FIFO
358 * into the memory buffer
359 */
360 if (msg->flags & I2C_M_RD) {
361 for (i = 0; i < msg->len; i++) {
362 msg->buf[i] = (readl(iproc_i2c->base + M_RX_OFFSET) >>
363 M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
364 }
365 }
366
367 return 0;
368} 780}
369 781
370static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter, 782static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
@@ -387,17 +799,23 @@ static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
387 799
388static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap) 800static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
389{ 801{
390 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 802 u32 val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
803
804 if (adap->algo->reg_slave)
805 val |= I2C_FUNC_SLAVE;
806
807 return val;
391} 808}
392 809
393static const struct i2c_algorithm bcm_iproc_algo = { 810static struct i2c_algorithm bcm_iproc_algo = {
394 .master_xfer = bcm_iproc_i2c_xfer, 811 .master_xfer = bcm_iproc_i2c_xfer,
395 .functionality = bcm_iproc_i2c_functionality, 812 .functionality = bcm_iproc_i2c_functionality,
813 .reg_slave = bcm_iproc_i2c_reg_slave,
814 .unreg_slave = bcm_iproc_i2c_unreg_slave,
396}; 815};
397 816
398static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = { 817static struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
399 /* need to reserve one byte in the FIFO for the slave address */ 818 .max_read_len = M_RX_MAX_READ_LEN,
400 .max_read_len = M_TX_RX_FIFO_SIZE - 1,
401}; 819};
402 820
403static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c) 821static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
@@ -425,10 +843,10 @@ static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
425 } 843 }
426 844
427 iproc_i2c->bus_speed = bus_speed; 845 iproc_i2c->bus_speed = bus_speed;
428 val = readl(iproc_i2c->base + TIM_CFG_OFFSET); 846 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
429 val &= ~(1 << TIM_CFG_MODE_400_SHIFT); 847 val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
430 val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT; 848 val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
431 writel(val, iproc_i2c->base + TIM_CFG_OFFSET); 849 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
432 850
433 dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed); 851 dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
434 852
@@ -449,6 +867,8 @@ static int bcm_iproc_i2c_probe(struct platform_device *pdev)
449 867
450 platform_set_drvdata(pdev, iproc_i2c); 868 platform_set_drvdata(pdev, iproc_i2c);
451 iproc_i2c->device = &pdev->dev; 869 iproc_i2c->device = &pdev->dev;
870 iproc_i2c->type =
871 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev);
452 init_completion(&iproc_i2c->done); 872 init_completion(&iproc_i2c->done);
453 873
454 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 874 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -456,6 +876,29 @@ static int bcm_iproc_i2c_probe(struct platform_device *pdev)
456 if (IS_ERR(iproc_i2c->base)) 876 if (IS_ERR(iproc_i2c->base))
457 return PTR_ERR(iproc_i2c->base); 877 return PTR_ERR(iproc_i2c->base);
458 878
879 if (iproc_i2c->type == IPROC_I2C_NIC) {
880 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
881 iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device,
882 res);
883 if (IS_ERR(iproc_i2c->idm_base))
884 return PTR_ERR(iproc_i2c->idm_base);
885
886 ret = of_property_read_u32(iproc_i2c->device->of_node,
887 "brcm,ape-hsls-addr-mask",
888 &iproc_i2c->ape_addr_mask);
889 if (ret < 0) {
890 dev_err(iproc_i2c->device,
891 "'brcm,ape-hsls-addr-mask' missing\n");
892 return -EINVAL;
893 }
894
895 spin_lock_init(&iproc_i2c->idm_lock);
896
897 /* no slave support */
898 bcm_iproc_algo.reg_slave = NULL;
899 bcm_iproc_algo.unreg_slave = NULL;
900 }
901
459 ret = bcm_iproc_i2c_init(iproc_i2c); 902 ret = bcm_iproc_i2c_init(iproc_i2c);
460 if (ret) 903 if (ret)
461 return ret; 904 return ret;
@@ -465,17 +908,20 @@ static int bcm_iproc_i2c_probe(struct platform_device *pdev)
465 return ret; 908 return ret;
466 909
467 irq = platform_get_irq(pdev, 0); 910 irq = platform_get_irq(pdev, 0);
468 if (irq <= 0) { 911 if (irq > 0) {
469 dev_err(iproc_i2c->device, "no irq resource\n"); 912 ret = devm_request_irq(iproc_i2c->device, irq,
470 return irq; 913 bcm_iproc_i2c_isr, 0, pdev->name,
471 } 914 iproc_i2c);
472 iproc_i2c->irq = irq; 915 if (ret < 0) {
916 dev_err(iproc_i2c->device,
917 "unable to request irq %i\n", irq);
918 return ret;
919 }
473 920
474 ret = devm_request_irq(iproc_i2c->device, irq, bcm_iproc_i2c_isr, 0, 921 iproc_i2c->irq = irq;
475 pdev->name, iproc_i2c); 922 } else {
476 if (ret < 0) { 923 dev_warn(iproc_i2c->device,
477 dev_err(iproc_i2c->device, "unable to request irq %i\n", irq); 924 "no irq resource, falling back to poll mode\n");
478 return ret;
479 } 925 }
480 926
481 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 927 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
@@ -495,10 +941,15 @@ static int bcm_iproc_i2c_remove(struct platform_device *pdev)
495{ 941{
496 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev); 942 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
497 943
498 /* make sure there's no pending interrupt when we remove the adapter */ 944 if (iproc_i2c->irq) {
499 writel(0, iproc_i2c->base + IE_OFFSET); 945 /*
500 readl(iproc_i2c->base + IE_OFFSET); 946 * Make sure there's no pending interrupt when we remove the
501 synchronize_irq(iproc_i2c->irq); 947 * adapter
948 */
949 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
950 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
951 synchronize_irq(iproc_i2c->irq);
952 }
502 953
503 i2c_del_adapter(&iproc_i2c->adapter); 954 i2c_del_adapter(&iproc_i2c->adapter);
504 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 955 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
@@ -512,10 +963,15 @@ static int bcm_iproc_i2c_suspend(struct device *dev)
512{ 963{
513 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev); 964 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
514 965
515 /* make sure there's no pending interrupt when we go into suspend */ 966 if (iproc_i2c->irq) {
516 writel(0, iproc_i2c->base + IE_OFFSET); 967 /*
517 readl(iproc_i2c->base + IE_OFFSET); 968 * Make sure there's no pending interrupt when we go into
518 synchronize_irq(iproc_i2c->irq); 969 * suspend
970 */
971 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
972 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
973 synchronize_irq(iproc_i2c->irq);
974 }
519 975
520 /* now disable the controller */ 976 /* now disable the controller */
521 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 977 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
@@ -538,10 +994,10 @@ static int bcm_iproc_i2c_resume(struct device *dev)
538 return ret; 994 return ret;
539 995
540 /* configure to the desired bus speed */ 996 /* configure to the desired bus speed */
541 val = readl(iproc_i2c->base + TIM_CFG_OFFSET); 997 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
542 val &= ~(1 << TIM_CFG_MODE_400_SHIFT); 998 val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
543 val |= (iproc_i2c->bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT; 999 val |= (iproc_i2c->bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
544 writel(val, iproc_i2c->base + TIM_CFG_OFFSET); 1000 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
545 1001
546 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 1002 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
547 1003
@@ -558,8 +1014,54 @@ static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
558#define BCM_IPROC_I2C_PM_OPS NULL 1014#define BCM_IPROC_I2C_PM_OPS NULL
559#endif /* CONFIG_PM_SLEEP */ 1015#endif /* CONFIG_PM_SLEEP */
560 1016
1017
1018static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)
1019{
1020 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1021
1022 if (iproc_i2c->slave)
1023 return -EBUSY;
1024
1025 if (slave->flags & I2C_CLIENT_TEN)
1026 return -EAFNOSUPPORT;
1027
1028 iproc_i2c->slave = slave;
1029 bcm_iproc_i2c_slave_init(iproc_i2c, false);
1030 return 0;
1031}
1032
1033static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
1034{
1035 u32 tmp;
1036 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1037
1038 if (!iproc_i2c->slave)
1039 return -EINVAL;
1040
1041 iproc_i2c->slave = NULL;
1042
1043 /* disable all slave interrupts */
1044 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1045 tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
1046 IE_S_ALL_INTERRUPT_SHIFT);
1047 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);
1048
1049 /* Erase the slave address programmed */
1050 tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
1051 tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
1052 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp);
1053
1054 return 0;
1055}
1056
561static const struct of_device_id bcm_iproc_i2c_of_match[] = { 1057static const struct of_device_id bcm_iproc_i2c_of_match[] = {
562 { .compatible = "brcm,iproc-i2c" }, 1058 {
1059 .compatible = "brcm,iproc-i2c",
1060 .data = (int *)IPROC_I2C,
1061 }, {
1062 .compatible = "brcm,iproc-nic-i2c",
1063 .data = (int *)IPROC_I2C_NIC,
1064 },
563 { /* sentinel */ } 1065 { /* sentinel */ }
564}; 1066};
565MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match); 1067MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
diff --git a/drivers/i2c/busses/i2c-brcmstb.c b/drivers/i2c/busses/i2c-brcmstb.c
index f4d862234980..506991596b68 100644
--- a/drivers/i2c/busses/i2c-brcmstb.c
+++ b/drivers/i2c/busses/i2c-brcmstb.c
@@ -165,7 +165,6 @@ static const struct bsc_clk_param bsc_clk[] = {
165struct brcmstb_i2c_dev { 165struct brcmstb_i2c_dev {
166 struct device *device; 166 struct device *device;
167 void __iomem *base; 167 void __iomem *base;
168 void __iomem *irq_base;
169 int irq; 168 int irq;
170 struct bsc_regs *bsc_regmap; 169 struct bsc_regs *bsc_regmap;
171 struct i2c_adapter adapter; 170 struct i2c_adapter adapter;
diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c
index a4730111d290..2de7452fcd6d 100644
--- a/drivers/i2c/busses/i2c-designware-common.c
+++ b/drivers/i2c/busses/i2c-designware-common.c
@@ -251,13 +251,27 @@ unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
251 251
252int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare) 252int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare)
253{ 253{
254 int ret;
255
254 if (IS_ERR(dev->clk)) 256 if (IS_ERR(dev->clk))
255 return PTR_ERR(dev->clk); 257 return PTR_ERR(dev->clk);
256 258
257 if (prepare) 259 if (prepare) {
258 return clk_prepare_enable(dev->clk); 260 /* Optional interface clock */
261 ret = clk_prepare_enable(dev->pclk);
262 if (ret)
263 return ret;
264
265 ret = clk_prepare_enable(dev->clk);
266 if (ret)
267 clk_disable_unprepare(dev->pclk);
268
269 return ret;
270 }
259 271
260 clk_disable_unprepare(dev->clk); 272 clk_disable_unprepare(dev->clk);
273 clk_disable_unprepare(dev->pclk);
274
261 return 0; 275 return 0;
262} 276}
263EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk); 277EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk);
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index 6b4ef1d38fb2..67edbbde1070 100644
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -177,6 +177,7 @@
177 * @base: IO registers pointer 177 * @base: IO registers pointer
178 * @cmd_complete: tx completion indicator 178 * @cmd_complete: tx completion indicator
179 * @clk: input reference clock 179 * @clk: input reference clock
180 * @pclk: clock required to access the registers
180 * @slave: represent an I2C slave device 181 * @slave: represent an I2C slave device
181 * @cmd_err: run time hadware error code 182 * @cmd_err: run time hadware error code
182 * @msgs: points to an array of messages currently being transferred 183 * @msgs: points to an array of messages currently being transferred
@@ -227,6 +228,7 @@ struct dw_i2c_dev {
227 void __iomem *ext; 228 void __iomem *ext;
228 struct completion cmd_complete; 229 struct completion cmd_complete;
229 struct clk *clk; 230 struct clk *clk;
231 struct clk *pclk;
230 struct reset_control *rst; 232 struct reset_control *rst;
231 struct i2c_client *slave; 233 struct i2c_client *slave;
232 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev); 234 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 416f89b8f881..ddfb81872906 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -344,6 +344,11 @@ static int dw_i2c_plat_probe(struct platform_device *pdev)
344 else 344 else
345 i2c_dw_configure_master(dev); 345 i2c_dw_configure_master(dev);
346 346
347 /* Optional interface clock */
348 dev->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
349 if (IS_ERR(dev->pclk))
350 return PTR_ERR(dev->pclk);
351
347 dev->clk = devm_clk_get(&pdev->dev, NULL); 352 dev->clk = devm_clk_get(&pdev->dev, NULL);
348 if (!i2c_dw_prepare_clk(dev, true)) { 353 if (!i2c_dw_prepare_clk(dev, true)) {
349 u64 clk_khz; 354 u64 clk_khz;
diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
index bba5c4627de3..9684a0ac2a6d 100644
--- a/drivers/i2c/busses/i2c-gpio.c
+++ b/drivers/i2c/busses/i2c-gpio.c
@@ -413,6 +413,8 @@ static int i2c_gpio_probe(struct platform_device *pdev)
413 413
414 if (gpiod_cansleep(priv->sda) || gpiod_cansleep(priv->scl)) 414 if (gpiod_cansleep(priv->sda) || gpiod_cansleep(priv->scl))
415 dev_warn(dev, "Slow GPIO pins might wreak havoc into I2C/SMBus bus timing"); 415 dev_warn(dev, "Slow GPIO pins might wreak havoc into I2C/SMBus bus timing");
416 else
417 bit_data->can_do_atomic = true;
416 418
417 bit_data->setsda = i2c_gpio_setsda_val; 419 bit_data->setsda = i2c_gpio_setsda_val;
418 bit_data->setscl = i2c_gpio_setscl_val; 420 bit_data->setscl = i2c_gpio_setscl_val;
diff --git a/drivers/i2c/busses/i2c-imx-lpi2c.c b/drivers/i2c/busses/i2c-imx-lpi2c.c
index 06c4c767af32..dc00fabc919a 100644
--- a/drivers/i2c/busses/i2c-imx-lpi2c.c
+++ b/drivers/i2c/busses/i2c-imx-lpi2c.c
@@ -639,8 +639,7 @@ static int lpi2c_imx_remove(struct platform_device *pdev)
639 return 0; 639 return 0;
640} 640}
641 641
642#ifdef CONFIG_PM_SLEEP 642static int __maybe_unused lpi2c_runtime_suspend(struct device *dev)
643static int lpi2c_runtime_suspend(struct device *dev)
644{ 643{
645 struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev); 644 struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev);
646 645
@@ -650,7 +649,7 @@ static int lpi2c_runtime_suspend(struct device *dev)
650 return 0; 649 return 0;
651} 650}
652 651
653static int lpi2c_runtime_resume(struct device *dev) 652static int __maybe_unused lpi2c_runtime_resume(struct device *dev)
654{ 653{
655 struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev); 654 struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev);
656 int ret; 655 int ret;
@@ -671,10 +670,6 @@ static const struct dev_pm_ops lpi2c_pm_ops = {
671 SET_RUNTIME_PM_OPS(lpi2c_runtime_suspend, 670 SET_RUNTIME_PM_OPS(lpi2c_runtime_suspend,
672 lpi2c_runtime_resume, NULL) 671 lpi2c_runtime_resume, NULL)
673}; 672};
674#define IMX_LPI2C_PM (&lpi2c_pm_ops)
675#else
676#define IMX_LPI2C_PM NULL
677#endif
678 673
679static struct platform_driver lpi2c_imx_driver = { 674static struct platform_driver lpi2c_imx_driver = {
680 .probe = lpi2c_imx_probe, 675 .probe = lpi2c_imx_probe,
@@ -682,7 +677,7 @@ static struct platform_driver lpi2c_imx_driver = {
682 .driver = { 677 .driver = {
683 .name = DRIVER_NAME, 678 .name = DRIVER_NAME,
684 .of_match_table = lpi2c_imx_of_match, 679 .of_match_table = lpi2c_imx_of_match,
685 .pm = IMX_LPI2C_PM, 680 .pm = &lpi2c_pm_ops,
686 }, 681 },
687}; 682};
688 683
diff --git a/drivers/i2c/busses/i2c-isch.c b/drivers/i2c/busses/i2c-isch.c
index 5c754bf659e2..f64c1d72f73f 100644
--- a/drivers/i2c/busses/i2c-isch.c
+++ b/drivers/i2c/busses/i2c-isch.c
@@ -30,7 +30,6 @@
30#include <linux/ioport.h> 30#include <linux/ioport.h>
31#include <linux/i2c.h> 31#include <linux/i2c.h>
32#include <linux/io.h> 32#include <linux/io.h>
33#include <linux/acpi.h>
34 33
35/* SCH SMBus address offsets */ 34/* SCH SMBus address offsets */
36#define SMBHSTCNT (0 + sch_smba) 35#define SMBHSTCNT (0 + sch_smba)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 684d651612b3..745b0d03e883 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -35,6 +35,7 @@
35#include <linux/slab.h> 35#include <linux/slab.h>
36 36
37#define I2C_RS_TRANSFER (1 << 4) 37#define I2C_RS_TRANSFER (1 << 4)
38#define I2C_ARB_LOST (1 << 3)
38#define I2C_HS_NACKERR (1 << 2) 39#define I2C_HS_NACKERR (1 << 2)
39#define I2C_ACKERR (1 << 1) 40#define I2C_ACKERR (1 << 1)
40#define I2C_TRANSAC_COMP (1 << 0) 41#define I2C_TRANSAC_COMP (1 << 0)
@@ -76,6 +77,8 @@
76#define I2C_CONTROL_DIR_CHANGE (0x1 << 4) 77#define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
77#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) 78#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
78#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) 79#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
80#define I2C_CONTROL_DMAACK_EN (0x1 << 8)
81#define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
79#define I2C_CONTROL_WRAPPER (0x1 << 0) 82#define I2C_CONTROL_WRAPPER (0x1 << 0)
80 83
81#define I2C_DRV_NAME "i2c-mt65xx" 84#define I2C_DRV_NAME "i2c-mt65xx"
@@ -106,40 +109,97 @@ enum mtk_trans_op {
106}; 109};
107 110
108enum I2C_REGS_OFFSET { 111enum I2C_REGS_OFFSET {
109 OFFSET_DATA_PORT = 0x0, 112 OFFSET_DATA_PORT,
110 OFFSET_SLAVE_ADDR = 0x04, 113 OFFSET_SLAVE_ADDR,
111 OFFSET_INTR_MASK = 0x08, 114 OFFSET_INTR_MASK,
112 OFFSET_INTR_STAT = 0x0c, 115 OFFSET_INTR_STAT,
113 OFFSET_CONTROL = 0x10, 116 OFFSET_CONTROL,
114 OFFSET_TRANSFER_LEN = 0x14, 117 OFFSET_TRANSFER_LEN,
115 OFFSET_TRANSAC_LEN = 0x18, 118 OFFSET_TRANSAC_LEN,
116 OFFSET_DELAY_LEN = 0x1c, 119 OFFSET_DELAY_LEN,
117 OFFSET_TIMING = 0x20, 120 OFFSET_TIMING,
118 OFFSET_START = 0x24, 121 OFFSET_START,
119 OFFSET_EXT_CONF = 0x28, 122 OFFSET_EXT_CONF,
120 OFFSET_FIFO_STAT = 0x30, 123 OFFSET_FIFO_STAT,
121 OFFSET_FIFO_THRESH = 0x34, 124 OFFSET_FIFO_THRESH,
122 OFFSET_FIFO_ADDR_CLR = 0x38, 125 OFFSET_FIFO_ADDR_CLR,
123 OFFSET_IO_CONFIG = 0x40, 126 OFFSET_IO_CONFIG,
124 OFFSET_RSV_DEBUG = 0x44, 127 OFFSET_RSV_DEBUG,
125 OFFSET_HS = 0x48, 128 OFFSET_HS,
126 OFFSET_SOFTRESET = 0x50, 129 OFFSET_SOFTRESET,
127 OFFSET_DCM_EN = 0x54, 130 OFFSET_DCM_EN,
128 OFFSET_PATH_DIR = 0x60, 131 OFFSET_PATH_DIR,
129 OFFSET_DEBUGSTAT = 0x64, 132 OFFSET_DEBUGSTAT,
130 OFFSET_DEBUGCTRL = 0x68, 133 OFFSET_DEBUGCTRL,
131 OFFSET_TRANSFER_LEN_AUX = 0x6c, 134 OFFSET_TRANSFER_LEN_AUX,
132 OFFSET_CLOCK_DIV = 0x70, 135 OFFSET_CLOCK_DIV,
136 OFFSET_LTIMING,
137};
138
139static const u16 mt_i2c_regs_v1[] = {
140 [OFFSET_DATA_PORT] = 0x0,
141 [OFFSET_SLAVE_ADDR] = 0x4,
142 [OFFSET_INTR_MASK] = 0x8,
143 [OFFSET_INTR_STAT] = 0xc,
144 [OFFSET_CONTROL] = 0x10,
145 [OFFSET_TRANSFER_LEN] = 0x14,
146 [OFFSET_TRANSAC_LEN] = 0x18,
147 [OFFSET_DELAY_LEN] = 0x1c,
148 [OFFSET_TIMING] = 0x20,
149 [OFFSET_START] = 0x24,
150 [OFFSET_EXT_CONF] = 0x28,
151 [OFFSET_FIFO_STAT] = 0x30,
152 [OFFSET_FIFO_THRESH] = 0x34,
153 [OFFSET_FIFO_ADDR_CLR] = 0x38,
154 [OFFSET_IO_CONFIG] = 0x40,
155 [OFFSET_RSV_DEBUG] = 0x44,
156 [OFFSET_HS] = 0x48,
157 [OFFSET_SOFTRESET] = 0x50,
158 [OFFSET_DCM_EN] = 0x54,
159 [OFFSET_PATH_DIR] = 0x60,
160 [OFFSET_DEBUGSTAT] = 0x64,
161 [OFFSET_DEBUGCTRL] = 0x68,
162 [OFFSET_TRANSFER_LEN_AUX] = 0x6c,
163 [OFFSET_CLOCK_DIV] = 0x70,
164};
165
166static const u16 mt_i2c_regs_v2[] = {
167 [OFFSET_DATA_PORT] = 0x0,
168 [OFFSET_SLAVE_ADDR] = 0x4,
169 [OFFSET_INTR_MASK] = 0x8,
170 [OFFSET_INTR_STAT] = 0xc,
171 [OFFSET_CONTROL] = 0x10,
172 [OFFSET_TRANSFER_LEN] = 0x14,
173 [OFFSET_TRANSAC_LEN] = 0x18,
174 [OFFSET_DELAY_LEN] = 0x1c,
175 [OFFSET_TIMING] = 0x20,
176 [OFFSET_START] = 0x24,
177 [OFFSET_EXT_CONF] = 0x28,
178 [OFFSET_LTIMING] = 0x2c,
179 [OFFSET_HS] = 0x30,
180 [OFFSET_IO_CONFIG] = 0x34,
181 [OFFSET_FIFO_ADDR_CLR] = 0x38,
182 [OFFSET_TRANSFER_LEN_AUX] = 0x44,
183 [OFFSET_CLOCK_DIV] = 0x48,
184 [OFFSET_SOFTRESET] = 0x50,
185 [OFFSET_DEBUGSTAT] = 0xe0,
186 [OFFSET_DEBUGCTRL] = 0xe8,
187 [OFFSET_FIFO_STAT] = 0xf4,
188 [OFFSET_FIFO_THRESH] = 0xf8,
189 [OFFSET_DCM_EN] = 0xf88,
133}; 190};
134 191
135struct mtk_i2c_compatible { 192struct mtk_i2c_compatible {
136 const struct i2c_adapter_quirks *quirks; 193 const struct i2c_adapter_quirks *quirks;
194 const u16 *regs;
137 unsigned char pmic_i2c: 1; 195 unsigned char pmic_i2c: 1;
138 unsigned char dcm: 1; 196 unsigned char dcm: 1;
139 unsigned char auto_restart: 1; 197 unsigned char auto_restart: 1;
140 unsigned char aux_len_reg: 1; 198 unsigned char aux_len_reg: 1;
141 unsigned char support_33bits: 1; 199 unsigned char support_33bits: 1;
142 unsigned char timing_adjust: 1; 200 unsigned char timing_adjust: 1;
201 unsigned char dma_sync: 1;
202 unsigned char ltiming_adjust: 1;
143}; 203};
144 204
145struct mtk_i2c { 205struct mtk_i2c {
@@ -153,6 +213,7 @@ struct mtk_i2c {
153 struct clk *clk_main; /* main clock for i2c bus */ 213 struct clk *clk_main; /* main clock for i2c bus */
154 struct clk *clk_dma; /* DMA clock for i2c via DMA */ 214 struct clk *clk_dma; /* DMA clock for i2c via DMA */
155 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */ 215 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
216 struct clk *clk_arb; /* Arbitrator clock for i2c */
156 bool have_pmic; /* can use i2c pins from PMIC */ 217 bool have_pmic; /* can use i2c pins from PMIC */
157 bool use_push_pull; /* IO config push-pull mode */ 218 bool use_push_pull; /* IO config push-pull mode */
158 219
@@ -162,6 +223,7 @@ struct mtk_i2c {
162 enum mtk_trans_op op; 223 enum mtk_trans_op op;
163 u16 timing_reg; 224 u16 timing_reg;
164 u16 high_speed_reg; 225 u16 high_speed_reg;
226 u16 ltiming_reg;
165 unsigned char auto_restart; 227 unsigned char auto_restart;
166 bool ignore_restart_irq; 228 bool ignore_restart_irq;
167 const struct mtk_i2c_compatible *dev_comp; 229 const struct mtk_i2c_compatible *dev_comp;
@@ -181,51 +243,78 @@ static const struct i2c_adapter_quirks mt7622_i2c_quirks = {
181}; 243};
182 244
183static const struct mtk_i2c_compatible mt2712_compat = { 245static const struct mtk_i2c_compatible mt2712_compat = {
246 .regs = mt_i2c_regs_v1,
184 .pmic_i2c = 0, 247 .pmic_i2c = 0,
185 .dcm = 1, 248 .dcm = 1,
186 .auto_restart = 1, 249 .auto_restart = 1,
187 .aux_len_reg = 1, 250 .aux_len_reg = 1,
188 .support_33bits = 1, 251 .support_33bits = 1,
189 .timing_adjust = 1, 252 .timing_adjust = 1,
253 .dma_sync = 0,
254 .ltiming_adjust = 0,
190}; 255};
191 256
192static const struct mtk_i2c_compatible mt6577_compat = { 257static const struct mtk_i2c_compatible mt6577_compat = {
193 .quirks = &mt6577_i2c_quirks, 258 .quirks = &mt6577_i2c_quirks,
259 .regs = mt_i2c_regs_v1,
194 .pmic_i2c = 0, 260 .pmic_i2c = 0,
195 .dcm = 1, 261 .dcm = 1,
196 .auto_restart = 0, 262 .auto_restart = 0,
197 .aux_len_reg = 0, 263 .aux_len_reg = 0,
198 .support_33bits = 0, 264 .support_33bits = 0,
199 .timing_adjust = 0, 265 .timing_adjust = 0,
266 .dma_sync = 0,
267 .ltiming_adjust = 0,
200}; 268};
201 269
202static const struct mtk_i2c_compatible mt6589_compat = { 270static const struct mtk_i2c_compatible mt6589_compat = {
203 .quirks = &mt6577_i2c_quirks, 271 .quirks = &mt6577_i2c_quirks,
272 .regs = mt_i2c_regs_v1,
204 .pmic_i2c = 1, 273 .pmic_i2c = 1,
205 .dcm = 0, 274 .dcm = 0,
206 .auto_restart = 0, 275 .auto_restart = 0,
207 .aux_len_reg = 0, 276 .aux_len_reg = 0,
208 .support_33bits = 0, 277 .support_33bits = 0,
209 .timing_adjust = 0, 278 .timing_adjust = 0,
279 .dma_sync = 0,
280 .ltiming_adjust = 0,
210}; 281};
211 282
212static const struct mtk_i2c_compatible mt7622_compat = { 283static const struct mtk_i2c_compatible mt7622_compat = {
213 .quirks = &mt7622_i2c_quirks, 284 .quirks = &mt7622_i2c_quirks,
285 .regs = mt_i2c_regs_v1,
214 .pmic_i2c = 0, 286 .pmic_i2c = 0,
215 .dcm = 1, 287 .dcm = 1,
216 .auto_restart = 1, 288 .auto_restart = 1,
217 .aux_len_reg = 1, 289 .aux_len_reg = 1,
218 .support_33bits = 0, 290 .support_33bits = 0,
219 .timing_adjust = 0, 291 .timing_adjust = 0,
292 .dma_sync = 0,
293 .ltiming_adjust = 0,
220}; 294};
221 295
222static const struct mtk_i2c_compatible mt8173_compat = { 296static const struct mtk_i2c_compatible mt8173_compat = {
297 .regs = mt_i2c_regs_v1,
223 .pmic_i2c = 0, 298 .pmic_i2c = 0,
224 .dcm = 1, 299 .dcm = 1,
225 .auto_restart = 1, 300 .auto_restart = 1,
226 .aux_len_reg = 1, 301 .aux_len_reg = 1,
227 .support_33bits = 1, 302 .support_33bits = 1,
228 .timing_adjust = 0, 303 .timing_adjust = 0,
304 .dma_sync = 0,
305 .ltiming_adjust = 0,
306};
307
308static const struct mtk_i2c_compatible mt8183_compat = {
309 .regs = mt_i2c_regs_v2,
310 .pmic_i2c = 0,
311 .dcm = 0,
312 .auto_restart = 1,
313 .aux_len_reg = 1,
314 .support_33bits = 1,
315 .timing_adjust = 1,
316 .dma_sync = 1,
317 .ltiming_adjust = 1,
229}; 318};
230 319
231static const struct of_device_id mtk_i2c_of_match[] = { 320static const struct of_device_id mtk_i2c_of_match[] = {
@@ -234,10 +323,22 @@ static const struct of_device_id mtk_i2c_of_match[] = {
234 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, 323 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
235 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, 324 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
236 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, 325 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
326 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
237 {} 327 {}
238}; 328};
239MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); 329MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
240 330
331static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
332{
333 return readw(i2c->base + i2c->dev_comp->regs[reg]);
334}
335
336static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
337 enum I2C_REGS_OFFSET reg)
338{
339 writew(val, i2c->base + i2c->dev_comp->regs[reg]);
340}
341
241static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) 342static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
242{ 343{
243 int ret; 344 int ret;
@@ -255,8 +356,18 @@ static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
255 if (ret) 356 if (ret)
256 goto err_pmic; 357 goto err_pmic;
257 } 358 }
359
360 if (i2c->clk_arb) {
361 ret = clk_prepare_enable(i2c->clk_arb);
362 if (ret)
363 goto err_arb;
364 }
365
258 return 0; 366 return 0;
259 367
368err_arb:
369 if (i2c->have_pmic)
370 clk_disable_unprepare(i2c->clk_pmic);
260err_pmic: 371err_pmic:
261 clk_disable_unprepare(i2c->clk_main); 372 clk_disable_unprepare(i2c->clk_main);
262err_main: 373err_main:
@@ -267,6 +378,9 @@ err_main:
267 378
268static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) 379static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
269{ 380{
381 if (i2c->clk_arb)
382 clk_disable_unprepare(i2c->clk_arb);
383
270 if (i2c->have_pmic) 384 if (i2c->have_pmic)
271 clk_disable_unprepare(i2c->clk_pmic); 385 clk_disable_unprepare(i2c->clk_pmic);
272 386
@@ -278,31 +392,36 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
278{ 392{
279 u16 control_reg; 393 u16 control_reg;
280 394
281 writew(I2C_SOFT_RST, i2c->base + OFFSET_SOFTRESET); 395 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
282 396
283 /* Set ioconfig */ 397 /* Set ioconfig */
284 if (i2c->use_push_pull) 398 if (i2c->use_push_pull)
285 writew(I2C_IO_CONFIG_PUSH_PULL, i2c->base + OFFSET_IO_CONFIG); 399 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
286 else 400 else
287 writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c->base + OFFSET_IO_CONFIG); 401 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
288 402
289 if (i2c->dev_comp->dcm) 403 if (i2c->dev_comp->dcm)
290 writew(I2C_DCM_DISABLE, i2c->base + OFFSET_DCM_EN); 404 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
291 405
292 if (i2c->dev_comp->timing_adjust) 406 if (i2c->dev_comp->timing_adjust)
293 writew(I2C_DEFAULT_CLK_DIV - 1, i2c->base + OFFSET_CLOCK_DIV); 407 mtk_i2c_writew(i2c, I2C_DEFAULT_CLK_DIV - 1, OFFSET_CLOCK_DIV);
294 408
295 writew(i2c->timing_reg, i2c->base + OFFSET_TIMING); 409 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
296 writew(i2c->high_speed_reg, i2c->base + OFFSET_HS); 410 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
411 if (i2c->dev_comp->ltiming_adjust)
412 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
297 413
298 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ 414 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
299 if (i2c->have_pmic) 415 if (i2c->have_pmic)
300 writew(I2C_CONTROL_WRAPPER, i2c->base + OFFSET_PATH_DIR); 416 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
301 417
302 control_reg = I2C_CONTROL_ACKERR_DET_EN | 418 control_reg = I2C_CONTROL_ACKERR_DET_EN |
303 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; 419 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
304 writew(control_reg, i2c->base + OFFSET_CONTROL); 420 if (i2c->dev_comp->dma_sync)
305 writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN); 421 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE;
422
423 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
424 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
306 425
307 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); 426 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
308 udelay(50); 427 udelay(50);
@@ -390,6 +509,8 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
390 unsigned int clk_src; 509 unsigned int clk_src;
391 unsigned int step_cnt; 510 unsigned int step_cnt;
392 unsigned int sample_cnt; 511 unsigned int sample_cnt;
512 unsigned int l_step_cnt;
513 unsigned int l_sample_cnt;
393 unsigned int target_speed; 514 unsigned int target_speed;
394 int ret; 515 int ret;
395 516
@@ -399,11 +520,11 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
399 if (target_speed > MAX_FS_MODE_SPEED) { 520 if (target_speed > MAX_FS_MODE_SPEED) {
400 /* Set master code speed register */ 521 /* Set master code speed register */
401 ret = mtk_i2c_calculate_speed(i2c, clk_src, MAX_FS_MODE_SPEED, 522 ret = mtk_i2c_calculate_speed(i2c, clk_src, MAX_FS_MODE_SPEED,
402 &step_cnt, &sample_cnt); 523 &l_step_cnt, &l_sample_cnt);
403 if (ret < 0) 524 if (ret < 0)
404 return ret; 525 return ret;
405 526
406 i2c->timing_reg = (sample_cnt << 8) | step_cnt; 527 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
407 528
408 /* Set the high speed mode register */ 529 /* Set the high speed mode register */
409 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed, 530 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
@@ -413,6 +534,10 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
413 534
414 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | 535 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
415 (sample_cnt << 12) | (step_cnt << 8); 536 (sample_cnt << 12) | (step_cnt << 8);
537
538 if (i2c->dev_comp->ltiming_adjust)
539 i2c->ltiming_reg = (l_sample_cnt << 6) | l_step_cnt |
540 (sample_cnt << 12) | (step_cnt << 9);
416 } else { 541 } else {
417 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed, 542 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
418 &step_cnt, &sample_cnt); 543 &step_cnt, &sample_cnt);
@@ -423,6 +548,9 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
423 548
424 /* Disable the high speed transaction */ 549 /* Disable the high speed transaction */
425 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; 550 i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
551
552 if (i2c->dev_comp->ltiming_adjust)
553 i2c->ltiming_reg = (sample_cnt << 6) | step_cnt;
426 } 554 }
427 555
428 return 0; 556 return 0;
@@ -454,7 +582,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
454 582
455 reinit_completion(&i2c->msg_complete); 583 reinit_completion(&i2c->msg_complete);
456 584
457 control_reg = readw(i2c->base + OFFSET_CONTROL) & 585 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
458 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); 586 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
459 if ((i2c->speed_hz > MAX_FS_MODE_SPEED) || (left_num >= 1)) 587 if ((i2c->speed_hz > MAX_FS_MODE_SPEED) || (left_num >= 1))
460 control_reg |= I2C_CONTROL_RS; 588 control_reg |= I2C_CONTROL_RS;
@@ -462,40 +590,41 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
462 if (i2c->op == I2C_MASTER_WRRD) 590 if (i2c->op == I2C_MASTER_WRRD)
463 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; 591 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
464 592
465 writew(control_reg, i2c->base + OFFSET_CONTROL); 593 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
466 594
467 /* set start condition */ 595 /* set start condition */
468 if (i2c->speed_hz <= I2C_DEFAULT_SPEED) 596 if (i2c->speed_hz <= I2C_DEFAULT_SPEED)
469 writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF); 597 mtk_i2c_writew(i2c, I2C_ST_START_CON, OFFSET_EXT_CONF);
470 else 598 else
471 writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF); 599 mtk_i2c_writew(i2c, I2C_FS_START_CON, OFFSET_EXT_CONF);
472 600
473 addr_reg = i2c_8bit_addr_from_msg(msgs); 601 addr_reg = i2c_8bit_addr_from_msg(msgs);
474 writew(addr_reg, i2c->base + OFFSET_SLAVE_ADDR); 602 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
475 603
476 /* Clear interrupt status */ 604 /* Clear interrupt status */
477 writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 605 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
478 I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT); 606 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
479 writew(I2C_FIFO_ADDR_CLR, i2c->base + OFFSET_FIFO_ADDR_CLR); 607
608 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
480 609
481 /* Enable interrupt */ 610 /* Enable interrupt */
482 writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 611 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
483 I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_MASK); 612 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK);
484 613
485 /* Set transfer and transaction len */ 614 /* Set transfer and transaction len */
486 if (i2c->op == I2C_MASTER_WRRD) { 615 if (i2c->op == I2C_MASTER_WRRD) {
487 if (i2c->dev_comp->aux_len_reg) { 616 if (i2c->dev_comp->aux_len_reg) {
488 writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN); 617 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
489 writew((msgs + 1)->len, i2c->base + 618 mtk_i2c_writew(i2c, (msgs + 1)->len,
490 OFFSET_TRANSFER_LEN_AUX); 619 OFFSET_TRANSFER_LEN_AUX);
491 } else { 620 } else {
492 writew(msgs->len | ((msgs + 1)->len) << 8, 621 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
493 i2c->base + OFFSET_TRANSFER_LEN); 622 OFFSET_TRANSFER_LEN);
494 } 623 }
495 writew(I2C_WRRD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN); 624 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
496 } else { 625 } else {
497 writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN); 626 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
498 writew(num, i2c->base + OFFSET_TRANSAC_LEN); 627 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
499 } 628 }
500 629
501 /* Prepare buffer data to start transfer */ 630 /* Prepare buffer data to start transfer */
@@ -607,14 +736,14 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
607 if (left_num >= 1) 736 if (left_num >= 1)
608 start_reg |= I2C_RS_MUL_CNFG; 737 start_reg |= I2C_RS_MUL_CNFG;
609 } 738 }
610 writew(start_reg, i2c->base + OFFSET_START); 739 mtk_i2c_writew(i2c, start_reg, OFFSET_START);
611 740
612 ret = wait_for_completion_timeout(&i2c->msg_complete, 741 ret = wait_for_completion_timeout(&i2c->msg_complete,
613 i2c->adap.timeout); 742 i2c->adap.timeout);
614 743
615 /* Clear interrupt mask */ 744 /* Clear interrupt mask */
616 writew(~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 745 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
617 I2C_TRANSAC_COMP), i2c->base + OFFSET_INTR_MASK); 746 I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK);
618 747
619 if (i2c->op == I2C_MASTER_WR) { 748 if (i2c->op == I2C_MASTER_WR) {
620 dma_unmap_single(i2c->dev, wpaddr, 749 dma_unmap_single(i2c->dev, wpaddr,
@@ -724,8 +853,8 @@ static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
724 if (i2c->auto_restart) 853 if (i2c->auto_restart)
725 restart_flag = I2C_RS_TRANSFER; 854 restart_flag = I2C_RS_TRANSFER;
726 855
727 intr_stat = readw(i2c->base + OFFSET_INTR_STAT); 856 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
728 writew(intr_stat, i2c->base + OFFSET_INTR_STAT); 857 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
729 858
730 /* 859 /*
731 * when occurs ack error, i2c controller generate two interrupts 860 * when occurs ack error, i2c controller generate two interrupts
@@ -737,8 +866,8 @@ static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
737 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { 866 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
738 i2c->ignore_restart_irq = false; 867 i2c->ignore_restart_irq = false;
739 i2c->irq_stat = 0; 868 i2c->irq_stat = 0;
740 writew(I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | I2C_TRANSAC_START, 869 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
741 i2c->base + OFFSET_START); 870 I2C_TRANSAC_START, OFFSET_START);
742 } else { 871 } else {
743 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) 872 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
744 complete(&i2c->msg_complete); 873 complete(&i2c->msg_complete);
@@ -839,6 +968,10 @@ static int mtk_i2c_probe(struct platform_device *pdev)
839 return PTR_ERR(i2c->clk_dma); 968 return PTR_ERR(i2c->clk_dma);
840 } 969 }
841 970
971 i2c->clk_arb = devm_clk_get(&pdev->dev, "arb");
972 if (IS_ERR(i2c->clk_arb))
973 i2c->clk_arb = NULL;
974
842 clk = i2c->clk_main; 975 clk = i2c->clk_main;
843 if (i2c->have_pmic) { 976 if (i2c->have_pmic) {
844 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); 977 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index 0ed5a41804dc..4f30a43b63da 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -1070,8 +1070,7 @@ static int nmk_i2c_remove(struct amba_device *adev)
1070 /* disable the controller */ 1070 /* disable the controller */
1071 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE); 1071 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
1072 clk_disable_unprepare(dev->clk); 1072 clk_disable_unprepare(dev->clk);
1073 if (res) 1073 release_mem_region(res->start, resource_size(res));
1074 release_mem_region(res->start, resource_size(res));
1075 1074
1076 return 0; 1075 return 0;
1077} 1076}
diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c
index 4e1a077fb688..c3dabee0aa35 100644
--- a/drivers/i2c/busses/i2c-ocores.c
+++ b/drivers/i2c/busses/i2c-ocores.c
@@ -26,8 +26,6 @@
26#include <linux/spinlock.h> 26#include <linux/spinlock.h>
27#include <linux/jiffies.h> 27#include <linux/jiffies.h>
28 28
29#define OCORES_FLAG_POLL BIT(0)
30
31/* 29/*
32 * 'process_lock' exists because ocores_process() and ocores_process_timeout() 30 * 'process_lock' exists because ocores_process() and ocores_process_timeout()
33 * can't run in parallel. 31 * can't run in parallel.
@@ -37,7 +35,6 @@ struct ocores_i2c {
37 int iobase; 35 int iobase;
38 u32 reg_shift; 36 u32 reg_shift;
39 u32 reg_io_width; 37 u32 reg_io_width;
40 unsigned long flags;
41 wait_queue_head_t wait; 38 wait_queue_head_t wait;
42 struct i2c_adapter adap; 39 struct i2c_adapter adap;
43 struct i2c_msg *msg; 40 struct i2c_msg *msg;
@@ -403,11 +400,7 @@ static int ocores_xfer_polling(struct i2c_adapter *adap,
403static int ocores_xfer(struct i2c_adapter *adap, 400static int ocores_xfer(struct i2c_adapter *adap,
404 struct i2c_msg *msgs, int num) 401 struct i2c_msg *msgs, int num)
405{ 402{
406 struct ocores_i2c *i2c = i2c_get_adapdata(adap); 403 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, false);
407
408 if (i2c->flags & OCORES_FLAG_POLL)
409 return ocores_xfer_polling(adap, msgs, num);
410 return ocores_xfer_core(i2c, msgs, num, false);
411} 404}
412 405
413static int ocores_init(struct device *dev, struct ocores_i2c *i2c) 406static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
@@ -447,8 +440,9 @@ static u32 ocores_func(struct i2c_adapter *adap)
447 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 440 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
448} 441}
449 442
450static const struct i2c_algorithm ocores_algorithm = { 443static struct i2c_algorithm ocores_algorithm = {
451 .master_xfer = ocores_xfer, 444 .master_xfer = ocores_xfer,
445 .master_xfer_atomic = ocores_xfer_polling,
452 .functionality = ocores_func, 446 .functionality = ocores_func,
453}; 447};
454 448
@@ -673,13 +667,13 @@ static int ocores_i2c_probe(struct platform_device *pdev)
673 667
674 irq = platform_get_irq(pdev, 0); 668 irq = platform_get_irq(pdev, 0);
675 if (irq == -ENXIO) { 669 if (irq == -ENXIO) {
676 i2c->flags |= OCORES_FLAG_POLL; 670 ocores_algorithm.master_xfer = ocores_xfer_polling;
677 } else { 671 } else {
678 if (irq < 0) 672 if (irq < 0)
679 return irq; 673 return irq;
680 } 674 }
681 675
682 if (!(i2c->flags & OCORES_FLAG_POLL)) { 676 if (ocores_algorithm.master_xfer != ocores_xfer_polling) {
683 ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0, 677 ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
684 pdev->name, i2c); 678 pdev->name, i2c);
685 if (ret) { 679 if (ret) {
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index cd9c65f3d404..faa0394048a0 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -269,6 +269,8 @@ static const u8 reg_map_ip_v2[] = {
269 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, 269 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
270}; 270};
271 271
272static int omap_i2c_xfer_data(struct omap_i2c_dev *omap);
273
272static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap, 274static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap,
273 int reg, u16 val) 275 int reg, u16 val)
274{ 276{
@@ -648,15 +650,28 @@ static void omap_i2c_resize_fifo(struct omap_i2c_dev *omap, u8 size, bool is_rx)
648 (1000 * omap->speed / 8); 650 (1000 * omap->speed / 8);
649} 651}
650 652
653static void omap_i2c_wait(struct omap_i2c_dev *omap)
654{
655 u16 stat;
656 u16 mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
657 int count = 0;
658
659 do {
660 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
661 count++;
662 } while (!(stat & mask) && count < 5);
663}
664
651/* 665/*
652 * Low level master read/write transaction. 666 * Low level master read/write transaction.
653 */ 667 */
654static int omap_i2c_xfer_msg(struct i2c_adapter *adap, 668static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
655 struct i2c_msg *msg, int stop) 669 struct i2c_msg *msg, int stop, bool polling)
656{ 670{
657 struct omap_i2c_dev *omap = i2c_get_adapdata(adap); 671 struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
658 unsigned long timeout; 672 unsigned long timeout;
659 u16 w; 673 u16 w;
674 int ret;
660 675
661 dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", 676 dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
662 msg->addr, msg->len, msg->flags, stop); 677 msg->addr, msg->len, msg->flags, stop);
@@ -680,7 +695,8 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
680 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; 695 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
681 omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w); 696 omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w);
682 697
683 reinit_completion(&omap->cmd_complete); 698 if (!polling)
699 reinit_completion(&omap->cmd_complete);
684 omap->cmd_err = 0; 700 omap->cmd_err = 0;
685 701
686 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; 702 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
@@ -732,8 +748,18 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
732 * REVISIT: We should abort the transfer on signals, but the bus goes 748 * REVISIT: We should abort the transfer on signals, but the bus goes
733 * into arbitration and we're currently unable to recover from it. 749 * into arbitration and we're currently unable to recover from it.
734 */ 750 */
735 timeout = wait_for_completion_timeout(&omap->cmd_complete, 751 if (!polling) {
736 OMAP_I2C_TIMEOUT); 752 timeout = wait_for_completion_timeout(&omap->cmd_complete,
753 OMAP_I2C_TIMEOUT);
754 } else {
755 do {
756 omap_i2c_wait(omap);
757 ret = omap_i2c_xfer_data(omap);
758 } while (ret == -EAGAIN);
759
760 timeout = !ret;
761 }
762
737 if (timeout == 0) { 763 if (timeout == 0) {
738 dev_err(omap->dev, "controller timed out\n"); 764 dev_err(omap->dev, "controller timed out\n");
739 omap_i2c_reset(omap); 765 omap_i2c_reset(omap);
@@ -772,7 +798,8 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
772 * to do the work during IRQ processing. 798 * to do the work during IRQ processing.
773 */ 799 */
774static int 800static int
775omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 801omap_i2c_xfer_common(struct i2c_adapter *adap, struct i2c_msg msgs[], int num,
802 bool polling)
776{ 803{
777 struct omap_i2c_dev *omap = i2c_get_adapdata(adap); 804 struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
778 int i; 805 int i;
@@ -794,7 +821,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
794 omap->set_mpu_wkup_lat(omap->dev, omap->latency); 821 omap->set_mpu_wkup_lat(omap->dev, omap->latency);
795 822
796 for (i = 0; i < num; i++) { 823 for (i = 0; i < num; i++) {
797 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); 824 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)),
825 polling);
798 if (r != 0) 826 if (r != 0)
799 break; 827 break;
800 } 828 }
@@ -813,6 +841,18 @@ out:
813 return r; 841 return r;
814} 842}
815 843
844static int
845omap_i2c_xfer_irq(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
846{
847 return omap_i2c_xfer_common(adap, msgs, num, false);
848}
849
850static int
851omap_i2c_xfer_polling(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
852{
853 return omap_i2c_xfer_common(adap, msgs, num, true);
854}
855
816static u32 856static u32
817omap_i2c_func(struct i2c_adapter *adap) 857omap_i2c_func(struct i2c_adapter *adap)
818{ 858{
@@ -1035,10 +1075,8 @@ omap_i2c_isr(int irq, void *dev_id)
1035 return ret; 1075 return ret;
1036} 1076}
1037 1077
1038static irqreturn_t 1078static int omap_i2c_xfer_data(struct omap_i2c_dev *omap)
1039omap_i2c_isr_thread(int this_irq, void *dev_id)
1040{ 1079{
1041 struct omap_i2c_dev *omap = dev_id;
1042 u16 bits; 1080 u16 bits;
1043 u16 stat; 1081 u16 stat;
1044 int err = 0, count = 0; 1082 int err = 0, count = 0;
@@ -1056,7 +1094,8 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
1056 1094
1057 if (!stat) { 1095 if (!stat) {
1058 /* my work here is done */ 1096 /* my work here is done */
1059 goto out; 1097 err = -EAGAIN;
1098 break;
1060 } 1099 }
1061 1100
1062 dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat); 1101 dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat);
@@ -1165,14 +1204,25 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
1165 } 1204 }
1166 } while (stat); 1205 } while (stat);
1167 1206
1168 omap_i2c_complete_cmd(omap, err); 1207 return err;
1208}
1209
1210static irqreturn_t
1211omap_i2c_isr_thread(int this_irq, void *dev_id)
1212{
1213 int ret;
1214 struct omap_i2c_dev *omap = dev_id;
1215
1216 ret = omap_i2c_xfer_data(omap);
1217 if (ret != -EAGAIN)
1218 omap_i2c_complete_cmd(omap, ret);
1169 1219
1170out:
1171 return IRQ_HANDLED; 1220 return IRQ_HANDLED;
1172} 1221}
1173 1222
1174static const struct i2c_algorithm omap_i2c_algo = { 1223static const struct i2c_algorithm omap_i2c_algo = {
1175 .master_xfer = omap_i2c_xfer, 1224 .master_xfer = omap_i2c_xfer_irq,
1225 .master_xfer_atomic = omap_i2c_xfer_polling,
1176 .functionality = omap_i2c_func, 1226 .functionality = omap_i2c_func,
1177}; 1227};
1178 1228
diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c
index 90946a8b9a75..e9a0514ae166 100644
--- a/drivers/i2c/busses/i2c-piix4.c
+++ b/drivers/i2c/busses/i2c-piix4.c
@@ -19,6 +19,7 @@
19 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100 19 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
20 ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800 20 ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
21 AMD Hudson-2, ML, CZ 21 AMD Hudson-2, ML, CZ
22 Hygon CZ
22 SMSC Victory66 23 SMSC Victory66
23 24
24 Note: we assume there can only be one device, with one or more 25 Note: we assume there can only be one device, with one or more
@@ -289,7 +290,9 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
289 PIIX4_dev->revision >= 0x41) || 290 PIIX4_dev->revision >= 0x41) ||
290 (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && 291 (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
291 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS && 292 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
292 PIIX4_dev->revision >= 0x49)) 293 PIIX4_dev->revision >= 0x49) ||
294 (PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON &&
295 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS))
293 smb_en = 0x00; 296 smb_en = 0x00;
294 else 297 else
295 smb_en = (aux) ? 0x28 : 0x2c; 298 smb_en = (aux) ? 0x28 : 0x2c;
@@ -361,7 +364,8 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
361 piix4_smba, i2ccfg >> 4); 364 piix4_smba, i2ccfg >> 4);
362 365
363 /* Find which register is used for port selection */ 366 /* Find which register is used for port selection */
364 if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD) { 367 if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD ||
368 PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) {
365 switch (PIIX4_dev->device) { 369 switch (PIIX4_dev->device) {
366 case PCI_DEVICE_ID_AMD_KERNCZ_SMBUS: 370 case PCI_DEVICE_ID_AMD_KERNCZ_SMBUS:
367 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ; 371 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ;
@@ -794,6 +798,7 @@ static const struct pci_device_id piix4_ids[] = {
794 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) }, 798 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
795 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) }, 799 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
796 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) }, 800 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
801 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
797 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 802 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
798 PCI_DEVICE_ID_SERVERWORKS_OSB4) }, 803 PCI_DEVICE_ID_SERVERWORKS_OSB4) },
799 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 804 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
@@ -904,11 +909,13 @@ static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id)
904 if ((dev->vendor == PCI_VENDOR_ID_ATI && 909 if ((dev->vendor == PCI_VENDOR_ID_ATI &&
905 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS && 910 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
906 dev->revision >= 0x40) || 911 dev->revision >= 0x40) ||
907 dev->vendor == PCI_VENDOR_ID_AMD) { 912 dev->vendor == PCI_VENDOR_ID_AMD ||
913 dev->vendor == PCI_VENDOR_ID_HYGON) {
908 bool notify_imc = false; 914 bool notify_imc = false;
909 is_sb800 = true; 915 is_sb800 = true;
910 916
911 if (dev->vendor == PCI_VENDOR_ID_AMD && 917 if ((dev->vendor == PCI_VENDOR_ID_AMD ||
918 dev->vendor == PCI_VENDOR_ID_HYGON) &&
912 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) { 919 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) {
913 u8 imc; 920 u8 imc;
914 921
diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
index a7578f6da979..d39a4606f72d 100644
--- a/drivers/i2c/busses/i2c-rcar.c
+++ b/drivers/i2c/busses/i2c-rcar.c
@@ -85,6 +85,7 @@
85/* ICFBSCR */ 85/* ICFBSCR */
86#define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */ 86#define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */
87 87
88#define RCAR_MIN_DMA_LEN 8
88 89
89#define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) 90#define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
90#define RCAR_BUS_PHASE_DATA (MDBS | MIE) 91#define RCAR_BUS_PHASE_DATA (MDBS | MIE)
@@ -398,7 +399,7 @@ static void rcar_i2c_dma_callback(void *data)
398 rcar_i2c_dma_unmap(priv); 399 rcar_i2c_dma_unmap(priv);
399} 400}
400 401
401static void rcar_i2c_dma(struct rcar_i2c_priv *priv) 402static bool rcar_i2c_dma(struct rcar_i2c_priv *priv)
402{ 403{
403 struct device *dev = rcar_i2c_priv_to_dev(priv); 404 struct device *dev = rcar_i2c_priv_to_dev(priv);
404 struct i2c_msg *msg = priv->msg; 405 struct i2c_msg *msg = priv->msg;
@@ -412,9 +413,9 @@ static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
412 int len; 413 int len;
413 414
414 /* Do various checks to see if DMA is feasible at all */ 415 /* Do various checks to see if DMA is feasible at all */
415 if (IS_ERR(chan) || msg->len < 8 || !(msg->flags & I2C_M_DMA_SAFE) || 416 if (IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN ||
416 (read && priv->flags & ID_P_NO_RXDMA)) 417 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA))
417 return; 418 return false;
418 419
419 if (read) { 420 if (read) {
420 /* 421 /*
@@ -434,7 +435,7 @@ static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
434 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 435 dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
435 if (dma_mapping_error(chan->device->dev, dma_addr)) { 436 if (dma_mapping_error(chan->device->dev, dma_addr)) {
436 dev_dbg(dev, "dma map failed, using PIO\n"); 437 dev_dbg(dev, "dma map failed, using PIO\n");
437 return; 438 return false;
438 } 439 }
439 440
440 sg_dma_len(&priv->sg) = len; 441 sg_dma_len(&priv->sg) = len;
@@ -448,7 +449,7 @@ static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
448 if (!txdesc) { 449 if (!txdesc) {
449 dev_dbg(dev, "dma prep slave sg failed, using PIO\n"); 450 dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
450 rcar_i2c_cleanup_dma(priv); 451 rcar_i2c_cleanup_dma(priv);
451 return; 452 return false;
452 } 453 }
453 454
454 txdesc->callback = rcar_i2c_dma_callback; 455 txdesc->callback = rcar_i2c_dma_callback;
@@ -458,7 +459,7 @@ static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
458 if (dma_submit_error(cookie)) { 459 if (dma_submit_error(cookie)) {
459 dev_dbg(dev, "submitting dma failed, using PIO\n"); 460 dev_dbg(dev, "submitting dma failed, using PIO\n");
460 rcar_i2c_cleanup_dma(priv); 461 rcar_i2c_cleanup_dma(priv);
461 return; 462 return false;
462 } 463 }
463 464
464 /* Enable DMA Master Received/Transmitted */ 465 /* Enable DMA Master Received/Transmitted */
@@ -468,6 +469,7 @@ static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
468 rcar_i2c_write(priv, ICDMAER, TMDMAE); 469 rcar_i2c_write(priv, ICDMAER, TMDMAE);
469 470
470 dma_async_issue_pending(chan); 471 dma_async_issue_pending(chan);
472 return true;
471} 473}
472 474
473static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) 475static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
@@ -478,6 +480,10 @@ static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
478 if (!(msr & MDE)) 480 if (!(msr & MDE))
479 return; 481 return;
480 482
483 /* Check if DMA can be enabled and take over */
484 if (priv->pos == 1 && rcar_i2c_dma(priv))
485 return;
486
481 if (priv->pos < msg->len) { 487 if (priv->pos < msg->len) {
482 /* 488 /*
483 * Prepare next data to ICRXTX register. 489 * Prepare next data to ICRXTX register.
@@ -488,13 +494,6 @@ static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
488 */ 494 */
489 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); 495 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
490 priv->pos++; 496 priv->pos++;
491
492 /*
493 * Try to use DMA to transmit the rest of the data if
494 * address transfer phase just finished.
495 */
496 if (msr & MAT)
497 rcar_i2c_dma(priv);
498 } else { 497 } else {
499 /* 498 /*
500 * The last data was pushed to ICRXTX on _PREV_ empty irq. 499 * The last data was pushed to ICRXTX on _PREV_ empty irq.
@@ -921,6 +920,9 @@ static int rcar_i2c_probe(struct platform_device *pdev)
921 struct i2c_timings i2c_t; 920 struct i2c_timings i2c_t;
922 int irq, ret; 921 int irq, ret;
923 922
923 /* Otherwise logic will break because some bytes must always use PIO */
924 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length");
925
924 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 926 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
925 if (!priv) 927 if (!priv)
926 return -ENOMEM; 928 return -ENOMEM;
diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index b75ff144b570..f31413fd9521 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -43,6 +43,7 @@
43#include <linux/module.h> 43#include <linux/module.h>
44#include <linux/of.h> 44#include <linux/of.h>
45#include <linux/platform_device.h> 45#include <linux/platform_device.h>
46#include <linux/pm_runtime.h>
46 47
47#define RIIC_ICCR1 0x00 48#define RIIC_ICCR1 0x00
48#define RIIC_ICCR2 0x04 49#define RIIC_ICCR2 0x04
@@ -112,12 +113,10 @@ static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
112{ 113{
113 struct riic_dev *riic = i2c_get_adapdata(adap); 114 struct riic_dev *riic = i2c_get_adapdata(adap);
114 unsigned long time_left; 115 unsigned long time_left;
115 int i, ret; 116 int i;
116 u8 start_bit; 117 u8 start_bit;
117 118
118 ret = clk_prepare_enable(riic->clk); 119 pm_runtime_get_sync(adap->dev.parent);
119 if (ret)
120 return ret;
121 120
122 if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) { 121 if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) {
123 riic->err = -EBUSY; 122 riic->err = -EBUSY;
@@ -150,7 +149,7 @@ static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
150 } 149 }
151 150
152 out: 151 out:
153 clk_disable_unprepare(riic->clk); 152 pm_runtime_put(adap->dev.parent);
154 153
155 return riic->err ?: num; 154 return riic->err ?: num;
156} 155}
@@ -281,20 +280,18 @@ static const struct i2c_algorithm riic_algo = {
281 280
282static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) 281static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
283{ 282{
284 int ret; 283 int ret = 0;
285 unsigned long rate; 284 unsigned long rate;
286 int total_ticks, cks, brl, brh; 285 int total_ticks, cks, brl, brh;
287 286
288 ret = clk_prepare_enable(riic->clk); 287 pm_runtime_get_sync(riic->adapter.dev.parent);
289 if (ret)
290 return ret;
291 288
292 if (t->bus_freq_hz > 400000) { 289 if (t->bus_freq_hz > 400000) {
293 dev_err(&riic->adapter.dev, 290 dev_err(&riic->adapter.dev,
294 "unsupported bus speed (%dHz). 400000 max\n", 291 "unsupported bus speed (%dHz). 400000 max\n",
295 t->bus_freq_hz); 292 t->bus_freq_hz);
296 clk_disable_unprepare(riic->clk); 293 ret = -EINVAL;
297 return -EINVAL; 294 goto out;
298 } 295 }
299 296
300 rate = clk_get_rate(riic->clk); 297 rate = clk_get_rate(riic->clk);
@@ -332,8 +329,8 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
332 if (brl > (0x1F + 3)) { 329 if (brl > (0x1F + 3)) {
333 dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n", 330 dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
334 (unsigned long)t->bus_freq_hz); 331 (unsigned long)t->bus_freq_hz);
335 clk_disable_unprepare(riic->clk); 332 ret = -EINVAL;
336 return -EINVAL; 333 goto out;
337 } 334 }
338 335
339 brh = total_ticks - brl; 336 brh = total_ticks - brl;
@@ -378,9 +375,9 @@ static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
378 375
379 riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); 376 riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
380 377
381 clk_disable_unprepare(riic->clk); 378out:
382 379 pm_runtime_put(riic->adapter.dev.parent);
383 return 0; 380 return ret;
384} 381}
385 382
386static struct riic_irq_desc riic_irqs[] = { 383static struct riic_irq_desc riic_irqs[] = {
@@ -439,28 +436,36 @@ static int riic_i2c_probe(struct platform_device *pdev)
439 436
440 i2c_parse_fw_timings(&pdev->dev, &i2c_t, true); 437 i2c_parse_fw_timings(&pdev->dev, &i2c_t, true);
441 438
439 pm_runtime_enable(&pdev->dev);
440
442 ret = riic_init_hw(riic, &i2c_t); 441 ret = riic_init_hw(riic, &i2c_t);
443 if (ret) 442 if (ret)
444 return ret; 443 goto out;
445
446 444
447 ret = i2c_add_adapter(adap); 445 ret = i2c_add_adapter(adap);
448 if (ret) 446 if (ret)
449 return ret; 447 goto out;
450 448
451 platform_set_drvdata(pdev, riic); 449 platform_set_drvdata(pdev, riic);
452 450
453 dev_info(&pdev->dev, "registered with %dHz bus speed\n", 451 dev_info(&pdev->dev, "registered with %dHz bus speed\n",
454 i2c_t.bus_freq_hz); 452 i2c_t.bus_freq_hz);
455 return 0; 453 return 0;
454
455out:
456 pm_runtime_disable(&pdev->dev);
457 return ret;
456} 458}
457 459
458static int riic_i2c_remove(struct platform_device *pdev) 460static int riic_i2c_remove(struct platform_device *pdev)
459{ 461{
460 struct riic_dev *riic = platform_get_drvdata(pdev); 462 struct riic_dev *riic = platform_get_drvdata(pdev);
461 463
464 pm_runtime_get_sync(&pdev->dev);
462 writeb(0, riic->base + RIIC_ICIER); 465 writeb(0, riic->base + RIIC_ICIER);
466 pm_runtime_put(&pdev->dev);
463 i2c_del_adapter(&riic->adapter); 467 i2c_del_adapter(&riic->adapter);
468 pm_runtime_disable(&pdev->dev);
464 469
465 return 0; 470 return 0;
466} 471}
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index 4284fc991cfd..48337bef5b87 100644
--- a/drivers/i2c/busses/i2c-stm32f7.c
+++ b/drivers/i2c/busses/i2c-stm32f7.c
@@ -476,8 +476,12 @@ static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
476 476
477 list_add_tail(&v->node, 477 list_add_tail(&v->node,
478 &solutions); 478 &solutions);
479 break;
479 } 480 }
480 } 481 }
482
483 if (p_prev == p)
484 break;
481 } 485 }
482 } 486 }
483 487
diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c
index 5503fa171df0..743c161b22c5 100644
--- a/drivers/i2c/busses/i2c-stu300.c
+++ b/drivers/i2c/busses/i2c-stu300.c
@@ -328,12 +328,6 @@ static int stu300_start_and_await_event(struct stu300_dev *dev,
328{ 328{
329 int ret; 329 int ret;
330 330
331 if (unlikely(irqs_disabled())) {
332 /* TODO: implement polling for this case if need be. */
333 WARN(1, "irqs are disabled, cannot poll for event\n");
334 return -EIO;
335 }
336
337 /* Lock command issue, fill in an event we wait for */ 331 /* Lock command issue, fill in an event we wait for */
338 spin_lock_irq(&dev->cmd_issue_lock); 332 spin_lock_irq(&dev->cmd_issue_lock);
339 init_completion(&dev->cmd_complete); 333 init_completion(&dev->cmd_complete);
@@ -380,13 +374,6 @@ static int stu300_await_event(struct stu300_dev *dev,
380{ 374{
381 int ret; 375 int ret;
382 376
383 if (unlikely(irqs_disabled())) {
384 /* TODO: implement polling for this case if need be. */
385 dev_err(&dev->pdev->dev, "irqs are disabled on this "
386 "system!\n");
387 return -EIO;
388 }
389
390 /* Is it already here? */ 377 /* Is it already here? */
391 spin_lock_irq(&dev->cmd_issue_lock); 378 spin_lock_irq(&dev->cmd_issue_lock);
392 dev->cmd_err = STU300_ERROR_NONE; 379 dev->cmd_err = STU300_ERROR_NONE;
@@ -846,6 +833,13 @@ static int stu300_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
846 return num; 833 return num;
847} 834}
848 835
836static int stu300_xfer_todo(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
837{
838 /* TODO: implement polling for this case if need be. */
839 WARN(1, "%s: atomic transfers not implemented\n", dev_name(&adap->dev));
840 return -EOPNOTSUPP;
841}
842
849static u32 stu300_func(struct i2c_adapter *adap) 843static u32 stu300_func(struct i2c_adapter *adap)
850{ 844{
851 /* This is the simplest thing you can think of... */ 845 /* This is the simplest thing you can think of... */
@@ -853,8 +847,9 @@ static u32 stu300_func(struct i2c_adapter *adap)
853} 847}
854 848
855static const struct i2c_algorithm stu300_algo = { 849static const struct i2c_algorithm stu300_algo = {
856 .master_xfer = stu300_xfer, 850 .master_xfer = stu300_xfer,
857 .functionality = stu300_func, 851 .master_xfer_atomic = stu300_xfer_todo,
852 .functionality = stu300_func,
858}; 853};
859 854
860static const struct i2c_adapter_quirks stu300_quirks = { 855static const struct i2c_adapter_quirks stu300_quirks = {
diff --git a/drivers/i2c/busses/i2c-tegra-bpmp.c b/drivers/i2c/busses/i2c-tegra-bpmp.c
index f6cd35d0a2ac..9bb085793a0c 100644
--- a/drivers/i2c/busses/i2c-tegra-bpmp.c
+++ b/drivers/i2c/busses/i2c-tegra-bpmp.c
@@ -207,7 +207,8 @@ static int tegra_bpmp_i2c_msg_len_check(struct i2c_msg *msgs, unsigned int num)
207 207
208static int tegra_bpmp_i2c_msg_xfer(struct tegra_bpmp_i2c *i2c, 208static int tegra_bpmp_i2c_msg_xfer(struct tegra_bpmp_i2c *i2c,
209 struct mrq_i2c_request *request, 209 struct mrq_i2c_request *request,
210 struct mrq_i2c_response *response) 210 struct mrq_i2c_response *response,
211 bool atomic)
211{ 212{
212 struct tegra_bpmp_message msg; 213 struct tegra_bpmp_message msg;
213 int err; 214 int err;
@@ -222,7 +223,7 @@ static int tegra_bpmp_i2c_msg_xfer(struct tegra_bpmp_i2c *i2c,
222 msg.rx.data = response; 223 msg.rx.data = response;
223 msg.rx.size = sizeof(*response); 224 msg.rx.size = sizeof(*response);
224 225
225 if (irqs_disabled()) 226 if (atomic)
226 err = tegra_bpmp_transfer_atomic(i2c->bpmp, &msg); 227 err = tegra_bpmp_transfer_atomic(i2c->bpmp, &msg);
227 else 228 else
228 err = tegra_bpmp_transfer(i2c->bpmp, &msg); 229 err = tegra_bpmp_transfer(i2c->bpmp, &msg);
@@ -230,8 +231,9 @@ static int tegra_bpmp_i2c_msg_xfer(struct tegra_bpmp_i2c *i2c,
230 return err; 231 return err;
231} 232}
232 233
233static int tegra_bpmp_i2c_xfer(struct i2c_adapter *adapter, 234static int tegra_bpmp_i2c_xfer_common(struct i2c_adapter *adapter,
234 struct i2c_msg *msgs, int num) 235 struct i2c_msg *msgs, int num,
236 bool atomic)
235{ 237{
236 struct tegra_bpmp_i2c *i2c = i2c_get_adapdata(adapter); 238 struct tegra_bpmp_i2c *i2c = i2c_get_adapdata(adapter);
237 struct mrq_i2c_response response; 239 struct mrq_i2c_response response;
@@ -253,7 +255,7 @@ static int tegra_bpmp_i2c_xfer(struct i2c_adapter *adapter,
253 return err; 255 return err;
254 } 256 }
255 257
256 err = tegra_bpmp_i2c_msg_xfer(i2c, &request, &response); 258 err = tegra_bpmp_i2c_msg_xfer(i2c, &request, &response, atomic);
257 if (err < 0) { 259 if (err < 0) {
258 dev_err(i2c->dev, "failed to transfer message: %d\n", err); 260 dev_err(i2c->dev, "failed to transfer message: %d\n", err);
259 return err; 261 return err;
@@ -268,6 +270,18 @@ static int tegra_bpmp_i2c_xfer(struct i2c_adapter *adapter,
268 return num; 270 return num;
269} 271}
270 272
273static int tegra_bpmp_i2c_xfer(struct i2c_adapter *adapter,
274 struct i2c_msg *msgs, int num)
275{
276 return tegra_bpmp_i2c_xfer_common(adapter, msgs, num, false);
277}
278
279static int tegra_bpmp_i2c_xfer_atomic(struct i2c_adapter *adapter,
280 struct i2c_msg *msgs, int num)
281{
282 return tegra_bpmp_i2c_xfer_common(adapter, msgs, num, true);
283}
284
271static u32 tegra_bpmp_i2c_func(struct i2c_adapter *adapter) 285static u32 tegra_bpmp_i2c_func(struct i2c_adapter *adapter)
272{ 286{
273 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR | 287 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
@@ -276,6 +290,7 @@ static u32 tegra_bpmp_i2c_func(struct i2c_adapter *adapter)
276 290
277static const struct i2c_algorithm tegra_bpmp_i2c_algo = { 291static const struct i2c_algorithm tegra_bpmp_i2c_algo = {
278 .master_xfer = tegra_bpmp_i2c_xfer, 292 .master_xfer = tegra_bpmp_i2c_xfer,
293 .master_xfer_atomic = tegra_bpmp_i2c_xfer_atomic,
279 .functionality = tegra_bpmp_i2c_func, 294 .functionality = tegra_bpmp_i2c_func,
280}; 295};
281 296
diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
index 688aa3b5f3ac..9732a81bb7dd 100644
--- a/drivers/i2c/i2c-core-base.c
+++ b/drivers/i2c/i2c-core-base.c
@@ -1871,8 +1871,10 @@ int __i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
1871 1871
1872 if (WARN_ON(!msgs || num < 1)) 1872 if (WARN_ON(!msgs || num < 1))
1873 return -EINVAL; 1873 return -EINVAL;
1874 if (WARN_ON(test_bit(I2C_ALF_IS_SUSPENDED, &adap->locked_flags))) 1874
1875 return -ESHUTDOWN; 1875 ret = __i2c_check_suspended(adap);
1876 if (ret)
1877 return ret;
1876 1878
1877 if (adap->quirks && i2c_check_for_quirks(adap, msgs, num)) 1879 if (adap->quirks && i2c_check_for_quirks(adap, msgs, num))
1878 return -EOPNOTSUPP; 1880 return -EOPNOTSUPP;
@@ -1894,7 +1896,11 @@ int __i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
1894 /* Retry automatically on arbitration loss */ 1896 /* Retry automatically on arbitration loss */
1895 orig_jiffies = jiffies; 1897 orig_jiffies = jiffies;
1896 for (ret = 0, try = 0; try <= adap->retries; try++) { 1898 for (ret = 0, try = 0; try <= adap->retries; try++) {
1897 ret = adap->algo->master_xfer(adap, msgs, num); 1899 if (i2c_in_atomic_xfer_mode() && adap->algo->master_xfer_atomic)
1900 ret = adap->algo->master_xfer_atomic(adap, msgs, num);
1901 else
1902 ret = adap->algo->master_xfer(adap, msgs, num);
1903
1898 if (ret != -EAGAIN) 1904 if (ret != -EAGAIN)
1899 break; 1905 break;
1900 if (time_after(jiffies, orig_jiffies + adap->timeout)) 1906 if (time_after(jiffies, orig_jiffies + adap->timeout))
@@ -1950,14 +1956,9 @@ int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
1950 * one (discarding status on the second message) or errno 1956 * one (discarding status on the second message) or errno
1951 * (discarding status on the first one). 1957 * (discarding status on the first one).
1952 */ 1958 */
1953 if (in_atomic() || irqs_disabled()) { 1959 ret = __i2c_lock_bus_helper(adap);
1954 ret = i2c_trylock_bus(adap, I2C_LOCK_SEGMENT); 1960 if (ret)
1955 if (!ret) 1961 return ret;
1956 /* I2C activity is ongoing. */
1957 return -EAGAIN;
1958 } else {
1959 i2c_lock_bus(adap, I2C_LOCK_SEGMENT);
1960 }
1961 1962
1962 ret = __i2c_transfer(adap, msgs, num); 1963 ret = __i2c_transfer(adap, msgs, num);
1963 i2c_unlock_bus(adap, I2C_LOCK_SEGMENT); 1964 i2c_unlock_bus(adap, I2C_LOCK_SEGMENT);
diff --git a/drivers/i2c/i2c-core-smbus.c b/drivers/i2c/i2c-core-smbus.c
index 132119112596..788d42f2aad9 100644
--- a/drivers/i2c/i2c-core-smbus.c
+++ b/drivers/i2c/i2c-core-smbus.c
@@ -20,6 +20,8 @@
20#include <linux/i2c-smbus.h> 20#include <linux/i2c-smbus.h>
21#include <linux/slab.h> 21#include <linux/slab.h>
22 22
23#include "i2c-core.h"
24
23#define CREATE_TRACE_POINTS 25#define CREATE_TRACE_POINTS
24#include <trace/events/smbus.h> 26#include <trace/events/smbus.h>
25 27
@@ -530,7 +532,10 @@ s32 i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
530{ 532{
531 s32 res; 533 s32 res;
532 534
533 i2c_lock_bus(adapter, I2C_LOCK_SEGMENT); 535 res = __i2c_lock_bus_helper(adapter);
536 if (res)
537 return res;
538
534 res = __i2c_smbus_xfer(adapter, addr, flags, read_write, 539 res = __i2c_smbus_xfer(adapter, addr, flags, read_write,
535 command, protocol, data); 540 command, protocol, data);
536 i2c_unlock_bus(adapter, I2C_LOCK_SEGMENT); 541 i2c_unlock_bus(adapter, I2C_LOCK_SEGMENT);
@@ -543,10 +548,17 @@ s32 __i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
543 unsigned short flags, char read_write, 548 unsigned short flags, char read_write,
544 u8 command, int protocol, union i2c_smbus_data *data) 549 u8 command, int protocol, union i2c_smbus_data *data)
545{ 550{
551 int (*xfer_func)(struct i2c_adapter *adap, u16 addr,
552 unsigned short flags, char read_write,
553 u8 command, int size, union i2c_smbus_data *data);
546 unsigned long orig_jiffies; 554 unsigned long orig_jiffies;
547 int try; 555 int try;
548 s32 res; 556 s32 res;
549 557
558 res = __i2c_check_suspended(adapter);
559 if (res)
560 return res;
561
550 /* If enabled, the following two tracepoints are conditional on 562 /* If enabled, the following two tracepoints are conditional on
551 * read_write and protocol. 563 * read_write and protocol.
552 */ 564 */
@@ -557,13 +569,20 @@ s32 __i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
557 569
558 flags &= I2C_M_TEN | I2C_CLIENT_PEC | I2C_CLIENT_SCCB; 570 flags &= I2C_M_TEN | I2C_CLIENT_PEC | I2C_CLIENT_SCCB;
559 571
560 if (adapter->algo->smbus_xfer) { 572 xfer_func = adapter->algo->smbus_xfer;
573 if (i2c_in_atomic_xfer_mode()) {
574 if (adapter->algo->smbus_xfer_atomic)
575 xfer_func = adapter->algo->smbus_xfer_atomic;
576 else if (adapter->algo->master_xfer_atomic)
577 xfer_func = NULL; /* fallback to I2C emulation */
578 }
579
580 if (xfer_func) {
561 /* Retry automatically on arbitration loss */ 581 /* Retry automatically on arbitration loss */
562 orig_jiffies = jiffies; 582 orig_jiffies = jiffies;
563 for (res = 0, try = 0; try <= adapter->retries; try++) { 583 for (res = 0, try = 0; try <= adapter->retries; try++) {
564 res = adapter->algo->smbus_xfer(adapter, addr, flags, 584 res = xfer_func(adapter, addr, flags, read_write,
565 read_write, command, 585 command, protocol, data);
566 protocol, data);
567 if (res != -EAGAIN) 586 if (res != -EAGAIN)
568 break; 587 break;
569 if (time_after(jiffies, 588 if (time_after(jiffies,
diff --git a/drivers/i2c/i2c-core.h b/drivers/i2c/i2c-core.h
index 37576f50fe20..c88cfef81343 100644
--- a/drivers/i2c/i2c-core.h
+++ b/drivers/i2c/i2c-core.h
@@ -29,6 +29,42 @@ extern int __i2c_first_dynamic_bus_num;
29 29
30int i2c_check_7bit_addr_validity_strict(unsigned short addr); 30int i2c_check_7bit_addr_validity_strict(unsigned short addr);
31 31
32/*
33 * We only allow atomic transfers for very late communication, e.g. to send
34 * the powerdown command to a PMIC. Atomic transfers are a corner case and not
35 * for generic use!
36 */
37static inline bool i2c_in_atomic_xfer_mode(void)
38{
39 return system_state > SYSTEM_RUNNING && irqs_disabled();
40}
41
42static inline int __i2c_lock_bus_helper(struct i2c_adapter *adap)
43{
44 int ret = 0;
45
46 if (i2c_in_atomic_xfer_mode()) {
47 WARN(!adap->algo->master_xfer_atomic && !adap->algo->smbus_xfer_atomic,
48 "No atomic I2C transfer handler for '%s'\n", dev_name(&adap->dev));
49 ret = i2c_trylock_bus(adap, I2C_LOCK_SEGMENT) ? 0 : -EAGAIN;
50 } else {
51 i2c_lock_bus(adap, I2C_LOCK_SEGMENT);
52 }
53
54 return ret;
55}
56
57static inline int __i2c_check_suspended(struct i2c_adapter *adap)
58{
59 if (test_bit(I2C_ALF_IS_SUSPENDED, &adap->locked_flags)) {
60 if (!test_and_set_bit(I2C_ALF_SUSPEND_REPORTED, &adap->locked_flags))
61 dev_WARN(&adap->dev, "Transfer while suspended\n");
62 return -ESHUTDOWN;
63 }
64
65 return 0;
66}
67
32#ifdef CONFIG_ACPI 68#ifdef CONFIG_ACPI
33const struct acpi_device_id * 69const struct acpi_device_id *
34i2c_acpi_match_device(const struct acpi_device_id *matches, 70i2c_acpi_match_device(const struct acpi_device_id *matches,
diff --git a/drivers/i2c/i2c-mux.c b/drivers/i2c/i2c-mux.c
index f330690b4125..603252fa1284 100644
--- a/drivers/i2c/i2c-mux.c
+++ b/drivers/i2c/i2c-mux.c
@@ -310,12 +310,18 @@ int i2c_mux_add_adapter(struct i2c_mux_core *muxc,
310 else 310 else
311 priv->algo.master_xfer = __i2c_mux_master_xfer; 311 priv->algo.master_xfer = __i2c_mux_master_xfer;
312 } 312 }
313 if (parent->algo->master_xfer_atomic)
314 priv->algo.master_xfer_atomic = priv->algo.master_xfer;
315
313 if (parent->algo->smbus_xfer) { 316 if (parent->algo->smbus_xfer) {
314 if (muxc->mux_locked) 317 if (muxc->mux_locked)
315 priv->algo.smbus_xfer = i2c_mux_smbus_xfer; 318 priv->algo.smbus_xfer = i2c_mux_smbus_xfer;
316 else 319 else
317 priv->algo.smbus_xfer = __i2c_mux_smbus_xfer; 320 priv->algo.smbus_xfer = __i2c_mux_smbus_xfer;
318 } 321 }
322 if (parent->algo->smbus_xfer_atomic)
323 priv->algo.smbus_xfer_atomic = priv->algo.smbus_xfer;
324
319 priv->algo.functionality = i2c_mux_functionality; 325 priv->algo.functionality = i2c_mux_functionality;
320 326
321 /* Now fill out new adapter structure */ 327 /* Now fill out new adapter structure */
diff --git a/drivers/i2c/muxes/i2c-demux-pinctrl.c b/drivers/i2c/muxes/i2c-demux-pinctrl.c
index 035032e20327..4eecffc26527 100644
--- a/drivers/i2c/muxes/i2c-demux-pinctrl.c
+++ b/drivers/i2c/muxes/i2c-demux-pinctrl.c
@@ -99,6 +99,8 @@ static int i2c_demux_activate_master(struct i2c_demux_pinctrl_priv *priv, u32 ne
99 99
100 /* Now fill out current adapter structure. cur_chan must be up to date */ 100 /* Now fill out current adapter structure. cur_chan must be up to date */
101 priv->algo.master_xfer = i2c_demux_master_xfer; 101 priv->algo.master_xfer = i2c_demux_master_xfer;
102 if (adap->algo->master_xfer_atomic)
103 priv->algo.master_xfer_atomic = i2c_demux_master_xfer;
102 priv->algo.functionality = i2c_demux_functionality; 104 priv->algo.functionality = i2c_demux_functionality;
103 105
104 snprintf(priv->cur_adap.name, sizeof(priv->cur_adap.name), 106 snprintf(priv->cur_adap.name, sizeof(priv->cur_adap.name),
@@ -219,8 +221,8 @@ static int i2c_demux_pinctrl_probe(struct platform_device *pdev)
219 return -EINVAL; 221 return -EINVAL;
220 } 222 }
221 223
222 priv = devm_kzalloc(&pdev->dev, sizeof(*priv) 224 priv = devm_kzalloc(&pdev->dev, struct_size(priv, chan, num_chan),
223 + num_chan * sizeof(struct i2c_demux_pinctrl_chan), GFP_KERNEL); 225 GFP_KERNEL);
224 226
225 props = devm_kcalloc(&pdev->dev, num_chan, sizeof(*props), GFP_KERNEL); 227 props = devm_kcalloc(&pdev->dev, num_chan, sizeof(*props), GFP_KERNEL);
226 228
diff --git a/drivers/i2c/muxes/i2c-mux-pca9541.c b/drivers/i2c/muxes/i2c-mux-pca9541.c
index 9e75d6b9140b..50e1fb4aedf5 100644
--- a/drivers/i2c/muxes/i2c-mux-pca9541.c
+++ b/drivers/i2c/muxes/i2c-mux-pca9541.c
@@ -22,7 +22,6 @@
22#include <linux/i2c-mux.h> 22#include <linux/i2c-mux.h>
23#include <linux/jiffies.h> 23#include <linux/jiffies.h>
24#include <linux/module.h> 24#include <linux/module.h>
25#include <linux/platform_data/pca954x.h>
26#include <linux/slab.h> 25#include <linux/slab.h>
27 26
28/* 27/*
@@ -287,10 +286,8 @@ static int pca9541_probe(struct i2c_client *client,
287 const struct i2c_device_id *id) 286 const struct i2c_device_id *id)
288{ 287{
289 struct i2c_adapter *adap = client->adapter; 288 struct i2c_adapter *adap = client->adapter;
290 struct pca954x_platform_data *pdata = dev_get_platdata(&client->dev);
291 struct i2c_mux_core *muxc; 289 struct i2c_mux_core *muxc;
292 struct pca9541 *data; 290 struct pca9541 *data;
293 int force;
294 int ret; 291 int ret;
295 292
296 if (!i2c_check_functionality(adap, I2C_FUNC_SMBUS_BYTE_DATA)) 293 if (!i2c_check_functionality(adap, I2C_FUNC_SMBUS_BYTE_DATA))
@@ -306,9 +303,6 @@ static int pca9541_probe(struct i2c_client *client,
306 303
307 /* Create mux adapter */ 304 /* Create mux adapter */
308 305
309 force = 0;
310 if (pdata)
311 force = pdata->modes[0].adap_id;
312 muxc = i2c_mux_alloc(adap, &client->dev, 1, sizeof(*data), 306 muxc = i2c_mux_alloc(adap, &client->dev, 1, sizeof(*data),
313 I2C_MUX_ARBITRATOR, 307 I2C_MUX_ARBITRATOR,
314 pca9541_select_chan, pca9541_release_chan); 308 pca9541_select_chan, pca9541_release_chan);
@@ -320,7 +314,7 @@ static int pca9541_probe(struct i2c_client *client,
320 314
321 i2c_set_clientdata(client, muxc); 315 i2c_set_clientdata(client, muxc);
322 316
323 ret = i2c_mux_add_adapter(muxc, force, 0, 0); 317 ret = i2c_mux_add_adapter(muxc, 0, 0, 0);
324 if (ret) 318 if (ret)
325 return ret; 319 return ret;
326 320
diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mux-pca954x.c
index bfabf985e830..923aa3a5a3dc 100644
--- a/drivers/i2c/muxes/i2c-mux-pca954x.c
+++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
@@ -46,10 +46,10 @@
46#include <linux/of.h> 46#include <linux/of.h>
47#include <linux/of_device.h> 47#include <linux/of_device.h>
48#include <linux/of_irq.h> 48#include <linux/of_irq.h>
49#include <linux/platform_data/pca954x.h>
50#include <linux/pm.h> 49#include <linux/pm.h>
51#include <linux/slab.h> 50#include <linux/slab.h>
52#include <linux/spinlock.h> 51#include <linux/spinlock.h>
52#include <dt-bindings/mux/mux.h>
53 53
54#define PCA954X_MAX_NCHANS 8 54#define PCA954X_MAX_NCHANS 8
55 55
@@ -85,7 +85,9 @@ struct pca954x {
85 const struct chip_desc *chip; 85 const struct chip_desc *chip;
86 86
87 u8 last_chan; /* last register value */ 87 u8 last_chan; /* last register value */
88 u8 deselect; 88 /* MUX_IDLE_AS_IS, MUX_IDLE_DISCONNECT or >= 0 for channel */
89 s8 idle_state;
90
89 struct i2c_client *client; 91 struct i2c_client *client;
90 92
91 struct irq_domain *irq; 93 struct irq_domain *irq;
@@ -254,15 +256,71 @@ static int pca954x_deselect_mux(struct i2c_mux_core *muxc, u32 chan)
254{ 256{
255 struct pca954x *data = i2c_mux_priv(muxc); 257 struct pca954x *data = i2c_mux_priv(muxc);
256 struct i2c_client *client = data->client; 258 struct i2c_client *client = data->client;
259 s8 idle_state;
260
261 idle_state = READ_ONCE(data->idle_state);
262 if (idle_state >= 0)
263 /* Set the mux back to a predetermined channel */
264 return pca954x_select_chan(muxc, idle_state);
265
266 if (idle_state == MUX_IDLE_DISCONNECT) {
267 /* Deselect active channel */
268 data->last_chan = 0;
269 return pca954x_reg_write(muxc->parent, client,
270 data->last_chan);
271 }
257 272
258 if (!(data->deselect & (1 << chan))) 273 /* otherwise leave as-is */
259 return 0;
260 274
261 /* Deselect active channel */ 275 return 0;
262 data->last_chan = 0; 276}
263 return pca954x_reg_write(muxc->parent, client, data->last_chan); 277
278static ssize_t idle_state_show(struct device *dev,
279 struct device_attribute *attr,
280 char *buf)
281{
282 struct i2c_client *client = to_i2c_client(dev);
283 struct i2c_mux_core *muxc = i2c_get_clientdata(client);
284 struct pca954x *data = i2c_mux_priv(muxc);
285
286 return sprintf(buf, "%d\n", READ_ONCE(data->idle_state));
264} 287}
265 288
289static ssize_t idle_state_store(struct device *dev,
290 struct device_attribute *attr,
291 const char *buf, size_t count)
292{
293 struct i2c_client *client = to_i2c_client(dev);
294 struct i2c_mux_core *muxc = i2c_get_clientdata(client);
295 struct pca954x *data = i2c_mux_priv(muxc);
296 int val;
297 int ret;
298
299 ret = kstrtoint(buf, 0, &val);
300 if (ret < 0)
301 return ret;
302
303 if (val != MUX_IDLE_AS_IS && val != MUX_IDLE_DISCONNECT &&
304 (val < 0 || val >= data->chip->nchans))
305 return -EINVAL;
306
307 i2c_lock_bus(muxc->parent, I2C_LOCK_SEGMENT);
308
309 WRITE_ONCE(data->idle_state, val);
310 /*
311 * Set the mux into a state consistent with the new
312 * idle_state.
313 */
314 if (data->last_chan || val != MUX_IDLE_DISCONNECT)
315 ret = pca954x_deselect_mux(muxc, 0);
316
317 i2c_unlock_bus(muxc->parent, I2C_LOCK_SEGMENT);
318
319 return ret < 0 ? ret : count;
320}
321
322static DEVICE_ATTR_RW(idle_state);
323
266static irqreturn_t pca954x_irq_handler(int irq, void *dev_id) 324static irqreturn_t pca954x_irq_handler(int irq, void *dev_id)
267{ 325{
268 struct pca954x *data = dev_id; 326 struct pca954x *data = dev_id;
@@ -329,8 +387,11 @@ static int pca954x_irq_setup(struct i2c_mux_core *muxc)
329static void pca954x_cleanup(struct i2c_mux_core *muxc) 387static void pca954x_cleanup(struct i2c_mux_core *muxc)
330{ 388{
331 struct pca954x *data = i2c_mux_priv(muxc); 389 struct pca954x *data = i2c_mux_priv(muxc);
390 struct i2c_client *client = data->client;
332 int c, irq; 391 int c, irq;
333 392
393 device_remove_file(&client->dev, &dev_attr_idle_state);
394
334 if (data->irq) { 395 if (data->irq) {
335 for (c = 0; c < data->chip->nchans; c++) { 396 for (c = 0; c < data->chip->nchans; c++) {
336 irq = irq_find_mapping(data->irq, c); 397 irq = irq_find_mapping(data->irq, c);
@@ -348,14 +409,13 @@ static int pca954x_probe(struct i2c_client *client,
348 const struct i2c_device_id *id) 409 const struct i2c_device_id *id)
349{ 410{
350 struct i2c_adapter *adap = client->adapter; 411 struct i2c_adapter *adap = client->adapter;
351 struct pca954x_platform_data *pdata = dev_get_platdata(&client->dev);
352 struct device *dev = &client->dev; 412 struct device *dev = &client->dev;
353 struct device_node *np = dev->of_node; 413 struct device_node *np = dev->of_node;
354 bool idle_disconnect_dt; 414 bool idle_disconnect_dt;
355 struct gpio_desc *gpio; 415 struct gpio_desc *gpio;
356 int num, force, class;
357 struct i2c_mux_core *muxc; 416 struct i2c_mux_core *muxc;
358 struct pca954x *data; 417 struct pca954x *data;
418 int num;
359 int ret; 419 int ret;
360 420
361 if (!i2c_check_functionality(adap, I2C_FUNC_SMBUS_BYTE)) 421 if (!i2c_check_functionality(adap, I2C_FUNC_SMBUS_BYTE))
@@ -412,9 +472,12 @@ static int pca954x_probe(struct i2c_client *client,
412 } 472 }
413 473
414 data->last_chan = 0; /* force the first selection */ 474 data->last_chan = 0; /* force the first selection */
475 data->idle_state = MUX_IDLE_AS_IS;
415 476
416 idle_disconnect_dt = np && 477 idle_disconnect_dt = np &&
417 of_property_read_bool(np, "i2c-mux-idle-disconnect"); 478 of_property_read_bool(np, "i2c-mux-idle-disconnect");
479 if (idle_disconnect_dt)
480 data->idle_state = MUX_IDLE_DISCONNECT;
418 481
419 ret = pca954x_irq_setup(muxc); 482 ret = pca954x_irq_setup(muxc);
420 if (ret) 483 if (ret)
@@ -422,24 +485,7 @@ static int pca954x_probe(struct i2c_client *client,
422 485
423 /* Now create an adapter for each channel */ 486 /* Now create an adapter for each channel */
424 for (num = 0; num < data->chip->nchans; num++) { 487 for (num = 0; num < data->chip->nchans; num++) {
425 bool idle_disconnect_pd = false; 488 ret = i2c_mux_add_adapter(muxc, 0, num, 0);
426
427 force = 0; /* dynamic adap number */
428 class = 0; /* no class by default */
429 if (pdata) {
430 if (num < pdata->num_modes) {
431 /* force static number */
432 force = pdata->modes[num].adap_id;
433 class = pdata->modes[num].class;
434 } else
435 /* discard unconfigured channels */
436 break;
437 idle_disconnect_pd = pdata->modes[num].deselect_on_exit;
438 }
439 data->deselect |= (idle_disconnect_pd ||
440 idle_disconnect_dt) << num;
441
442 ret = i2c_mux_add_adapter(muxc, force, num, class);
443 if (ret) 489 if (ret)
444 goto fail_cleanup; 490 goto fail_cleanup;
445 } 491 }
@@ -453,6 +499,12 @@ static int pca954x_probe(struct i2c_client *client,
453 goto fail_cleanup; 499 goto fail_cleanup;
454 } 500 }
455 501
502 /*
503 * The attr probably isn't going to be needed in most cases,
504 * so don't fail completely on error.
505 */
506 device_create_file(dev, &dev_attr_idle_state);
507
456 dev_info(dev, "registered %d multiplexed busses for I2C %s %s\n", 508 dev_info(dev, "registered %d multiplexed busses for I2C %s %s\n",
457 num, data->chip->muxtype == pca954x_ismux 509 num, data->chip->muxtype == pca954x_ismux
458 ? "mux" : "switch", client->name); 510 ? "mux" : "switch", client->name);
diff --git a/include/linux/i2c-algo-bit.h b/include/linux/i2c-algo-bit.h
index 69045df78e2d..7fd5575a368f 100644
--- a/include/linux/i2c-algo-bit.h
+++ b/include/linux/i2c-algo-bit.h
@@ -33,6 +33,7 @@ struct i2c_algo_bit_data {
33 minimum 5 us for standard-mode I2C and SMBus, 33 minimum 5 us for standard-mode I2C and SMBus,
34 maximum 50 us for SMBus */ 34 maximum 50 us for SMBus */
35 int timeout; /* in jiffies */ 35 int timeout; /* in jiffies */
36 bool can_do_atomic; /* callbacks don't sleep, we can be atomic */
36}; 37};
37 38
38int i2c_bit_add_bus(struct i2c_adapter *); 39int i2c_bit_add_bus(struct i2c_adapter *);
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 383510b4f083..be27062f8ed1 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -499,9 +499,13 @@ i2c_register_board_info(int busnum, struct i2c_board_info const *info,
499 * @master_xfer: Issue a set of i2c transactions to the given I2C adapter 499 * @master_xfer: Issue a set of i2c transactions to the given I2C adapter
500 * defined by the msgs array, with num messages available to transfer via 500 * defined by the msgs array, with num messages available to transfer via
501 * the adapter specified by adap. 501 * the adapter specified by adap.
502 * @master_xfer_atomic: same as @master_xfer. Yet, only using atomic context
503 * so e.g. PMICs can be accessed very late before shutdown. Optional.
502 * @smbus_xfer: Issue smbus transactions to the given I2C adapter. If this 504 * @smbus_xfer: Issue smbus transactions to the given I2C adapter. If this
503 * is not present, then the bus layer will try and convert the SMBus calls 505 * is not present, then the bus layer will try and convert the SMBus calls
504 * into I2C transfers instead. 506 * into I2C transfers instead.
507 * @smbus_xfer_atomic: same as @smbus_xfer. Yet, only using atomic context
508 * so e.g. PMICs can be accessed very late before shutdown. Optional.
505 * @functionality: Return the flags that this algorithm/adapter pair supports 509 * @functionality: Return the flags that this algorithm/adapter pair supports
506 * from the I2C_FUNC_* flags. 510 * from the I2C_FUNC_* flags.
507 * @reg_slave: Register given client to I2C slave mode of this adapter 511 * @reg_slave: Register given client to I2C slave mode of this adapter
@@ -512,25 +516,33 @@ i2c_register_board_info(int busnum, struct i2c_board_info const *info,
512 * be addressed using the same bus algorithms - i.e. bit-banging or the PCF8584 516 * be addressed using the same bus algorithms - i.e. bit-banging or the PCF8584
513 * to name two of the most common. 517 * to name two of the most common.
514 * 518 *
515 * The return codes from the @master_xfer field should indicate the type of 519 * The return codes from the @master_xfer{_atomic} fields should indicate the
516 * error code that occurred during the transfer, as documented in the kernel 520 * type of error code that occurred during the transfer, as documented in the
517 * Documentation file Documentation/i2c/fault-codes. 521 * Kernel Documentation file Documentation/i2c/fault-codes.
518 */ 522 */
519struct i2c_algorithm { 523struct i2c_algorithm {
520 /* If an adapter algorithm can't do I2C-level access, set master_xfer 524 /*
521 to NULL. If an adapter algorithm can do SMBus access, set 525 * If an adapter algorithm can't do I2C-level access, set master_xfer
522 smbus_xfer. If set to NULL, the SMBus protocol is simulated 526 * to NULL. If an adapter algorithm can do SMBus access, set
523 using common I2C messages */ 527 * smbus_xfer. If set to NULL, the SMBus protocol is simulated
524 /* master_xfer should return the number of messages successfully 528 * using common I2C messages.
525 processed, or a negative value on error */ 529 *
530 * master_xfer should return the number of messages successfully
531 * processed, or a negative value on error
532 */
526 int (*master_xfer)(struct i2c_adapter *adap, struct i2c_msg *msgs, 533 int (*master_xfer)(struct i2c_adapter *adap, struct i2c_msg *msgs,
527 int num); 534 int num);
528 int (*smbus_xfer) (struct i2c_adapter *adap, u16 addr, 535 int (*master_xfer_atomic)(struct i2c_adapter *adap,
529 unsigned short flags, char read_write, 536 struct i2c_msg *msgs, int num);
530 u8 command, int size, union i2c_smbus_data *data); 537 int (*smbus_xfer)(struct i2c_adapter *adap, u16 addr,
538 unsigned short flags, char read_write,
539 u8 command, int size, union i2c_smbus_data *data);
540 int (*smbus_xfer_atomic)(struct i2c_adapter *adap, u16 addr,
541 unsigned short flags, char read_write,
542 u8 command, int size, union i2c_smbus_data *data);
531 543
532 /* To determine what the adapter supports */ 544 /* To determine what the adapter supports */
533 u32 (*functionality) (struct i2c_adapter *); 545 u32 (*functionality)(struct i2c_adapter *adap);
534 546
535#if IS_ENABLED(CONFIG_I2C_SLAVE) 547#if IS_ENABLED(CONFIG_I2C_SLAVE)
536 int (*reg_slave)(struct i2c_client *client); 548 int (*reg_slave)(struct i2c_client *client);
@@ -682,7 +694,8 @@ struct i2c_adapter {
682 int retries; 694 int retries;
683 struct device dev; /* the adapter device */ 695 struct device dev; /* the adapter device */
684 unsigned long locked_flags; /* owned by the I2C core */ 696 unsigned long locked_flags; /* owned by the I2C core */
685#define I2C_ALF_IS_SUSPENDED 0 697#define I2C_ALF_IS_SUSPENDED 0
698#define I2C_ALF_SUSPEND_REPORTED 1
686 699
687 int nr; 700 int nr;
688 char name[48]; 701 char name[48];
diff --git a/include/linux/platform_data/pca954x.h b/include/linux/platform_data/pca954x.h
deleted file mode 100644
index 1712677d5904..000000000000
--- a/include/linux/platform_data/pca954x.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 *
3 * pca954x.h - I2C multiplexer/switch support
4 *
5 * Copyright (c) 2008-2009 Rodolfo Giometti <giometti@linux.it>
6 * Copyright (c) 2008-2009 Eurotech S.p.A. <info@eurotech.it>
7 * Michael Lawnick <michael.lawnick.ext@nsn.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24
25#ifndef _LINUX_I2C_PCA954X_H
26#define _LINUX_I2C_PCA954X_H
27
28/* Platform data for the PCA954x I2C multiplexers */
29
30/* Per channel initialisation data:
31 * @adap_id: bus number for the adapter. 0 = don't care
32 * @deselect_on_exit: set this entry to 1, if your H/W needs deselection
33 * of this channel after transaction.
34 *
35 */
36struct pca954x_platform_mode {
37 int adap_id;
38 unsigned int deselect_on_exit:1;
39 unsigned int class;
40};
41
42/* Per mux/switch data, used with i2c_register_board_info */
43struct pca954x_platform_data {
44 struct pca954x_platform_mode *modes;
45 int num_modes;
46};
47
48#endif /* _LINUX_I2C_PCA954X_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-25 19:48:16 -0400