7 files changed, 49 insertions, 12 deletions

diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index 314f59c12162..d0c743853318 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -25,9 +25,9 @@
                 cache-sets = <512>;
                 cache-line-size = <32>;
                 /* At full speed latency must be >=2 */
-                arm,tag-latency = <2>;
-                arm,data-latency = <2 2>;
-                arm,dirty-latency = <2>;
+                arm,tag-latency = <8>;
+                arm,data-latency = <8 8>;
+                arm,dirty-latency = <8>;
         };
 
         mtu0: mtu@101e2000 {
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index 01f40197ea13..3279bf1a17a1 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -110,7 +110,11 @@
                         interrupt-parent = <&vic>;
                         interrupts = <31>; /* Cascaded to vic */
                         clear-mask = <0xffffffff>;
-                        valid-mask = <0xffc203f8>;
+                        /*
+                         * Valid interrupt lines mask according to
+                         * table 4-36 page 4-50 of ARM DUI 0225D
+                         */
+                        valid-mask = <0x0760031b>;
                 };
 
                 dma@10130000 {
@@ -266,8 +270,8 @@
                         };
                         mmc@5000 {
                                 compatible = "arm,pl180", "arm,primecell";
-                                reg = < 0x5000 0x1000>;
-                                interrupts-extended = <&vic 22 &sic 2>;
+                                reg = <0x5000 0x1000>;
+                                interrupts-extended = <&vic 22 &sic 1>;
                                 clocks = <&xtal24mhz>, <&pclk>;
                                 clock-names = "mclk", "apb_pclk";
                         };
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
index b83137f66034..33a8eb28374e 100644
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -5,6 +5,16 @@
         compatible = "arm,versatile-pb";
 
         amba {
+                /* The Versatile PB is using more SIC IRQ lines than the AB */
+                sic: intc@10003000 {
+                        clear-mask = <0xffffffff>;
+                        /*
+                         * Valid interrupt lines mask according to
+                         * figure 3-30 page 3-74 of ARM DUI 0224B
+                         */
+                        valid-mask = <0x7fe003ff>;
+                };
+
                 gpio2: gpio@101e6000 {
                         compatible = "arm,pl061", "arm,primecell";
                         reg = <0x101e6000 0x1000>;
@@ -67,6 +77,13 @@
                 };
 
                 fpga {
+                        mmc@5000 {
+                                /*
+                                 * Overrides the interrupt assignment from
+                                 * the Versatile AB board file.
+                                 */
+                                interrupts-extended = <&sic 22 &sic 23>;
+                        };
                         uart@9000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x9000 0x1000>;
@@ -86,7 +103,8 @@
                         mmc@b000 {
                                 compatible = "arm,pl180", "arm,primecell";
                                 reg = <0xb000 0x1000>;
-                                interrupts-extended = <&vic 23 &sic 2>;
+                                interrupt-parent = <&sic>;
+                                interrupts = <1>, <2>;
                                 clocks = <&xtal24mhz>, <&pclk>;
                                 clock-names = "mclk", "apb_pclk";
                         };
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
index b1c59a766a13..e12213d16693 100644
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -187,6 +187,15 @@
                         interrupts = <43>;
                 };
 
+                sdhc@d800a000 {
+                        compatible = "wm,wm8505-sdhc";
+                        reg = <0xd800a000 0x400>;
+                        interrupts = <20>, <21>;
+                        clocks = <&clksdhc>;
+                        bus-width = <4>;
+                        sdon-inverted;
+                };
+
                 fb: fb@d8050800 {
                         compatible = "wm,wm8505-fb";
                         reg = <0xd8050800 0x200>;
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 69a22fdb52a5..cd7b198fc79e 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -366,6 +366,7 @@ CONFIG_BATTERY_MAX17042=m
 CONFIG_CHARGER_MAX14577=m
 CONFIG_CHARGER_MAX77693=m
 CONFIG_CHARGER_TPS65090=y
+CONFIG_AXP20X_POWER=m
 CONFIG_POWER_RESET_AS3722=y
 CONFIG_POWER_RESET_GPIO=y
 CONFIG_POWER_RESET_GPIO_RESTART=y
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 3c36e16fcacf..b503a89441bf 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -84,6 +84,7 @@ CONFIG_SPI_SUN4I=y
 CONFIG_SPI_SUN6I=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_POWER_SUPPLY=y
+CONFIG_AXP20X_POWER=y
 CONFIG_THERMAL=y
 CONFIG_CPU_THERMAL=y
 CONFIG_WATCHDOG=y
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 17a6f752a436..7b76ce01c21d 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -149,8 +149,8 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
                 freq = 104;
                 break;
         default:
-                freq = 54;
-                break;
+                pr_err("onenand rate not detected, bad GPMC async timings?\n");
+                freq = 0;
         }
 
         return freq;
@@ -271,6 +271,11 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
         struct gpmc_timings t;
         int ret;
 
+        /*
+         * Note that we need to keep sync_write set for the call to
+         * omap2_onenand_set_async_mode() to work to detect the onenand
+         * supported clock rate for the sync timings.
+         */
         if (gpmc_onenand_data->of_node) {
                 gpmc_read_settings_dt(gpmc_onenand_data->of_node,
                                       &onenand_async);
@@ -281,12 +286,9 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
                         else
                                 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
                         onenand_async.sync_read = false;
-                        onenand_async.sync_write = false;
                 }
         }
 
-        omap2_onenand_set_async_mode(onenand_base);
-
         omap2_onenand_calc_async_timings(&t);
 
         ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
@@ -310,6 +312,8 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
         if (!freq) {
                 /* Very first call freq is not known */
                 freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
+                if (!freq)
+                        return -ENODEV;
                 set_onenand_cfg(onenand_base);
         }