diff options
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 7 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a77990.dtsi | 7 |
2 files changed, 6 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 61a0afb74e63..1ea684af99c4 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | /* | 2 | /* |
| 3 | * Device Tree Source for the RZ/G2E (R8A774C0) SoC | 3 | * Device Tree Source for the RZ/G2E (R8A774C0) SoC |
| 4 | * | 4 | * |
| 5 | * Copyright (C) 2018 Renesas Electronics Corp. | 5 | * Copyright (C) 2018-2019 Renesas Electronics Corp. |
| 6 | */ | 6 | */ |
| 7 | 7 | ||
| 8 | #include <dt-bindings/clock/r8a774c0-cpg-mssr.h> | 8 | #include <dt-bindings/clock/r8a774c0-cpg-mssr.h> |
| @@ -1150,9 +1150,8 @@ | |||
| 1150 | <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, | 1150 | <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, |
| 1151 | <&scif_clk>; | 1151 | <&scif_clk>; |
| 1152 | clock-names = "fck", "brg_int", "scif_clk"; | 1152 | clock-names = "fck", "brg_int", "scif_clk"; |
| 1153 | dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, | 1153 | dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; |
| 1154 | <&dmac2 0x5b>, <&dmac2 0x5a>; | 1154 | dma-names = "tx", "rx"; |
| 1155 | dma-names = "tx", "rx", "tx", "rx"; | ||
| 1156 | power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; | 1155 | power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; |
| 1157 | resets = <&cpg 202>; | 1156 | resets = <&cpg 202>; |
| 1158 | status = "disabled"; | 1157 | status = "disabled"; |
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index a69faa60ea4d..d2ad665fe2d9 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | /* | 2 | /* |
| 3 | * Device Tree Source for the R-Car E3 (R8A77990) SoC | 3 | * Device Tree Source for the R-Car E3 (R8A77990) SoC |
| 4 | * | 4 | * |
| 5 | * Copyright (C) 2018 Renesas Electronics Corp. | 5 | * Copyright (C) 2018-2019 Renesas Electronics Corp. |
| 6 | */ | 6 | */ |
| 7 | 7 | ||
| 8 | #include <dt-bindings/clock/r8a77990-cpg-mssr.h> | 8 | #include <dt-bindings/clock/r8a77990-cpg-mssr.h> |
| @@ -1067,9 +1067,8 @@ | |||
| 1067 | <&cpg CPG_CORE R8A77990_CLK_S3D1C>, | 1067 | <&cpg CPG_CORE R8A77990_CLK_S3D1C>, |
| 1068 | <&scif_clk>; | 1068 | <&scif_clk>; |
| 1069 | clock-names = "fck", "brg_int", "scif_clk"; | 1069 | clock-names = "fck", "brg_int", "scif_clk"; |
| 1070 | dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, | 1070 | dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; |
| 1071 | <&dmac2 0x5b>, <&dmac2 0x5a>; | 1071 | dma-names = "tx", "rx"; |
| 1072 | dma-names = "tx", "rx", "tx", "rx"; | ||
| 1073 | power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; | 1072 | power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| 1074 | resets = <&cpg 202>; | 1073 | resets = <&cpg 202>; |
| 1075 | status = "disabled"; | 1074 | status = "disabled"; |
