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-rw-r--r--drivers/tty/serial/imx.c346
1 files changed, 179 insertions, 167 deletions
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 7356a848751e..23d591897e82 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -381,7 +381,7 @@ static void imx_port_ucrs_restore(struct imx_port *sport,
381} 381}
382#endif 382#endif
383 383
384static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2) 384static void imx_port_rts_active(struct imx_port *sport, u32 *ucr2)
385{ 385{
386 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 386 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
387 387
@@ -389,7 +389,7 @@ static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2)
389 mctrl_gpio_set(sport->gpios, sport->port.mctrl); 389 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
390} 390}
391 391
392static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2) 392static void imx_port_rts_inactive(struct imx_port *sport, u32 *ucr2)
393{ 393{
394 *ucr2 &= ~UCR2_CTSC; 394 *ucr2 &= ~UCR2_CTSC;
395 *ucr2 |= UCR2_CTS; 395 *ucr2 |= UCR2_CTS;
@@ -398,7 +398,7 @@ static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2)
398 mctrl_gpio_set(sport->gpios, sport->port.mctrl); 398 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
399} 399}
400 400
401static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2) 401static void imx_port_rts_auto(struct imx_port *sport, u32 *ucr2)
402{ 402{
403 *ucr2 |= UCR2_CTSC; 403 *ucr2 |= UCR2_CTSC;
404} 404}
@@ -407,7 +407,7 @@ static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2)
407static void imx_stop_tx(struct uart_port *port) 407static void imx_stop_tx(struct uart_port *port)
408{ 408{
409 struct imx_port *sport = (struct imx_port *)port; 409 struct imx_port *sport = (struct imx_port *)port;
410 unsigned long temp; 410 u32 ucr1;
411 411
412 /* 412 /*
413 * We are maybe in the SMP context, so if the DMA TX thread is running 413 * We are maybe in the SMP context, so if the DMA TX thread is running
@@ -416,23 +416,23 @@ static void imx_stop_tx(struct uart_port *port)
416 if (sport->dma_is_txing) 416 if (sport->dma_is_txing)
417 return; 417 return;
418 418
419 temp = imx_uart_readl(sport, UCR1); 419 ucr1 = imx_uart_readl(sport, UCR1);
420 imx_uart_writel(sport, temp & ~UCR1_TXMPTYEN, UCR1); 420 imx_uart_writel(sport, ucr1 & ~UCR1_TXMPTYEN, UCR1);
421 421
422 /* in rs485 mode disable transmitter if shifter is empty */ 422 /* in rs485 mode disable transmitter if shifter is empty */
423 if (port->rs485.flags & SER_RS485_ENABLED && 423 if (port->rs485.flags & SER_RS485_ENABLED &&
424 imx_uart_readl(sport, USR2) & USR2_TXDC) { 424 imx_uart_readl(sport, USR2) & USR2_TXDC) {
425 temp = imx_uart_readl(sport, UCR2); 425 u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4;
426 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 426 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
427 imx_port_rts_active(sport, &temp); 427 imx_port_rts_active(sport, &ucr2);
428 else 428 else
429 imx_port_rts_inactive(sport, &temp); 429 imx_port_rts_inactive(sport, &ucr2);
430 temp |= UCR2_RXEN; 430 ucr2 |= UCR2_RXEN;
431 imx_uart_writel(sport, temp, UCR2); 431 imx_uart_writel(sport, ucr2, UCR2);
432 432
433 temp = imx_uart_readl(sport, UCR4); 433 ucr4 = imx_uart_readl(sport, UCR4);
434 temp &= ~UCR4_TCEN; 434 ucr4 &= ~UCR4_TCEN;
435 imx_uart_writel(sport, temp, UCR4); 435 imx_uart_writel(sport, ucr4, UCR4);
436 } 436 }
437} 437}
438 438
@@ -440,7 +440,7 @@ static void imx_stop_tx(struct uart_port *port)
440static void imx_stop_rx(struct uart_port *port) 440static void imx_stop_rx(struct uart_port *port)
441{ 441{
442 struct imx_port *sport = (struct imx_port *)port; 442 struct imx_port *sport = (struct imx_port *)port;
443 unsigned long temp; 443 u32 ucr1, ucr2;
444 444
445 if (sport->dma_is_rxing) { 445 if (sport->dma_is_rxing) {
446 if (sport->port.suspended) { 446 if (sport->port.suspended) {
@@ -451,12 +451,12 @@ static void imx_stop_rx(struct uart_port *port)
451 } 451 }
452 } 452 }
453 453
454 temp = imx_uart_readl(sport, UCR2); 454 ucr2 = imx_uart_readl(sport, UCR2);
455 imx_uart_writel(sport, temp & ~UCR2_RXEN, UCR2); 455 imx_uart_writel(sport, ucr2 & ~UCR2_RXEN, UCR2);
456 456
457 /* disable the `Receiver Ready Interrrupt` */ 457 /* disable the `Receiver Ready Interrrupt` */
458 temp = imx_uart_readl(sport, UCR1); 458 ucr1 = imx_uart_readl(sport, UCR1);
459 imx_uart_writel(sport, temp & ~UCR1_RRDYEN, UCR1); 459 imx_uart_writel(sport, ucr1 & ~UCR1_RRDYEN, UCR1);
460} 460}
461 461
462/* called with port.lock taken and irqs off */ 462/* called with port.lock taken and irqs off */
@@ -475,7 +475,6 @@ static void imx_dma_tx(struct imx_port *sport);
475static inline void imx_transmit_buffer(struct imx_port *sport) 475static inline void imx_transmit_buffer(struct imx_port *sport)
476{ 476{
477 struct circ_buf *xmit = &sport->port.state->xmit; 477 struct circ_buf *xmit = &sport->port.state->xmit;
478 unsigned long temp;
479 478
480 if (sport->port.x_char) { 479 if (sport->port.x_char) {
481 /* Send next char */ 480 /* Send next char */
@@ -491,17 +490,18 @@ static inline void imx_transmit_buffer(struct imx_port *sport)
491 } 490 }
492 491
493 if (sport->dma_is_enabled) { 492 if (sport->dma_is_enabled) {
493 u32 ucr1;
494 /* 494 /*
495 * We've just sent a X-char Ensure the TX DMA is enabled 495 * We've just sent a X-char Ensure the TX DMA is enabled
496 * and the TX IRQ is disabled. 496 * and the TX IRQ is disabled.
497 **/ 497 **/
498 temp = imx_uart_readl(sport, UCR1); 498 ucr1 = imx_uart_readl(sport, UCR1);
499 temp &= ~UCR1_TXMPTYEN; 499 ucr1 &= ~UCR1_TXMPTYEN;
500 if (sport->dma_is_txing) { 500 if (sport->dma_is_txing) {
501 temp |= UCR1_TXDMAEN; 501 ucr1 |= UCR1_TXDMAEN;
502 imx_uart_writel(sport, temp, UCR1); 502 imx_uart_writel(sport, ucr1, UCR1);
503 } else { 503 } else {
504 imx_uart_writel(sport, temp, UCR1); 504 imx_uart_writel(sport, ucr1, UCR1);
505 imx_dma_tx(sport); 505 imx_dma_tx(sport);
506 } 506 }
507 507
@@ -530,15 +530,15 @@ static void dma_tx_callback(void *data)
530 struct scatterlist *sgl = &sport->tx_sgl[0]; 530 struct scatterlist *sgl = &sport->tx_sgl[0];
531 struct circ_buf *xmit = &sport->port.state->xmit; 531 struct circ_buf *xmit = &sport->port.state->xmit;
532 unsigned long flags; 532 unsigned long flags;
533 unsigned long temp; 533 u32 ucr1;
534 534
535 spin_lock_irqsave(&sport->port.lock, flags); 535 spin_lock_irqsave(&sport->port.lock, flags);
536 536
537 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 537 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
538 538
539 temp = imx_uart_readl(sport, UCR1); 539 ucr1 = imx_uart_readl(sport, UCR1);
540 temp &= ~UCR1_TXDMAEN; 540 ucr1 &= ~UCR1_TXDMAEN;
541 imx_uart_writel(sport, temp, UCR1); 541 imx_uart_writel(sport, ucr1, UCR1);
542 542
543 /* update the stat */ 543 /* update the stat */
544 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 544 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
@@ -565,7 +565,7 @@ static void imx_dma_tx(struct imx_port *sport)
565 struct dma_async_tx_descriptor *desc; 565 struct dma_async_tx_descriptor *desc;
566 struct dma_chan *chan = sport->dma_chan_tx; 566 struct dma_chan *chan = sport->dma_chan_tx;
567 struct device *dev = sport->port.dev; 567 struct device *dev = sport->port.dev;
568 unsigned long temp; 568 u32 ucr1;
569 int ret; 569 int ret;
570 570
571 if (sport->dma_is_txing) 571 if (sport->dma_is_txing)
@@ -603,9 +603,9 @@ static void imx_dma_tx(struct imx_port *sport)
603 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 603 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
604 uart_circ_chars_pending(xmit)); 604 uart_circ_chars_pending(xmit));
605 605
606 temp = imx_uart_readl(sport, UCR1); 606 ucr1 = imx_uart_readl(sport, UCR1);
607 temp |= UCR1_TXDMAEN; 607 ucr1 |= UCR1_TXDMAEN;
608 imx_uart_writel(sport, temp, UCR1); 608 imx_uart_writel(sport, ucr1, UCR1);
609 609
610 /* fire it */ 610 /* fire it */
611 sport->dma_is_txing = 1; 611 sport->dma_is_txing = 1;
@@ -618,37 +618,39 @@ static void imx_dma_tx(struct imx_port *sport)
618static void imx_start_tx(struct uart_port *port) 618static void imx_start_tx(struct uart_port *port)
619{ 619{
620 struct imx_port *sport = (struct imx_port *)port; 620 struct imx_port *sport = (struct imx_port *)port;
621 unsigned long temp; 621 u32 ucr1;
622 622
623 if (port->rs485.flags & SER_RS485_ENABLED) { 623 if (port->rs485.flags & SER_RS485_ENABLED) {
624 temp = imx_uart_readl(sport, UCR2); 624 u32 ucr2, ucr4;
625
626 ucr2 = imx_uart_readl(sport, UCR2);
625 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 627 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
626 imx_port_rts_active(sport, &temp); 628 imx_port_rts_active(sport, &ucr2);
627 else 629 else
628 imx_port_rts_inactive(sport, &temp); 630 imx_port_rts_inactive(sport, &ucr2);
629 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 631 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
630 temp &= ~UCR2_RXEN; 632 ucr2 &= ~UCR2_RXEN;
631 imx_uart_writel(sport, temp, UCR2); 633 imx_uart_writel(sport, ucr2, UCR2);
632 634
633 /* enable transmitter and shifter empty irq */ 635 /* enable transmitter and shifter empty irq */
634 temp = imx_uart_readl(sport, UCR4); 636 ucr4 = imx_uart_readl(sport, UCR4);
635 temp |= UCR4_TCEN; 637 ucr4 |= UCR4_TCEN;
636 imx_uart_writel(sport, temp, UCR4); 638 imx_uart_writel(sport, ucr4, UCR4);
637 } 639 }
638 640
639 if (!sport->dma_is_enabled) { 641 if (!sport->dma_is_enabled) {
640 temp = imx_uart_readl(sport, UCR1); 642 ucr1 = imx_uart_readl(sport, UCR1);
641 imx_uart_writel(sport, temp | UCR1_TXMPTYEN, UCR1); 643 imx_uart_writel(sport, ucr1 | UCR1_TXMPTYEN, UCR1);
642 } 644 }
643 645
644 if (sport->dma_is_enabled) { 646 if (sport->dma_is_enabled) {
645 if (sport->port.x_char) { 647 if (sport->port.x_char) {
646 /* We have X-char to send, so enable TX IRQ and 648 /* We have X-char to send, so enable TX IRQ and
647 * disable TX DMA to let TX interrupt to send X-char */ 649 * disable TX DMA to let TX interrupt to send X-char */
648 temp = imx_uart_readl(sport, UCR1); 650 ucr1 = imx_uart_readl(sport, UCR1);
649 temp &= ~UCR1_TXDMAEN; 651 ucr1 &= ~UCR1_TXDMAEN;
650 temp |= UCR1_TXMPTYEN; 652 ucr1 |= UCR1_TXMPTYEN;
651 imx_uart_writel(sport, temp, UCR1); 653 imx_uart_writel(sport, ucr1, UCR1);
652 return; 654 return;
653 } 655 }
654 656
@@ -662,14 +664,14 @@ static void imx_start_tx(struct uart_port *port)
662static irqreturn_t imx_rtsint(int irq, void *dev_id) 664static irqreturn_t imx_rtsint(int irq, void *dev_id)
663{ 665{
664 struct imx_port *sport = dev_id; 666 struct imx_port *sport = dev_id;
665 unsigned int val; 667 u32 usr1;
666 unsigned long flags; 668 unsigned long flags;
667 669
668 spin_lock_irqsave(&sport->port.lock, flags); 670 spin_lock_irqsave(&sport->port.lock, flags);
669 671
670 imx_uart_writel(sport, USR1_RTSD, USR1); 672 imx_uart_writel(sport, USR1_RTSD, USR1);
671 val = imx_uart_readl(sport, USR1) & USR1_RTSS; 673 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
672 uart_handle_cts_change(&sport->port, !!val); 674 uart_handle_cts_change(&sport->port, !!usr1);
673 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 675 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
674 676
675 spin_unlock_irqrestore(&sport->port.lock, flags); 677 spin_unlock_irqrestore(&sport->port.lock, flags);
@@ -692,18 +694,20 @@ static irqreturn_t imx_rxint(int irq, void *dev_id)
692 struct imx_port *sport = dev_id; 694 struct imx_port *sport = dev_id;
693 unsigned int rx, flg, ignored = 0; 695 unsigned int rx, flg, ignored = 0;
694 struct tty_port *port = &sport->port.state->port; 696 struct tty_port *port = &sport->port.state->port;
695 unsigned long flags, temp; 697 unsigned long flags;
696 698
697 spin_lock_irqsave(&sport->port.lock, flags); 699 spin_lock_irqsave(&sport->port.lock, flags);
698 700
699 while (imx_uart_readl(sport, USR2) & USR2_RDR) { 701 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
702 u32 usr2;
703
700 flg = TTY_NORMAL; 704 flg = TTY_NORMAL;
701 sport->port.icount.rx++; 705 sport->port.icount.rx++;
702 706
703 rx = imx_uart_readl(sport, URXD0); 707 rx = imx_uart_readl(sport, URXD0);
704 708
705 temp = imx_uart_readl(sport, USR2); 709 usr2 = imx_uart_readl(sport, USR2);
706 if (temp & USR2_BRCD) { 710 if (usr2 & USR2_BRCD) {
707 imx_uart_writel(sport, USR2_BRCD, USR2); 711 imx_uart_writel(sport, USR2_BRCD, USR2);
708 if (uart_handle_break(&sport->port)) 712 if (uart_handle_break(&sport->port))
709 continue; 713 continue;
@@ -920,25 +924,27 @@ static unsigned int imx_get_mctrl(struct uart_port *port)
920static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) 924static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
921{ 925{
922 struct imx_port *sport = (struct imx_port *)port; 926 struct imx_port *sport = (struct imx_port *)port;
923 unsigned long temp; 927 u32 ucr3, uts;
924 928
925 if (!(port->rs485.flags & SER_RS485_ENABLED)) { 929 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
926 temp = imx_uart_readl(sport, UCR2); 930 u32 ucr2;
927 temp &= ~(UCR2_CTS | UCR2_CTSC); 931
932 ucr2 = imx_uart_readl(sport, UCR2);
933 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
928 if (mctrl & TIOCM_RTS) 934 if (mctrl & TIOCM_RTS)
929 temp |= UCR2_CTS | UCR2_CTSC; 935 ucr2 |= UCR2_CTS | UCR2_CTSC;
930 imx_uart_writel(sport, temp, UCR2); 936 imx_uart_writel(sport, ucr2, UCR2);
931 } 937 }
932 938
933 temp = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 939 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
934 if (!(mctrl & TIOCM_DTR)) 940 if (!(mctrl & TIOCM_DTR))
935 temp |= UCR3_DSR; 941 ucr3 |= UCR3_DSR;
936 imx_uart_writel(sport, temp, UCR3); 942 imx_uart_writel(sport, ucr3, UCR3);
937 943
938 temp = imx_uart_readl(sport, uts_reg(sport)) & ~UTS_LOOP; 944 uts = imx_uart_readl(sport, uts_reg(sport)) & ~UTS_LOOP;
939 if (mctrl & TIOCM_LOOP) 945 if (mctrl & TIOCM_LOOP)
940 temp |= UTS_LOOP; 946 uts |= UTS_LOOP;
941 imx_uart_writel(sport, temp, uts_reg(sport)); 947 imx_uart_writel(sport, uts, uts_reg(sport));
942 948
943 mctrl_gpio_set(sport->gpios, mctrl); 949 mctrl_gpio_set(sport->gpios, mctrl);
944} 950}
@@ -949,16 +955,17 @@ static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
949static void imx_break_ctl(struct uart_port *port, int break_state) 955static void imx_break_ctl(struct uart_port *port, int break_state)
950{ 956{
951 struct imx_port *sport = (struct imx_port *)port; 957 struct imx_port *sport = (struct imx_port *)port;
952 unsigned long flags, temp; 958 unsigned long flags;
959 u32 ucr1;
953 960
954 spin_lock_irqsave(&sport->port.lock, flags); 961 spin_lock_irqsave(&sport->port.lock, flags);
955 962
956 temp = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 963 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
957 964
958 if (break_state != 0) 965 if (break_state != 0)
959 temp |= UCR1_SNDBRK; 966 ucr1 |= UCR1_SNDBRK;
960 967
961 imx_uart_writel(sport, temp, UCR1); 968 imx_uart_writel(sport, ucr1, UCR1);
962 969
963 spin_unlock_irqrestore(&sport->port.lock, flags); 970 spin_unlock_irqrestore(&sport->port.lock, flags);
964} 971}
@@ -1108,12 +1115,12 @@ static int start_rx_dma(struct imx_port *sport)
1108static void clear_rx_errors(struct imx_port *sport) 1115static void clear_rx_errors(struct imx_port *sport)
1109{ 1116{
1110 struct tty_port *port = &sport->port.state->port; 1117 struct tty_port *port = &sport->port.state->port;
1111 unsigned int status_usr1, status_usr2; 1118 u32 usr1, usr2;
1112 1119
1113 status_usr1 = imx_uart_readl(sport, USR1); 1120 usr1 = imx_uart_readl(sport, USR1);
1114 status_usr2 = imx_uart_readl(sport, USR2); 1121 usr2 = imx_uart_readl(sport, USR2);
1115 1122
1116 if (status_usr2 & USR2_BRCD) { 1123 if (usr2 & USR2_BRCD) {
1117 sport->port.icount.brk++; 1124 sport->port.icount.brk++;
1118 imx_uart_writel(sport, USR2_BRCD, USR2); 1125 imx_uart_writel(sport, USR2_BRCD, USR2);
1119 uart_handle_break(&sport->port); 1126 uart_handle_break(&sport->port);
@@ -1122,16 +1129,16 @@ static void clear_rx_errors(struct imx_port *sport)
1122 tty_flip_buffer_push(port); 1129 tty_flip_buffer_push(port);
1123 } else { 1130 } else {
1124 dev_err(sport->port.dev, "DMA transaction error.\n"); 1131 dev_err(sport->port.dev, "DMA transaction error.\n");
1125 if (status_usr1 & USR1_FRAMERR) { 1132 if (usr1 & USR1_FRAMERR) {
1126 sport->port.icount.frame++; 1133 sport->port.icount.frame++;
1127 imx_uart_writel(sport, USR1_FRAMERR, USR1); 1134 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1128 } else if (status_usr1 & USR1_PARITYERR) { 1135 } else if (usr1 & USR1_PARITYERR) {
1129 sport->port.icount.parity++; 1136 sport->port.icount.parity++;
1130 imx_uart_writel(sport, USR1_PARITYERR, USR1); 1137 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1131 } 1138 }
1132 } 1139 }
1133 1140
1134 if (status_usr2 & USR2_ORE) { 1141 if (usr2 & USR2_ORE) {
1135 sport->port.icount.overrun++; 1142 sport->port.icount.overrun++;
1136 imx_uart_writel(sport, USR2_ORE, USR2); 1143 imx_uart_writel(sport, USR2_ORE, USR2);
1137 } 1144 }
@@ -1230,12 +1237,12 @@ err:
1230 1237
1231static void imx_enable_dma(struct imx_port *sport) 1238static void imx_enable_dma(struct imx_port *sport)
1232{ 1239{
1233 unsigned long temp; 1240 u32 ucr1;
1234 1241
1235 /* set UCR1 */ 1242 /* set UCR1 */
1236 temp = imx_uart_readl(sport, UCR1); 1243 ucr1 = imx_uart_readl(sport, UCR1);
1237 temp |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 1244 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1238 imx_uart_writel(sport, temp, UCR1); 1245 imx_uart_writel(sport, ucr1, UCR1);
1239 1246
1240 imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 1247 imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1241 1248
@@ -1244,17 +1251,17 @@ static void imx_enable_dma(struct imx_port *sport)
1244 1251
1245static void imx_disable_dma(struct imx_port *sport) 1252static void imx_disable_dma(struct imx_port *sport)
1246{ 1253{
1247 unsigned long temp; 1254 u32 ucr1, ucr2;
1248 1255
1249 /* clear UCR1 */ 1256 /* clear UCR1 */
1250 temp = imx_uart_readl(sport, UCR1); 1257 ucr1 = imx_uart_readl(sport, UCR1);
1251 temp &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 1258 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1252 imx_uart_writel(sport, temp, UCR1); 1259 imx_uart_writel(sport, ucr1, UCR1);
1253 1260
1254 /* clear UCR2 */ 1261 /* clear UCR2 */
1255 temp = imx_uart_readl(sport, UCR2); 1262 ucr2 = imx_uart_readl(sport, UCR2);
1256 temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN); 1263 ucr2 &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN);
1257 imx_uart_writel(sport, temp, UCR2); 1264 imx_uart_writel(sport, ucr2, UCR2);
1258 1265
1259 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1266 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1260 1267
@@ -1268,8 +1275,9 @@ static int imx_startup(struct uart_port *port)
1268{ 1275{
1269 struct imx_port *sport = (struct imx_port *)port; 1276 struct imx_port *sport = (struct imx_port *)port;
1270 int retval, i; 1277 int retval, i;
1271 unsigned long flags, temp; 1278 unsigned long flags;
1272 int dma_is_inited = 0; 1279 int dma_is_inited = 0;
1280 u32 ucr1, ucr2, ucr4;
1273 1281
1274 retval = clk_prepare_enable(sport->clk_per); 1282 retval = clk_prepare_enable(sport->clk_per);
1275 if (retval) 1283 if (retval)
@@ -1285,13 +1293,13 @@ static int imx_startup(struct uart_port *port)
1285 /* disable the DREN bit (Data Ready interrupt enable) before 1293 /* disable the DREN bit (Data Ready interrupt enable) before
1286 * requesting IRQs 1294 * requesting IRQs
1287 */ 1295 */
1288 temp = imx_uart_readl(sport, UCR4); 1296 ucr4 = imx_uart_readl(sport, UCR4);
1289 1297
1290 /* set the trigger level for CTS */ 1298 /* set the trigger level for CTS */
1291 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1299 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1292 temp |= CTSTL << UCR4_CTSTL_SHF; 1300 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1293 1301
1294 imx_uart_writel(sport, temp & ~UCR4_DREN, UCR4); 1302 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1295 1303
1296 /* Can we enable the DMA support? */ 1304 /* Can we enable the DMA support? */
1297 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 1305 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
@@ -1301,9 +1309,9 @@ static int imx_startup(struct uart_port *port)
1301 /* Reset fifo's and state machines */ 1309 /* Reset fifo's and state machines */
1302 i = 100; 1310 i = 100;
1303 1311
1304 temp = imx_uart_readl(sport, UCR2); 1312 ucr2 = imx_uart_readl(sport, UCR2);
1305 temp &= ~UCR2_SRST; 1313 ucr2 &= ~UCR2_SRST;
1306 imx_uart_writel(sport, temp, UCR2); 1314 imx_uart_writel(sport, ucr2, UCR2);
1307 1315
1308 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1316 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1309 udelay(1); 1317 udelay(1);
@@ -1317,42 +1325,44 @@ static int imx_startup(struct uart_port *port)
1317 if (dma_is_inited) 1325 if (dma_is_inited)
1318 imx_enable_dma(sport); 1326 imx_enable_dma(sport);
1319 1327
1320 temp = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 1328 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1321 if (!sport->dma_is_enabled) 1329 if (!sport->dma_is_enabled)
1322 temp |= UCR1_RRDYEN; 1330 ucr1 |= UCR1_RRDYEN;
1323 temp |= UCR1_UARTEN; 1331 ucr1 |= UCR1_UARTEN;
1324 if (sport->have_rtscts) 1332 if (sport->have_rtscts)
1325 temp |= UCR1_RTSDEN; 1333 ucr1 |= UCR1_RTSDEN;
1326 1334
1327 imx_uart_writel(sport, temp, UCR1); 1335 imx_uart_writel(sport, ucr1, UCR1);
1328 1336
1329 temp = imx_uart_readl(sport, UCR4) & ~UCR4_OREN; 1337 ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN;
1330 if (!sport->dma_is_enabled) 1338 if (!sport->dma_is_enabled)
1331 temp |= UCR4_OREN; 1339 ucr4 |= UCR4_OREN;
1332 imx_uart_writel(sport, temp, UCR4); 1340 imx_uart_writel(sport, ucr4, UCR4);
1333 1341
1334 temp = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 1342 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1335 temp |= (UCR2_RXEN | UCR2_TXEN); 1343 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1336 if (!sport->have_rtscts) 1344 if (!sport->have_rtscts)
1337 temp |= UCR2_IRTS; 1345 ucr2 |= UCR2_IRTS;
1338 /* 1346 /*
1339 * make sure the edge sensitive RTS-irq is disabled, 1347 * make sure the edge sensitive RTS-irq is disabled,
1340 * we're using RTSD instead. 1348 * we're using RTSD instead.
1341 */ 1349 */
1342 if (!is_imx1_uart(sport)) 1350 if (!is_imx1_uart(sport))
1343 temp &= ~UCR2_RTSEN; 1351 ucr2 &= ~UCR2_RTSEN;
1344 imx_uart_writel(sport, temp, UCR2); 1352 imx_uart_writel(sport, ucr2, UCR2);
1345 1353
1346 if (!is_imx1_uart(sport)) { 1354 if (!is_imx1_uart(sport)) {
1347 temp = imx_uart_readl(sport, UCR3); 1355 u32 ucr3;
1356
1357 ucr3 = imx_uart_readl(sport, UCR3);
1348 1358
1349 temp |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 1359 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1350 1360
1351 if (sport->dte_mode) 1361 if (sport->dte_mode)
1352 /* disable broken interrupts */ 1362 /* disable broken interrupts */
1353 temp &= ~(UCR3_RI | UCR3_DCD); 1363 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1354 1364
1355 imx_uart_writel(sport, temp, UCR3); 1365 imx_uart_writel(sport, ucr3, UCR3);
1356 } 1366 }
1357 1367
1358 /* 1368 /*
@@ -1376,8 +1386,8 @@ static int imx_startup(struct uart_port *port)
1376static void imx_shutdown(struct uart_port *port) 1386static void imx_shutdown(struct uart_port *port)
1377{ 1387{
1378 struct imx_port *sport = (struct imx_port *)port; 1388 struct imx_port *sport = (struct imx_port *)port;
1379 unsigned long temp;
1380 unsigned long flags; 1389 unsigned long flags;
1390 u32 ucr1, ucr2;
1381 1391
1382 if (sport->dma_is_enabled) { 1392 if (sport->dma_is_enabled) {
1383 sport->dma_is_rxing = 0; 1393 sport->dma_is_rxing = 0;
@@ -1396,9 +1406,9 @@ static void imx_shutdown(struct uart_port *port)
1396 mctrl_gpio_disable_ms(sport->gpios); 1406 mctrl_gpio_disable_ms(sport->gpios);
1397 1407
1398 spin_lock_irqsave(&sport->port.lock, flags); 1408 spin_lock_irqsave(&sport->port.lock, flags);
1399 temp = imx_uart_readl(sport, UCR2); 1409 ucr2 = imx_uart_readl(sport, UCR2);
1400 temp &= ~(UCR2_TXEN); 1410 ucr2 &= ~UCR2_TXEN;
1401 imx_uart_writel(sport, temp, UCR2); 1411 imx_uart_writel(sport, ucr2, UCR2);
1402 spin_unlock_irqrestore(&sport->port.lock, flags); 1412 spin_unlock_irqrestore(&sport->port.lock, flags);
1403 1413
1404 /* 1414 /*
@@ -1411,10 +1421,10 @@ static void imx_shutdown(struct uart_port *port)
1411 */ 1421 */
1412 1422
1413 spin_lock_irqsave(&sport->port.lock, flags); 1423 spin_lock_irqsave(&sport->port.lock, flags);
1414 temp = imx_uart_readl(sport, UCR1); 1424 ucr1 = imx_uart_readl(sport, UCR1);
1415 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); 1425 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1416 1426
1417 imx_uart_writel(sport, temp, UCR1); 1427 imx_uart_writel(sport, ucr1, UCR1);
1418 spin_unlock_irqrestore(&sport->port.lock, flags); 1428 spin_unlock_irqrestore(&sport->port.lock, flags);
1419 1429
1420 clk_disable_unprepare(sport->clk_per); 1430 clk_disable_unprepare(sport->clk_per);
@@ -1426,7 +1436,7 @@ static void imx_flush_buffer(struct uart_port *port)
1426{ 1436{
1427 struct imx_port *sport = (struct imx_port *)port; 1437 struct imx_port *sport = (struct imx_port *)port;
1428 struct scatterlist *sgl = &sport->tx_sgl[0]; 1438 struct scatterlist *sgl = &sport->tx_sgl[0];
1429 unsigned long temp; 1439 u32 ucr2;
1430 int i = 100, ubir, ubmr, uts; 1440 int i = 100, ubir, ubmr, uts;
1431 1441
1432 if (!sport->dma_chan_tx) 1442 if (!sport->dma_chan_tx)
@@ -1435,11 +1445,13 @@ static void imx_flush_buffer(struct uart_port *port)
1435 sport->tx_bytes = 0; 1445 sport->tx_bytes = 0;
1436 dmaengine_terminate_all(sport->dma_chan_tx); 1446 dmaengine_terminate_all(sport->dma_chan_tx);
1437 if (sport->dma_is_txing) { 1447 if (sport->dma_is_txing) {
1448 u32 ucr1;
1449
1438 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 1450 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1439 DMA_TO_DEVICE); 1451 DMA_TO_DEVICE);
1440 temp = imx_uart_readl(sport, UCR1); 1452 ucr1 = imx_uart_readl(sport, UCR1);
1441 temp &= ~UCR1_TXDMAEN; 1453 ucr1 &= ~UCR1_TXDMAEN;
1442 imx_uart_writel(sport, temp, UCR1); 1454 imx_uart_writel(sport, ucr1, UCR1);
1443 sport->dma_is_txing = 0; 1455 sport->dma_is_txing = 0;
1444 } 1456 }
1445 1457
@@ -1458,9 +1470,9 @@ static void imx_flush_buffer(struct uart_port *port)
1458 ubmr = imx_uart_readl(sport, UBMR); 1470 ubmr = imx_uart_readl(sport, UBMR);
1459 uts = imx_uart_readl(sport, IMX21_UTS); 1471 uts = imx_uart_readl(sport, IMX21_UTS);
1460 1472
1461 temp = imx_uart_readl(sport, UCR2); 1473 ucr2 = imx_uart_readl(sport, UCR2);
1462 temp &= ~UCR2_SRST; 1474 ucr2 &= ~UCR2_SRST;
1463 imx_uart_writel(sport, temp, UCR2); 1475 imx_uart_writel(sport, ucr2, UCR2);
1464 1476
1465 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1477 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1466 udelay(1); 1478 udelay(1);
@@ -1477,10 +1489,10 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
1477{ 1489{
1478 struct imx_port *sport = (struct imx_port *)port; 1490 struct imx_port *sport = (struct imx_port *)port;
1479 unsigned long flags; 1491 unsigned long flags;
1480 unsigned long ucr2, old_ucr1, old_ucr2; 1492 u32 ucr2, old_ucr1, old_ucr2, ufcr;
1481 unsigned int baud, quot; 1493 unsigned int baud, quot;
1482 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1494 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1483 unsigned long div, ufcr; 1495 unsigned long div;
1484 unsigned long num, denom; 1496 unsigned long num, denom;
1485 uint64_t tdiv64; 1497 uint64_t tdiv64;
1486 1498
@@ -1690,7 +1702,7 @@ static int imx_poll_init(struct uart_port *port)
1690{ 1702{
1691 struct imx_port *sport = (struct imx_port *)port; 1703 struct imx_port *sport = (struct imx_port *)port;
1692 unsigned long flags; 1704 unsigned long flags;
1693 unsigned long temp; 1705 u32 ucr1, ucr2;
1694 int retval; 1706 int retval;
1695 1707
1696 retval = clk_prepare_enable(sport->clk_ipg); 1708 retval = clk_prepare_enable(sport->clk_ipg);
@@ -1704,16 +1716,16 @@ static int imx_poll_init(struct uart_port *port)
1704 1716
1705 spin_lock_irqsave(&sport->port.lock, flags); 1717 spin_lock_irqsave(&sport->port.lock, flags);
1706 1718
1707 temp = imx_uart_readl(sport, UCR1); 1719 ucr1 = imx_uart_readl(sport, UCR1);
1708 if (is_imx1_uart(sport)) 1720 if (is_imx1_uart(sport))
1709 temp |= IMX1_UCR1_UARTCLKEN; 1721 ucr1 |= IMX1_UCR1_UARTCLKEN;
1710 temp |= UCR1_UARTEN | UCR1_RRDYEN; 1722 ucr1 |= UCR1_UARTEN | UCR1_RRDYEN;
1711 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN); 1723 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1712 imx_uart_writel(sport, temp, UCR1); 1724 imx_uart_writel(sport, ucr1, UCR1);
1713 1725
1714 temp = imx_uart_readl(sport, UCR2); 1726 ucr2 = imx_uart_readl(sport, UCR2);
1715 temp |= UCR2_RXEN; 1727 ucr2 |= UCR2_RXEN;
1716 imx_uart_writel(sport, temp, UCR2); 1728 imx_uart_writel(sport, ucr2, UCR2);
1717 1729
1718 spin_unlock_irqrestore(&sport->port.lock, flags); 1730 spin_unlock_irqrestore(&sport->port.lock, flags);
1719 1731
@@ -1754,7 +1766,7 @@ static int imx_rs485_config(struct uart_port *port,
1754 struct serial_rs485 *rs485conf) 1766 struct serial_rs485 *rs485conf)
1755{ 1767{
1756 struct imx_port *sport = (struct imx_port *)port; 1768 struct imx_port *sport = (struct imx_port *)port;
1757 unsigned long temp; 1769 u32 ucr2;
1758 1770
1759 /* unimplemented */ 1771 /* unimplemented */
1760 rs485conf->delay_rts_before_send = 0; 1772 rs485conf->delay_rts_before_send = 0;
@@ -1766,20 +1778,20 @@ static int imx_rs485_config(struct uart_port *port,
1766 1778
1767 if (rs485conf->flags & SER_RS485_ENABLED) { 1779 if (rs485conf->flags & SER_RS485_ENABLED) {
1768 /* disable transmitter */ 1780 /* disable transmitter */
1769 temp = imx_uart_readl(sport, UCR2); 1781 ucr2 = imx_uart_readl(sport, UCR2);
1770 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 1782 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1771 imx_port_rts_active(sport, &temp); 1783 imx_port_rts_active(sport, &ucr2);
1772 else 1784 else
1773 imx_port_rts_inactive(sport, &temp); 1785 imx_port_rts_inactive(sport, &ucr2);
1774 imx_uart_writel(sport, temp, UCR2); 1786 imx_uart_writel(sport, ucr2, UCR2);
1775 } 1787 }
1776 1788
1777 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 1789 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1778 if (!(rs485conf->flags & SER_RS485_ENABLED) || 1790 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1779 rs485conf->flags & SER_RS485_RX_DURING_TX) { 1791 rs485conf->flags & SER_RS485_RX_DURING_TX) {
1780 temp = imx_uart_readl(sport, UCR2); 1792 ucr2 = imx_uart_readl(sport, UCR2);
1781 temp |= UCR2_RXEN; 1793 ucr2 |= UCR2_RXEN;
1782 imx_uart_writel(sport, temp, UCR2); 1794 imx_uart_writel(sport, ucr2, UCR2);
1783 } 1795 }
1784 1796
1785 port->rs485 = *rs485conf; 1797 port->rs485 = *rs485conf;
@@ -2118,7 +2130,8 @@ static int serial_imx_probe(struct platform_device *pdev)
2118{ 2130{
2119 struct imx_port *sport; 2131 struct imx_port *sport;
2120 void __iomem *base; 2132 void __iomem *base;
2121 int ret = 0, reg; 2133 int ret = 0;
2134 u32 ucr1;
2122 struct resource *res; 2135 struct resource *res;
2123 int txirq, rxirq, rtsirq; 2136 int txirq, rxirq, rtsirq;
2124 2137
@@ -2202,10 +2215,10 @@ static int serial_imx_probe(struct platform_device *pdev)
2202 imx_rs485_config(&sport->port, &sport->port.rs485); 2215 imx_rs485_config(&sport->port, &sport->port.rs485);
2203 2216
2204 /* Disable interrupts before requesting them */ 2217 /* Disable interrupts before requesting them */
2205 reg = imx_uart_readl(sport, UCR1); 2218 ucr1 = imx_uart_readl(sport, UCR1);
2206 reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 2219 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2207 UCR1_TXMPTYEN | UCR1_RTSDEN); 2220 UCR1_TXMPTYEN | UCR1_RTSDEN);
2208 imx_uart_writel(sport, reg, UCR1); 2221 imx_uart_writel(sport, ucr1, UCR1);
2209 2222
2210 if (!is_imx1_uart(sport) && sport->dte_mode) { 2223 if (!is_imx1_uart(sport) && sport->dte_mode) {
2211 /* 2224 /*
@@ -2214,9 +2227,9 @@ static int serial_imx_probe(struct platform_device *pdev)
2214 * and DCD (when they are outputs) or enables the respective 2227 * and DCD (when they are outputs) or enables the respective
2215 * irqs. So set this bit early, i.e. before requesting irqs. 2228 * irqs. So set this bit early, i.e. before requesting irqs.
2216 */ 2229 */
2217 reg = imx_uart_readl(sport, UFCR); 2230 u32 ufcr = imx_uart_readl(sport, UFCR);
2218 if (!(reg & UFCR_DCEDTE)) 2231 if (!(ufcr & UFCR_DCEDTE))
2219 imx_uart_writel(sport, reg | UFCR_DCEDTE, UFCR); 2232 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2220 2233
2221 /* 2234 /*
2222 * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2235 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
@@ -2228,11 +2241,10 @@ static int serial_imx_probe(struct platform_device *pdev)
2228 UCR3); 2241 UCR3);
2229 2242
2230 } else { 2243 } else {
2231 unsigned long ucr3 = UCR3_DSR; 2244 u32 ucr3 = UCR3_DSR;
2232 2245 u32 ufcr = imx_uart_readl(sport, UFCR);
2233 reg = imx_uart_readl(sport, UFCR); 2246 if (ufcr & UFCR_DCEDTE)
2234 if (reg & UFCR_DCEDTE) 2247 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2235 imx_uart_writel(sport, reg & ~UFCR_DCEDTE, UFCR);
2236 2248
2237 if (!is_imx1_uart(sport)) 2249 if (!is_imx1_uart(sport))
2238 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 2250 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
@@ -2320,24 +2332,24 @@ static void serial_imx_save_context(struct imx_port *sport)
2320 2332
2321static void serial_imx_enable_wakeup(struct imx_port *sport, bool on) 2333static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2322{ 2334{
2323 unsigned int val; 2335 u32 ucr3;
2324 2336
2325 val = imx_uart_readl(sport, UCR3); 2337 ucr3 = imx_uart_readl(sport, UCR3);
2326 if (on) { 2338 if (on) {
2327 imx_uart_writel(sport, USR1_AWAKE, USR1); 2339 imx_uart_writel(sport, USR1_AWAKE, USR1);
2328 val |= UCR3_AWAKEN; 2340 ucr3 |= UCR3_AWAKEN;
2341 } else {
2342 ucr3 &= ~UCR3_AWAKEN;
2329 } 2343 }
2330 else 2344 imx_uart_writel(sport, ucr3, UCR3);
2331 val &= ~UCR3_AWAKEN;
2332 imx_uart_writel(sport, val, UCR3);
2333 2345
2334 if (sport->have_rtscts) { 2346 if (sport->have_rtscts) {
2335 val = imx_uart_readl(sport, UCR1); 2347 u32 ucr1 = imx_uart_readl(sport, UCR1);
2336 if (on) 2348 if (on)
2337 val |= UCR1_RTSDEN; 2349 ucr1 |= UCR1_RTSDEN;
2338 else 2350 else
2339 val &= ~UCR1_RTSDEN; 2351 ucr1 &= ~UCR1_RTSDEN;
2340 imx_uart_writel(sport, val, UCR1); 2352 imx_uart_writel(sport, ucr1, UCR1);
2341 } 2353 }
2342} 2354}
2343 2355