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1 | Amlogic Meson Display Controller | ||
2 | ================================ | ||
3 | |||
4 | The Amlogic Meson Display controller is composed of several components | ||
5 | that are going to be documented below: | ||
6 | |||
7 | DMC|---------------VPU (Video Processing Unit)----------------|------HHI------| | ||
8 | | vd1 _______ _____________ _________________ | | | ||
9 | D |-------| |----| | | | | HDMI PLL | | ||
10 | D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK | | ||
11 | R |-------| |----| Processing | | | | | | ||
12 | | osd2 | | | |---| Enci ----------|----|-----VDAC------| | ||
13 | R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----| | ||
14 | A | osd1 | | | Blenders | | Encl ----------|----|---------------| | ||
15 | M |-------|______|----|____________| |________________| | | | ||
16 | ___|__________________________________________________________|_______________| | ||
17 | |||
18 | |||
19 | VIU: Video Input Unit | ||
20 | --------------------- | ||
21 | |||
22 | The Video Input Unit is in charge of the pixel scanout from the DDR memory. | ||
23 | It fetches the frames addresses, stride and parameters from the "Canvas" memory. | ||
24 | This part is also in charge of the CSC (Colorspace Conversion). | ||
25 | It can handle 2 OSD Planes and 2 Video Planes. | ||
26 | |||
27 | VPP: Video Post Processing | ||
28 | -------------------------- | ||
29 | |||
30 | The Video Post Processing is in charge of the scaling and blending of the | ||
31 | various planes into a single pixel stream. | ||
32 | There is a special "pre-blending" used by the video planes with a dedicated | ||
33 | scaler and a "post-blending" to merge with the OSD Planes. | ||
34 | The OSD planes also have a dedicated scaler for one of the OSD. | ||
35 | |||
36 | VENC: Video Encoders | ||
37 | -------------------- | ||
38 | |||
39 | The VENC is composed of the multiple pixel encoders : | ||
40 | - ENCI : Interlace Video encoder for CVBS and Interlace HDMI | ||
41 | - ENCP : Progressive Video Encoder for HDMI | ||
42 | - ENCL : LCD LVDS Encoder | ||
43 | The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock | ||
44 | tree and provides the scanout clock to the VPP and VIU. | ||
45 | The ENCI is connected to a single VDAC for Composite Output. | ||
46 | The ENCI and ENCP are connected to an on-chip HDMI Transceiver. | ||
47 | |||
48 | Device Tree Bindings: | ||
49 | --------------------- | ||
50 | |||
51 | VPU: Video Processing Unit | ||
52 | -------------------------- | ||
53 | |||
54 | Required properties: | ||
55 | - compatible: value should be different for each SoC family as : | ||
56 | - GXBB (S905) : "amlogic,meson-gxbb-vpu" | ||
57 | - GXL (S905X, S905D) : "amlogic,meson-gxl-vpu" | ||
58 | - GXM (S912) : "amlogic,meson-gxm-vpu" | ||
59 | followed by the common "amlogic,meson-gx-vpu" | ||
60 | - reg: base address and size of he following memory-mapped regions : | ||
61 | - vpu | ||
62 | - hhi | ||
63 | - dmc | ||
64 | - reg-names: should contain the names of the previous memory regions | ||
65 | - interrupts: should contain the VENC Vsync interrupt number | ||
66 | |||
67 | Required nodes: | ||
68 | |||
69 | The connections to the VPU output video ports are modeled using the OF graph | ||
70 | bindings specified in Documentation/devicetree/bindings/graph.txt. | ||
71 | |||
72 | The following table lists for each supported model the port number | ||
73 | corresponding to each VPU output. | ||
74 | |||
75 | Port 0 Port 1 | ||
76 | ----------------------------------------- | ||
77 | S905 (GXBB) CVBS VDAC HDMI-TX | ||
78 | S905X (GXL) CVBS VDAC HDMI-TX | ||
79 | S905D (GXL) CVBS VDAC HDMI-TX | ||
80 | S912 (GXM) CVBS VDAC HDMI-TX | ||
81 | |||
82 | Example: | ||
83 | |||
84 | tv-connector { | ||
85 | compatible = "composite-video-connector"; | ||
86 | |||
87 | port { | ||
88 | tv_connector_in: endpoint { | ||
89 | remote-endpoint = <&cvbs_vdac_out>; | ||
90 | }; | ||
91 | }; | ||
92 | }; | ||
93 | |||
94 | vpu: vpu@d0100000 { | ||
95 | compatible = "amlogic,meson-gxbb-vpu"; | ||
96 | reg = <0x0 0xd0100000 0x0 0x100000>, | ||
97 | <0x0 0xc883c000 0x0 0x1000>, | ||
98 | <0x0 0xc8838000 0x0 0x1000>; | ||
99 | reg-names = "vpu", "hhi", "dmc"; | ||
100 | interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; | ||
101 | #address-cells = <1>; | ||
102 | #size-cells = <0>; | ||
103 | |||
104 | /* CVBS VDAC output port */ | ||
105 | port@0 { | ||
106 | reg = <0>; | ||
107 | |||
108 | cvbs_vdac_out: endpoint { | ||
109 | remote-endpoint = <&tv_connector_in>; | ||
110 | }; | ||
111 | }; | ||
112 | }; | ||