2 files changed, 41 insertions, 26 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 48dfb305a0b0..51a78283a86d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -175,32 +175,22 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
         if (res_pool != NULL) {
                 struct dc_firmware_info fw_info = { { 0 } };
 
-                if (dc->ctx->dc_bios->funcs->get_firmware_info(
-                                dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
-                                res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency;
-
-                                if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
-                                        // On FPGA these dividers are currently not configured by GDB
-                                        res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
-                                        res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
-                                } else if (res_pool->dccg && res_pool->hubbub) {
-                                        // If DCCG reference frequency cannot be determined (usually means not set to xtalin) then this is a critical error
-                                        // as this value must be known for DCHUB programming
-                                        (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
-                                                        fw_info.pll_info.crystal_frequency,
-                                                        &res_pool->ref_clocks.dccg_ref_clock_inKhz);
-
-                                        // Similarly, if DCHUB reference frequency cannot be determined, then it is also a critical error
-                                        (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
-                                                        res_pool->ref_clocks.dccg_ref_clock_inKhz,
-                                                        &res_pool->ref_clocks.dchub_ref_clock_inKhz);
-                                } else {
-                                        // Not all ASICs have DCCG sw component
-                                        res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
-                                        res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
-                                }
-                        } else
-                                ASSERT_CRITICAL(false);
+                if (dc->ctx->dc_bios->funcs->get_firmware_info(dc->ctx->dc_bios,
+                                &fw_info) == BP_RESULT_OK) {
+                        res_pool->ref_clocks.xtalin_clock_inKhz =
+                                fw_info.pll_info.crystal_frequency;
+                        /* initialize with firmware data first, no all
+                         * ASIC have DCCG SW component. FPGA or
+                         * simulation need initialization of
+                         * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
+                         * with xtalin_clock_inKhz
+                         */
+                        res_pool->ref_clocks.dccg_ref_clock_inKhz =
+                                res_pool->ref_clocks.xtalin_clock_inKhz;
+                        res_pool->ref_clocks.dchub_ref_clock_inKhz =
+                                res_pool->ref_clocks.xtalin_clock_inKhz;
+                } else
+                        ASSERT_CRITICAL(false);
         }
 
         return res_pool;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 6925d25d2457..0b84a322b8a2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -523,6 +523,7 @@ static void dcn20_init_hw(struct dc *dc)
         struct dc_bios *dcb = dc->ctx->dc_bios;
         struct resource_pool *res_pool = dc->res_pool;
         struct dc_state  *context = dc->current_state;
+        struct dc_firmware_info fw_info = { { 0 } };
 
         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
@@ -546,6 +547,30 @@ static void dcn20_init_hw(struct dc *dc)
         } else {
                 if (!dcb->funcs->is_accelerated_mode(dcb)) {
                         bios_golden_init(dc);
+                        if (dc->ctx->dc_bios->funcs->get_firmware_info(
+                                        dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
+                                res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency;
+
+                                if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+                                        if (res_pool->dccg && res_pool->hubbub) {
+
+                                                (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+                                                                fw_info.pll_info.crystal_frequency,
+                                                                &res_pool->ref_clocks.dccg_ref_clock_inKhz);
+
+                                                (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+                                                                res_pool->ref_clocks.dccg_ref_clock_inKhz,
+                                                                &res_pool->ref_clocks.dchub_ref_clock_inKhz);
+                                        } else {
+                                                // Not all ASICs have DCCG sw component
+                                                res_pool->ref_clocks.dccg_ref_clock_inKhz =
+                                                                res_pool->ref_clocks.xtalin_clock_inKhz;
+                                                res_pool->ref_clocks.dchub_ref_clock_inKhz =
+                                                                res_pool->ref_clocks.xtalin_clock_inKhz;
+                                        }
+                                }
+                        } else
+                                ASSERT_CRITICAL(false);
                         disable_vga(dc->hwseq);
                 }