2 files changed, 9 insertions, 0 deletions

diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index b316ab787a3b..ad8c9db61237 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -110,6 +110,8 @@ notrace unsigned long __init early_init(unsigned long dt_ptr)
  * This is called very early on the boot process, after a minimal
  * MMU environment has been set up but before MMU_init is called.
  */
+extern unsigned int memset_nocache_branch; /* Insn to be replaced by NOP */
+
 notrace void __init machine_init(u64 dt_ptr)
 {
         lockdep_init();
@@ -118,6 +120,7 @@ notrace void __init machine_init(u64 dt_ptr)
         udbg_early_init();
 
         patch_instruction((unsigned int *)&memcpy, PPC_INST_NOP);
+        patch_instruction(&memset_nocache_branch, PPC_INST_NOP);
 
         /* Do some early initialization based on the flat device tree */
         early_init_devtree(__va(dt_ptr));
diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S
index da5847d09718..c44df2dbedd5 100644
--- a/arch/powerpc/lib/copy_32.S
+++ b/arch/powerpc/lib/copy_32.S
@@ -73,6 +73,10 @@ CACHELINE_MASK = (L1_CACHE_BYTES-1)
  * Use dcbz on the complete cache lines in the destination
  * to set them to zero.  This requires that the destination
  * area is cacheable.  -- paulus
+ *
+ * During early init, cache might not be active yet, so dcbz cannot be used.
+ * We therefore skip the optimised bloc that uses dcbz. This jump is
+ * replaced by a nop once cache is active. This is done in machine_init()
  */
 _GLOBAL(memset)
         rlwimi  r4,r4,8,16,23
@@ -88,6 +92,8 @@ _GLOBAL(memset)
         subf    r6,r0,r6
         cmplwi  0,r4,0
         bne     2f      /* Use normal procedure if r4 is not zero */
+_GLOBAL(memset_nocache_branch)
+        b       2f      /* Skip optimised bloc until cache is enabled */
 
         clrlwi  r7,r6,32-LG_CACHELINE_BYTES
         add     r8,r7,r5