diff options
-rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/common.h | 2 | ||||
-rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | 30 | ||||
-rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c | 24 | ||||
-rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 9 | ||||
-rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 8 | ||||
-rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 | ||||
-rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c | 11 | ||||
-rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 29 |
8 files changed, 79 insertions, 35 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index 86eba2a7bbea..51077a8dc1f5 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h | |||
@@ -529,6 +529,8 @@ struct mac_device_info { | |||
529 | int unicast_filter_entries; | 529 | int unicast_filter_entries; |
530 | int mcast_bits_log2; | 530 | int mcast_bits_log2; |
531 | unsigned int rx_csum; | 531 | unsigned int rx_csum; |
532 | unsigned int pcs; | ||
533 | unsigned int pmt; | ||
532 | }; | 534 | }; |
533 | 535 | ||
534 | struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins, | 536 | struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins, |
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h index e67136038e55..ff3e5ab39bd0 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | |||
@@ -38,16 +38,26 @@ | |||
38 | #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */ | 38 | #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */ |
39 | 39 | ||
40 | #define GMAC_INT_STATUS 0x00000038 /* interrupt status register */ | 40 | #define GMAC_INT_STATUS 0x00000038 /* interrupt status register */ |
41 | enum dwmac1000_irq_status { | 41 | #define GMAC_INT_STATUS_PMT BIT(3) |
42 | lpiis_irq = 0x400, | 42 | #define GMAC_INT_STATUS_MMCIS BIT(4) |
43 | time_stamp_irq = 0x0200, | 43 | #define GMAC_INT_STATUS_MMCRIS BIT(5) |
44 | mmc_rx_csum_offload_irq = 0x0080, | 44 | #define GMAC_INT_STATUS_MMCTIS BIT(6) |
45 | mmc_tx_irq = 0x0040, | 45 | #define GMAC_INT_STATUS_MMCCSUM BIT(7) |
46 | mmc_rx_irq = 0x0020, | 46 | #define GMAC_INT_STATUS_TSTAMP BIT(9) |
47 | mmc_irq = 0x0010, | 47 | #define GMAC_INT_STATUS_LPIIS BIT(10) |
48 | pmt_irq = 0x0008, | 48 | |
49 | }; | 49 | /* interrupt mask register */ |
50 | #define GMAC_INT_MASK 0x0000003c /* interrupt mask register */ | 50 | #define GMAC_INT_MASK 0x0000003c |
51 | #define GMAC_INT_DISABLE_RGMII BIT(0) | ||
52 | #define GMAC_INT_DISABLE_PCSLINK BIT(1) | ||
53 | #define GMAC_INT_DISABLE_PCSAN BIT(2) | ||
54 | #define GMAC_INT_DISABLE_PMT BIT(3) | ||
55 | #define GMAC_INT_DISABLE_TIMESTAMP BIT(9) | ||
56 | #define GMAC_INT_DISABLE_PCS (GMAC_INT_DISABLE_RGMII | \ | ||
57 | GMAC_INT_DISABLE_PCSLINK | \ | ||
58 | GMAC_INT_DISABLE_PCSAN) | ||
59 | #define GMAC_INT_DEFAULT_MASK (GMAC_INT_DISABLE_TIMESTAMP | \ | ||
60 | GMAC_INT_DISABLE_PCS) | ||
51 | 61 | ||
52 | /* PMT Control and Status */ | 62 | /* PMT Control and Status */ |
53 | #define GMAC_PMT 0x0000002c | 63 | #define GMAC_PMT 0x0000002c |
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c index 9772a43c27ef..0d31f2f80d07 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c | |||
@@ -37,7 +37,10 @@ static void dwmac1000_core_init(struct mac_device_info *hw, int mtu) | |||
37 | { | 37 | { |
38 | void __iomem *ioaddr = hw->pcsr; | 38 | void __iomem *ioaddr = hw->pcsr; |
39 | u32 value = readl(ioaddr + GMAC_CONTROL); | 39 | u32 value = readl(ioaddr + GMAC_CONTROL); |
40 | |||
41 | /* Configure GMAC core */ | ||
40 | value |= GMAC_CORE_INIT; | 42 | value |= GMAC_CORE_INIT; |
43 | |||
41 | if (mtu > 1500) | 44 | if (mtu > 1500) |
42 | value |= GMAC_CONTROL_2K; | 45 | value |= GMAC_CONTROL_2K; |
43 | if (mtu > 2000) | 46 | if (mtu > 2000) |
@@ -46,7 +49,14 @@ static void dwmac1000_core_init(struct mac_device_info *hw, int mtu) | |||
46 | writel(value, ioaddr + GMAC_CONTROL); | 49 | writel(value, ioaddr + GMAC_CONTROL); |
47 | 50 | ||
48 | /* Mask GMAC interrupts */ | 51 | /* Mask GMAC interrupts */ |
49 | writel(0x207, ioaddr + GMAC_INT_MASK); | 52 | value = GMAC_INT_DEFAULT_MASK; |
53 | |||
54 | if (hw->pmt) | ||
55 | value &= ~GMAC_INT_DISABLE_PMT; | ||
56 | if (hw->pcs) | ||
57 | value &= ~GMAC_INT_DISABLE_PCS; | ||
58 | |||
59 | writel(value, ioaddr + GMAC_INT_MASK); | ||
50 | 60 | ||
51 | #ifdef STMMAC_VLAN_TAG_USED | 61 | #ifdef STMMAC_VLAN_TAG_USED |
52 | /* Tag detection without filtering */ | 62 | /* Tag detection without filtering */ |
@@ -283,20 +293,20 @@ static int dwmac1000_irq_status(struct mac_device_info *hw, | |||
283 | int ret = 0; | 293 | int ret = 0; |
284 | 294 | ||
285 | /* Not used events (e.g. MMC interrupts) are not handled. */ | 295 | /* Not used events (e.g. MMC interrupts) are not handled. */ |
286 | if ((intr_status & mmc_tx_irq)) | 296 | if ((intr_status & GMAC_INT_STATUS_MMCTIS)) |
287 | x->mmc_tx_irq_n++; | 297 | x->mmc_tx_irq_n++; |
288 | if (unlikely(intr_status & mmc_rx_irq)) | 298 | if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS)) |
289 | x->mmc_rx_irq_n++; | 299 | x->mmc_rx_irq_n++; |
290 | if (unlikely(intr_status & mmc_rx_csum_offload_irq)) | 300 | if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM)) |
291 | x->mmc_rx_csum_offload_irq_n++; | 301 | x->mmc_rx_csum_offload_irq_n++; |
292 | if (unlikely(intr_status & pmt_irq)) { | 302 | if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) { |
293 | /* clear the PMT bits 5 and 6 by reading the PMT status reg */ | 303 | /* clear the PMT bits 5 and 6 by reading the PMT status reg */ |
294 | readl(ioaddr + GMAC_PMT); | 304 | readl(ioaddr + GMAC_PMT); |
295 | x->irq_receive_pmt_irq_n++; | 305 | x->irq_receive_pmt_irq_n++; |
296 | } | 306 | } |
297 | 307 | ||
298 | /* MAC trx/rx EEE LPI entry/exit interrupts */ | 308 | /* MAC tx/rx EEE LPI entry/exit interrupts */ |
299 | if (intr_status & lpiis_irq) { | 309 | if (intr_status & GMAC_INT_STATUS_LPIIS) { |
300 | /* Clean LPI interrupt by reading the Reg 12 */ | 310 | /* Clean LPI interrupt by reading the Reg 12 */ |
301 | ret = readl(ioaddr + LPI_CTRL_STATUS); | 311 | ret = readl(ioaddr + LPI_CTRL_STATUS); |
302 | 312 | ||
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h index 227fa20d10c1..6f4f5ce25114 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h | |||
@@ -52,9 +52,18 @@ | |||
52 | #define GMAC_TX_FLOW_CTRL_PT_SHIFT 16 | 52 | #define GMAC_TX_FLOW_CTRL_PT_SHIFT 16 |
53 | 53 | ||
54 | /* MAC Interrupt bitmap*/ | 54 | /* MAC Interrupt bitmap*/ |
55 | #define GMAC_INT_RGSMIIS BIT(0) | ||
56 | #define GMAC_INT_PCS_LINK BIT(1) | ||
57 | #define GMAC_INT_PCS_ANE BIT(2) | ||
58 | #define GMAC_INT_PCS_PHYIS BIT(3) | ||
55 | #define GMAC_INT_PMT_EN BIT(4) | 59 | #define GMAC_INT_PMT_EN BIT(4) |
56 | #define GMAC_INT_LPI_EN BIT(5) | 60 | #define GMAC_INT_LPI_EN BIT(5) |
57 | 61 | ||
62 | #define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \ | ||
63 | GMAC_INT_PCS_ANE) | ||
64 | |||
65 | #define GMAC_INT_DEFAULT_MASK GMAC_INT_PMT_EN | ||
66 | |||
58 | enum dwmac4_irq_status { | 67 | enum dwmac4_irq_status { |
59 | time_stamp_irq = 0x00001000, | 68 | time_stamp_irq = 0x00001000, |
60 | mmc_rx_csum_offload_irq = 0x00000800, | 69 | mmc_rx_csum_offload_irq = 0x00000800, |
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c index 207d8bb0c80b..747f3cf1e20b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | |||
@@ -35,7 +35,13 @@ static void dwmac4_core_init(struct mac_device_info *hw, int mtu) | |||
35 | writel(value, ioaddr + GMAC_CONFIG); | 35 | writel(value, ioaddr + GMAC_CONFIG); |
36 | 36 | ||
37 | /* Mask GMAC interrupts */ | 37 | /* Mask GMAC interrupts */ |
38 | writel(GMAC_INT_PMT_EN, ioaddr + GMAC_INT_EN); | 38 | value = GMAC_INT_DEFAULT_MASK; |
39 | if (hw->pmt) | ||
40 | value |= GMAC_INT_PMT_EN; | ||
41 | if (hw->pcs) | ||
42 | value |= GMAC_PCS_IRQ_DEFAULT; | ||
43 | |||
44 | writel(value, ioaddr + GMAC_INT_EN); | ||
39 | } | 45 | } |
40 | 46 | ||
41 | static void dwmac4_dump_regs(struct mac_device_info *hw) | 47 | static void dwmac4_dump_regs(struct mac_device_info *hw) |
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h index 59ae6088cd22..8dc9056c1001 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h | |||
@@ -117,7 +117,6 @@ struct stmmac_priv { | |||
117 | int eee_enabled; | 117 | int eee_enabled; |
118 | int eee_active; | 118 | int eee_active; |
119 | int tx_lpi_timer; | 119 | int tx_lpi_timer; |
120 | int pcs; | ||
121 | unsigned int mode; | 120 | unsigned int mode; |
122 | int extend_desc; | 121 | int extend_desc; |
123 | struct ptp_clock *ptp_clock; | 122 | struct ptp_clock *ptp_clock; |
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c index a5f4f46da42b..da2d9b5b740a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c | |||
@@ -276,7 +276,8 @@ static int stmmac_ethtool_getsettings(struct net_device *dev, | |||
276 | struct phy_device *phy = priv->phydev; | 276 | struct phy_device *phy = priv->phydev; |
277 | int rc; | 277 | int rc; |
278 | 278 | ||
279 | if ((priv->pcs & STMMAC_PCS_RGMII) || (priv->pcs & STMMAC_PCS_SGMII)) { | 279 | if (priv->hw->pcs & STMMAC_PCS_RGMII || |
280 | priv->hw->pcs & STMMAC_PCS_SGMII) { | ||
280 | struct rgmii_adv adv; | 281 | struct rgmii_adv adv; |
281 | 282 | ||
282 | if (!priv->xstats.pcs_link) { | 283 | if (!priv->xstats.pcs_link) { |
@@ -361,7 +362,8 @@ static int stmmac_ethtool_setsettings(struct net_device *dev, | |||
361 | struct phy_device *phy = priv->phydev; | 362 | struct phy_device *phy = priv->phydev; |
362 | int rc; | 363 | int rc; |
363 | 364 | ||
364 | if ((priv->pcs & STMMAC_PCS_RGMII) || (priv->pcs & STMMAC_PCS_SGMII)) { | 365 | if (priv->hw->pcs & STMMAC_PCS_RGMII || |
366 | priv->hw->pcs & STMMAC_PCS_SGMII) { | ||
365 | u32 mask = ADVERTISED_Autoneg | ADVERTISED_Pause; | 367 | u32 mask = ADVERTISED_Autoneg | ADVERTISED_Pause; |
366 | 368 | ||
367 | /* Only support ANE */ | 369 | /* Only support ANE */ |
@@ -457,7 +459,7 @@ stmmac_get_pauseparam(struct net_device *netdev, | |||
457 | pause->rx_pause = 0; | 459 | pause->rx_pause = 0; |
458 | pause->tx_pause = 0; | 460 | pause->tx_pause = 0; |
459 | 461 | ||
460 | if (priv->pcs && priv->hw->mac->pcs_get_adv_lp) { | 462 | if (priv->hw->pcs && priv->hw->mac->pcs_get_adv_lp) { |
461 | struct rgmii_adv adv_lp; | 463 | struct rgmii_adv adv_lp; |
462 | 464 | ||
463 | pause->autoneg = 1; | 465 | pause->autoneg = 1; |
@@ -487,7 +489,7 @@ stmmac_set_pauseparam(struct net_device *netdev, | |||
487 | struct phy_device *phy = priv->phydev; | 489 | struct phy_device *phy = priv->phydev; |
488 | int new_pause = FLOW_OFF; | 490 | int new_pause = FLOW_OFF; |
489 | 491 | ||
490 | if (priv->pcs && priv->hw->mac->pcs_get_adv_lp) { | 492 | if (priv->hw->pcs && priv->hw->mac->pcs_get_adv_lp) { |
491 | struct rgmii_adv adv_lp; | 493 | struct rgmii_adv adv_lp; |
492 | 494 | ||
493 | pause->autoneg = 1; | 495 | pause->autoneg = 1; |
@@ -507,6 +509,7 @@ stmmac_set_pauseparam(struct net_device *netdev, | |||
507 | 509 | ||
508 | priv->flow_ctrl = new_pause; | 510 | priv->flow_ctrl = new_pause; |
509 | phy->autoneg = pause->autoneg; | 511 | phy->autoneg = pause->autoneg; |
512 | |||
510 | if (phy->autoneg) { | 513 | if (phy->autoneg) { |
511 | if (netif_running(netdev)) | 514 | if (netif_running(netdev)) |
512 | return phy_start_aneg(phy); | 515 | return phy_start_aneg(phy); |
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 6c43d6825172..6142fce9ffac 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | |||
@@ -285,8 +285,9 @@ bool stmmac_eee_init(struct stmmac_priv *priv) | |||
285 | /* Using PCS we cannot dial with the phy registers at this stage | 285 | /* Using PCS we cannot dial with the phy registers at this stage |
286 | * so we do not support extra feature like EEE. | 286 | * so we do not support extra feature like EEE. |
287 | */ | 287 | */ |
288 | if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) || | 288 | if ((priv->hw->pcs == STMMAC_PCS_RGMII) || |
289 | (priv->pcs == STMMAC_PCS_RTBI)) | 289 | (priv->hw->pcs == STMMAC_PCS_TBI) || |
290 | (priv->hw->pcs == STMMAC_PCS_RTBI)) | ||
290 | goto out; | 291 | goto out; |
291 | 292 | ||
292 | /* MAC core supports the EEE feature. */ | 293 | /* MAC core supports the EEE feature. */ |
@@ -799,10 +800,10 @@ static void stmmac_check_pcs_mode(struct stmmac_priv *priv) | |||
799 | (interface == PHY_INTERFACE_MODE_RGMII_RXID) || | 800 | (interface == PHY_INTERFACE_MODE_RGMII_RXID) || |
800 | (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { | 801 | (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { |
801 | pr_debug("STMMAC: PCS RGMII support enable\n"); | 802 | pr_debug("STMMAC: PCS RGMII support enable\n"); |
802 | priv->pcs = STMMAC_PCS_RGMII; | 803 | priv->hw->pcs = STMMAC_PCS_RGMII; |
803 | } else if (interface == PHY_INTERFACE_MODE_SGMII) { | 804 | } else if (interface == PHY_INTERFACE_MODE_SGMII) { |
804 | pr_debug("STMMAC: PCS SGMII support enable\n"); | 805 | pr_debug("STMMAC: PCS SGMII support enable\n"); |
805 | priv->pcs = STMMAC_PCS_SGMII; | 806 | priv->hw->pcs = STMMAC_PCS_SGMII; |
806 | } | 807 | } |
807 | } | 808 | } |
808 | } | 809 | } |
@@ -1714,7 +1715,7 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) | |||
1714 | priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); | 1715 | priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); |
1715 | } | 1716 | } |
1716 | 1717 | ||
1717 | if (priv->pcs && priv->hw->mac->pcs_ctrl_ane) | 1718 | if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane) |
1718 | priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, 0, 0); | 1719 | priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, 0, 0); |
1719 | 1720 | ||
1720 | /* set TX ring length */ | 1721 | /* set TX ring length */ |
@@ -1748,8 +1749,9 @@ static int stmmac_open(struct net_device *dev) | |||
1748 | 1749 | ||
1749 | stmmac_check_ether_addr(priv); | 1750 | stmmac_check_ether_addr(priv); |
1750 | 1751 | ||
1751 | if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && | 1752 | if (priv->hw->pcs != STMMAC_PCS_RGMII && |
1752 | priv->pcs != STMMAC_PCS_RTBI) { | 1753 | priv->hw->pcs != STMMAC_PCS_TBI && |
1754 | priv->hw->pcs != STMMAC_PCS_RTBI) { | ||
1753 | ret = stmmac_init_phy(dev); | 1755 | ret = stmmac_init_phy(dev); |
1754 | if (ret) { | 1756 | if (ret) { |
1755 | pr_err("%s: Cannot attach to PHY (error: %d)\n", | 1757 | pr_err("%s: Cannot attach to PHY (error: %d)\n", |
@@ -2811,7 +2813,7 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id) | |||
2811 | } | 2813 | } |
2812 | 2814 | ||
2813 | /* PCS link status */ | 2815 | /* PCS link status */ |
2814 | if (priv->pcs) { | 2816 | if (priv->hw->pcs) { |
2815 | if (priv->xstats.pcs_link) | 2817 | if (priv->xstats.pcs_link) |
2816 | netif_carrier_on(dev); | 2818 | netif_carrier_on(dev); |
2817 | else | 2819 | else |
@@ -3138,6 +3140,7 @@ static int stmmac_hw_init(struct stmmac_priv *priv) | |||
3138 | */ | 3140 | */ |
3139 | priv->plat->enh_desc = priv->dma_cap.enh_desc; | 3141 | priv->plat->enh_desc = priv->dma_cap.enh_desc; |
3140 | priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; | 3142 | priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; |
3143 | priv->hw->pmt = priv->plat->pmt; | ||
3141 | 3144 | ||
3142 | /* TXCOE doesn't work in thresh DMA mode */ | 3145 | /* TXCOE doesn't work in thresh DMA mode */ |
3143 | if (priv->plat->force_thresh_dma_mode) | 3146 | if (priv->plat->force_thresh_dma_mode) |
@@ -3333,8 +3336,9 @@ int stmmac_dvr_probe(struct device *device, | |||
3333 | 3336 | ||
3334 | stmmac_check_pcs_mode(priv); | 3337 | stmmac_check_pcs_mode(priv); |
3335 | 3338 | ||
3336 | if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && | 3339 | if (priv->hw->pcs != STMMAC_PCS_RGMII && |
3337 | priv->pcs != STMMAC_PCS_RTBI) { | 3340 | priv->hw->pcs != STMMAC_PCS_TBI && |
3341 | priv->hw->pcs != STMMAC_PCS_RTBI) { | ||
3338 | /* MDIO bus Registration */ | 3342 | /* MDIO bus Registration */ |
3339 | ret = stmmac_mdio_register(ndev); | 3343 | ret = stmmac_mdio_register(ndev); |
3340 | if (ret < 0) { | 3344 | if (ret < 0) { |
@@ -3384,8 +3388,9 @@ int stmmac_dvr_remove(struct device *dev) | |||
3384 | reset_control_assert(priv->stmmac_rst); | 3388 | reset_control_assert(priv->stmmac_rst); |
3385 | clk_disable_unprepare(priv->pclk); | 3389 | clk_disable_unprepare(priv->pclk); |
3386 | clk_disable_unprepare(priv->stmmac_clk); | 3390 | clk_disable_unprepare(priv->stmmac_clk); |
3387 | if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && | 3391 | if (priv->hw->pcs != STMMAC_PCS_RGMII && |
3388 | priv->pcs != STMMAC_PCS_RTBI) | 3392 | priv->hw->pcs != STMMAC_PCS_TBI && |
3393 | priv->hw->pcs != STMMAC_PCS_RTBI) | ||
3389 | stmmac_mdio_unregister(ndev); | 3394 | stmmac_mdio_unregister(ndev); |
3390 | free_netdev(ndev); | 3395 | free_netdev(ndev); |
3391 | 3396 | ||