aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--drivers/gpu/drm/i915/gvt/handlers.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 7732caa1a546..a6ade66349bd 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1924,7 +1924,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
1924 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1924 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1925 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1925 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1926 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1926 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1927 MMIO_DFH(_MMIO(0x20e4), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1927 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
1928 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1928 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1929 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1929 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 1930 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1930 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1931 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
@@ -3028,7 +3029,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
3028 MMIO_D(CSR_HTP_SKL, D_SKL_PLUS); 3029 MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
3029 MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS); 3030 MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS);
3030 3031
3031 MMIO_D(BDW_SCRATCH1, D_SKL_PLUS); 3032 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3032 3033
3033 MMIO_D(SKL_DFSM, D_SKL_PLUS); 3034 MMIO_D(SKL_DFSM, D_SKL_PLUS);
3034 MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS); 3035 MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
@@ -3041,8 +3042,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
3041 MMIO_D(RPM_CONFIG0, D_SKL_PLUS); 3042 MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
3042 MMIO_D(_MMIO(0xd08), D_SKL_PLUS); 3043 MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
3043 MMIO_D(RC6_LOCATION, D_SKL_PLUS); 3044 MMIO_D(RC6_LOCATION, D_SKL_PLUS);
3044 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS, F_MODE_MASK, 3045 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
3045 NULL, NULL); 3046 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
3046 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3047 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3047 NULL, NULL); 3048 NULL, NULL);
3048 3049
@@ -3061,7 +3062,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
3061 MMIO_D(_MMIO(0x46520), D_SKL_PLUS); 3062 MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
3062 3063
3063 MMIO_D(_MMIO(0xc403c), D_SKL_PLUS); 3064 MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
3064 MMIO_D(_MMIO(0xb004), D_SKL_PLUS); 3065 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3065 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 3066 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
3066 3067
3067 MMIO_D(_MMIO(0x65900), D_SKL_PLUS); 3068 MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
@@ -3273,7 +3274,7 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
3273 MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT); 3274 MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
3274 MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT); 3275 MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
3275 MMIO_D(GEN6_GFXPAUSE, D_BXT); 3276 MMIO_D(GEN6_GFXPAUSE, D_BXT);
3276 MMIO_D(GEN8_L3SQCREG1, D_BXT); 3277 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
3277 3278
3278 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL); 3279 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
3279 3280