2 files changed, 53 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/bitmain/Makefile b/arch/arm64/boot/dts/bitmain/Makefile
new file mode 100644
index 000000000000..be90a6071be0
--- /dev/null
+++ b/arch/arm64/boot/dts/bitmain/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+dtb-$(CONFIG_ARCH_BITMAIN) += bm1880-sophon-edge.dtb
diff --git a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
new file mode 100644
index 000000000000..6a3255597138
--- /dev/null
+++ b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Linaro Ltd.
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+/dts-v1/;
+
+#include "bm1880.dtsi"
+
+/ {
+        compatible = "bitmain,sophon-edge", "bitmain,bm1880";
+        model = "Sophon Edge";
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart2;
+                serial2 = &uart1;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB
+        };
+
+        uart_clk: uart-clk {
+                compatible = "fixed-clock";
+                clock-frequency = <500000000>;
+                #clock-cells = <0>;
+        };
+};
+
+&uart0 {
+        status = "okay";
+        clocks = <&uart_clk>;
+};
+
+&uart1 {
+        status = "okay";
+        clocks = <&uart_clk>;
+};
+
+&uart2 {
+        status = "okay";
+        clocks = <&uart_clk>;
+};