diff options
4 files changed, 90 insertions, 66 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index fe0fa52a9fd2..cd5819789d76 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c | |||
@@ -193,6 +193,7 @@ bool dc_stream_set_cursor_attributes( | |||
193 | 193 | ||
194 | core_dc = stream->ctx->dc; | 194 | core_dc = stream->ctx->dc; |
195 | res_ctx = &core_dc->current_state->res_ctx; | 195 | res_ctx = &core_dc->current_state->res_ctx; |
196 | stream->cursor_attributes = *attributes; | ||
196 | 197 | ||
197 | for (i = 0; i < MAX_PIPES; i++) { | 198 | for (i = 0; i < MAX_PIPES; i++) { |
198 | struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; | 199 | struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; |
@@ -204,34 +205,8 @@ bool dc_stream_set_cursor_attributes( | |||
204 | continue; | 205 | continue; |
205 | 206 | ||
206 | 207 | ||
207 | if (pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes != NULL) | 208 | core_dc->hwss.set_cursor_attribute(pipe_ctx); |
208 | pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( | ||
209 | pipe_ctx->plane_res.ipp, attributes); | ||
210 | |||
211 | if (pipe_ctx->plane_res.hubp != NULL && | ||
212 | pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes != NULL) | ||
213 | pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes( | ||
214 | pipe_ctx->plane_res.hubp, attributes); | ||
215 | |||
216 | if (pipe_ctx->plane_res.mi != NULL && | ||
217 | pipe_ctx->plane_res.mi->funcs->set_cursor_attributes != NULL) | ||
218 | pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( | ||
219 | pipe_ctx->plane_res.mi, attributes); | ||
220 | |||
221 | |||
222 | if (pipe_ctx->plane_res.xfm != NULL && | ||
223 | pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes != NULL) | ||
224 | pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( | ||
225 | pipe_ctx->plane_res.xfm, attributes); | ||
226 | |||
227 | if (pipe_ctx->plane_res.dpp != NULL && | ||
228 | pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes != NULL) | ||
229 | pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes( | ||
230 | pipe_ctx->plane_res.dpp, attributes->color_format); | ||
231 | } | 209 | } |
232 | |||
233 | stream->cursor_attributes = *attributes; | ||
234 | |||
235 | return true; | 210 | return true; |
236 | } | 211 | } |
237 | 212 | ||
@@ -255,21 +230,10 @@ bool dc_stream_set_cursor_position( | |||
255 | 230 | ||
256 | core_dc = stream->ctx->dc; | 231 | core_dc = stream->ctx->dc; |
257 | res_ctx = &core_dc->current_state->res_ctx; | 232 | res_ctx = &core_dc->current_state->res_ctx; |
233 | stream->cursor_position = *position; | ||
258 | 234 | ||
259 | for (i = 0; i < MAX_PIPES; i++) { | 235 | for (i = 0; i < MAX_PIPES; i++) { |
260 | struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; | 236 | struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; |
261 | struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; | ||
262 | struct mem_input *mi = pipe_ctx->plane_res.mi; | ||
263 | struct hubp *hubp = pipe_ctx->plane_res.hubp; | ||
264 | struct dpp *dpp = pipe_ctx->plane_res.dpp; | ||
265 | struct dc_cursor_position pos_cpy = *position; | ||
266 | struct dc_cursor_mi_param param = { | ||
267 | .pixel_clk_khz = stream->timing.pix_clk_khz, | ||
268 | .ref_clk_khz = core_dc->res_pool->ref_clock_inKhz, | ||
269 | .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x, | ||
270 | .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width, | ||
271 | .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz | ||
272 | }; | ||
273 | 237 | ||
274 | if (pipe_ctx->stream != stream || | 238 | if (pipe_ctx->stream != stream || |
275 | (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || | 239 | (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || |
@@ -278,33 +242,9 @@ bool dc_stream_set_cursor_position( | |||
278 | !pipe_ctx->plane_res.ipp) | 242 | !pipe_ctx->plane_res.ipp) |
279 | continue; | 243 | continue; |
280 | 244 | ||
281 | if (pipe_ctx->plane_state->address.type | 245 | core_dc->hwss.set_cursor_position(pipe_ctx); |
282 | == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) | ||
283 | pos_cpy.enable = false; | ||
284 | |||
285 | if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) | ||
286 | pos_cpy.enable = false; | ||
287 | |||
288 | |||
289 | if (ipp != NULL && ipp->funcs->ipp_cursor_set_position != NULL) | ||
290 | ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); | ||
291 | |||
292 | if (mi != NULL && mi->funcs->set_cursor_position != NULL) | ||
293 | mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); | ||
294 | |||
295 | if (!hubp) | ||
296 | continue; | ||
297 | |||
298 | if (hubp->funcs->set_cursor_position != NULL) | ||
299 | hubp->funcs->set_cursor_position(hubp, &pos_cpy, ¶m); | ||
300 | |||
301 | if (dpp != NULL && dpp->funcs->set_cursor_position != NULL) | ||
302 | dpp->funcs->set_cursor_position(dpp, &pos_cpy, ¶m, hubp->curs_attr.width); | ||
303 | |||
304 | } | 246 | } |
305 | 247 | ||
306 | stream->cursor_position = *position; | ||
307 | |||
308 | return true; | 248 | return true; |
309 | } | 249 | } |
310 | 250 | ||
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 9353872b4eca..e7e3028fa5d5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | |||
@@ -2930,6 +2930,44 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, | |||
2930 | } | 2930 | } |
2931 | } | 2931 | } |
2932 | 2932 | ||
2933 | void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) | ||
2934 | { | ||
2935 | struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; | ||
2936 | struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; | ||
2937 | struct mem_input *mi = pipe_ctx->plane_res.mi; | ||
2938 | struct dc_cursor_mi_param param = { | ||
2939 | .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz, | ||
2940 | .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz, | ||
2941 | .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x, | ||
2942 | .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width, | ||
2943 | .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz | ||
2944 | }; | ||
2945 | |||
2946 | if (pipe_ctx->plane_state->address.type | ||
2947 | == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) | ||
2948 | pos_cpy.enable = false; | ||
2949 | |||
2950 | if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) | ||
2951 | pos_cpy.enable = false; | ||
2952 | |||
2953 | ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); | ||
2954 | mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); | ||
2955 | } | ||
2956 | |||
2957 | void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) | ||
2958 | { | ||
2959 | struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; | ||
2960 | |||
2961 | pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( | ||
2962 | pipe_ctx->plane_res.ipp, attributes); | ||
2963 | |||
2964 | pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( | ||
2965 | pipe_ctx->plane_res.mi, attributes); | ||
2966 | |||
2967 | pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( | ||
2968 | pipe_ctx->plane_res.xfm, attributes); | ||
2969 | } | ||
2970 | |||
2933 | static void ready_shared_resources(struct dc *dc, struct dc_state *context) {} | 2971 | static void ready_shared_resources(struct dc *dc, struct dc_state *context) {} |
2934 | 2972 | ||
2935 | static void optimize_shared_resources(struct dc *dc) {} | 2973 | static void optimize_shared_resources(struct dc *dc) {} |
@@ -2972,6 +3010,8 @@ static const struct hw_sequencer_funcs dce110_funcs = { | |||
2972 | .edp_backlight_control = hwss_edp_backlight_control, | 3010 | .edp_backlight_control = hwss_edp_backlight_control, |
2973 | .edp_power_control = hwss_edp_power_control, | 3011 | .edp_power_control = hwss_edp_power_control, |
2974 | .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready, | 3012 | .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready, |
3013 | .set_cursor_position = dce110_set_cursor_position, | ||
3014 | .set_cursor_attribute = dce110_set_cursor_attribute | ||
2975 | }; | 3015 | }; |
2976 | 3016 | ||
2977 | void dce110_hw_sequencer_construct(struct dc *dc) | 3017 | void dce110_hw_sequencer_construct(struct dc *dc) |
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 82572863acab..7b959fa2351e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | |||
@@ -1761,6 +1761,11 @@ static void update_dchubp_dpp( | |||
1761 | &pipe_ctx->plane_res.scl_data.viewport_c); | 1761 | &pipe_ctx->plane_res.scl_data.viewport_c); |
1762 | } | 1762 | } |
1763 | 1763 | ||
1764 | if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { | ||
1765 | dc->hwss.set_cursor_position(pipe_ctx); | ||
1766 | dc->hwss.set_cursor_attribute(pipe_ctx); | ||
1767 | } | ||
1768 | |||
1764 | if (plane_state->update_flags.bits.full_update) { | 1769 | if (plane_state->update_flags.bits.full_update) { |
1765 | /*gamut remap*/ | 1770 | /*gamut remap*/ |
1766 | program_gamut_remap(pipe_ctx); | 1771 | program_gamut_remap(pipe_ctx); |
@@ -2296,7 +2301,7 @@ static bool dcn10_dummy_display_power_gating( | |||
2296 | return true; | 2301 | return true; |
2297 | } | 2302 | } |
2298 | 2303 | ||
2299 | void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) | 2304 | static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) |
2300 | { | 2305 | { |
2301 | struct dc_plane_state *plane_state = pipe_ctx->plane_state; | 2306 | struct dc_plane_state *plane_state = pipe_ctx->plane_state; |
2302 | struct timing_generator *tg = pipe_ctx->stream_res.tg; | 2307 | struct timing_generator *tg = pipe_ctx->stream_res.tg; |
@@ -2316,12 +2321,46 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) | |||
2316 | } | 2321 | } |
2317 | } | 2322 | } |
2318 | 2323 | ||
2319 | void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data) | 2324 | static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data) |
2320 | { | 2325 | { |
2321 | if (hws->ctx->dc->res_pool->hubbub != NULL) | 2326 | if (hws->ctx->dc->res_pool->hubbub != NULL) |
2322 | hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data); | 2327 | hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data); |
2323 | } | 2328 | } |
2324 | 2329 | ||
2330 | static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) | ||
2331 | { | ||
2332 | struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; | ||
2333 | struct hubp *hubp = pipe_ctx->plane_res.hubp; | ||
2334 | struct dpp *dpp = pipe_ctx->plane_res.dpp; | ||
2335 | struct dc_cursor_mi_param param = { | ||
2336 | .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz, | ||
2337 | .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz, | ||
2338 | .viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x, | ||
2339 | .viewport_width = pipe_ctx->plane_res.scl_data.viewport.width, | ||
2340 | .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz | ||
2341 | }; | ||
2342 | |||
2343 | if (pipe_ctx->plane_state->address.type | ||
2344 | == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) | ||
2345 | pos_cpy.enable = false; | ||
2346 | |||
2347 | if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) | ||
2348 | pos_cpy.enable = false; | ||
2349 | |||
2350 | hubp->funcs->set_cursor_position(hubp, &pos_cpy, ¶m); | ||
2351 | dpp->funcs->set_cursor_position(dpp, &pos_cpy, ¶m, hubp->curs_attr.width); | ||
2352 | } | ||
2353 | |||
2354 | static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx) | ||
2355 | { | ||
2356 | struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; | ||
2357 | |||
2358 | pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes( | ||
2359 | pipe_ctx->plane_res.hubp, attributes); | ||
2360 | pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes( | ||
2361 | pipe_ctx->plane_res.dpp, attributes->color_format); | ||
2362 | } | ||
2363 | |||
2325 | static const struct hw_sequencer_funcs dcn10_funcs = { | 2364 | static const struct hw_sequencer_funcs dcn10_funcs = { |
2326 | .program_gamut_remap = program_gamut_remap, | 2365 | .program_gamut_remap = program_gamut_remap, |
2327 | .program_csc_matrix = program_csc_matrix, | 2366 | .program_csc_matrix = program_csc_matrix, |
@@ -2362,6 +2401,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = { | |||
2362 | .edp_backlight_control = hwss_edp_backlight_control, | 2401 | .edp_backlight_control = hwss_edp_backlight_control, |
2363 | .edp_power_control = hwss_edp_power_control, | 2402 | .edp_power_control = hwss_edp_power_control, |
2364 | .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready, | 2403 | .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready, |
2404 | .set_cursor_position = dcn10_set_cursor_position, | ||
2405 | .set_cursor_attribute = dcn10_set_cursor_attribute | ||
2365 | }; | 2406 | }; |
2366 | 2407 | ||
2367 | 2408 | ||
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 4c0aa56f7bae..379c6ecd271a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | |||
@@ -198,6 +198,9 @@ struct hw_sequencer_funcs { | |||
198 | bool enable); | 198 | bool enable); |
199 | void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); | 199 | void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); |
200 | 200 | ||
201 | void (*set_cursor_position)(struct pipe_ctx *pipe); | ||
202 | void (*set_cursor_attribute)(struct pipe_ctx *pipe); | ||
203 | |||
201 | }; | 204 | }; |
202 | 205 | ||
203 | void color_space_to_black_color( | 206 | void color_space_to_black_color( |