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-rw-r--r--drivers/gpu/drm/i915/gvt/gtt.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 244ad1729764..f3a75bb9ec27 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -2183,7 +2183,8 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
2183 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; 2183 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
2184 unsigned long g_gtt_index = off >> info->gtt_entry_size_shift; 2184 unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
2185 unsigned long gma, gfn; 2185 unsigned long gma, gfn;
2186 struct intel_gvt_gtt_entry e, m; 2186 struct intel_gvt_gtt_entry e = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
2187 struct intel_gvt_gtt_entry m = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
2187 dma_addr_t dma_addr; 2188 dma_addr_t dma_addr;
2188 int ret; 2189 int ret;
2189 struct intel_gvt_partial_pte *partial_pte, *pos, *n; 2190 struct intel_gvt_partial_pte *partial_pte, *pos, *n;
@@ -2250,7 +2251,8 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
2250 2251
2251 if (!partial_update && (ops->test_present(&e))) { 2252 if (!partial_update && (ops->test_present(&e))) {
2252 gfn = ops->get_pfn(&e); 2253 gfn = ops->get_pfn(&e);
2253 m = e; 2254 m.val64 = e.val64;
2255 m.type = e.type;
2254 2256
2255 /* one PTE update may be issued in multiple writes and the 2257 /* one PTE update may be issued in multiple writes and the
2256 * first write may not construct a valid gfn 2258 * first write may not construct a valid gfn