diff options
| -rw-r--r-- | drivers/gpu/drm/exynos/exynos_mixer.c | 15 | ||||
| -rw-r--r-- | drivers/gpu/drm/exynos/regs-mixer.h | 1 |
2 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index c00abbe3cd13..d35950121fc4 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c | |||
| @@ -377,6 +377,20 @@ static void mixer_run(struct mixer_context *ctx) | |||
| 377 | mixer_regs_dump(ctx); | 377 | mixer_regs_dump(ctx); |
| 378 | } | 378 | } |
| 379 | 379 | ||
| 380 | static void mixer_stop(struct mixer_context *ctx) | ||
| 381 | { | ||
| 382 | struct mixer_resources *res = &ctx->mixer_res; | ||
| 383 | int timeout = 20; | ||
| 384 | |||
| 385 | mixer_reg_writemask(res, MXR_STATUS, 0, MXR_STATUS_REG_RUN); | ||
| 386 | |||
| 387 | while (!(mixer_reg_read(res, MXR_STATUS) & MXR_STATUS_REG_IDLE) && | ||
| 388 | --timeout) | ||
| 389 | usleep_range(10000, 12000); | ||
| 390 | |||
| 391 | mixer_regs_dump(ctx); | ||
| 392 | } | ||
| 393 | |||
| 380 | static void vp_video_buffer(struct mixer_context *ctx, int win) | 394 | static void vp_video_buffer(struct mixer_context *ctx, int win) |
| 381 | { | 395 | { |
| 382 | struct mixer_resources *res = &ctx->mixer_res; | 396 | struct mixer_resources *res = &ctx->mixer_res; |
| @@ -1094,6 +1108,7 @@ static void mixer_poweroff(struct exynos_drm_manager *mgr) | |||
| 1094 | } | 1108 | } |
| 1095 | mutex_unlock(&ctx->mixer_mutex); | 1109 | mutex_unlock(&ctx->mixer_mutex); |
| 1096 | 1110 | ||
| 1111 | mixer_stop(ctx); | ||
| 1097 | mixer_window_suspend(mgr); | 1112 | mixer_window_suspend(mgr); |
| 1098 | 1113 | ||
| 1099 | ctx->int_en = mixer_reg_read(res, MXR_INT_EN); | 1114 | ctx->int_en = mixer_reg_read(res, MXR_INT_EN); |
diff --git a/drivers/gpu/drm/exynos/regs-mixer.h b/drivers/gpu/drm/exynos/regs-mixer.h index 4537026bc385..5f32e1a29411 100644 --- a/drivers/gpu/drm/exynos/regs-mixer.h +++ b/drivers/gpu/drm/exynos/regs-mixer.h | |||
| @@ -78,6 +78,7 @@ | |||
| 78 | #define MXR_STATUS_BIG_ENDIAN (1 << 3) | 78 | #define MXR_STATUS_BIG_ENDIAN (1 << 3) |
| 79 | #define MXR_STATUS_ENDIAN_MASK (1 << 3) | 79 | #define MXR_STATUS_ENDIAN_MASK (1 << 3) |
| 80 | #define MXR_STATUS_SYNC_ENABLE (1 << 2) | 80 | #define MXR_STATUS_SYNC_ENABLE (1 << 2) |
| 81 | #define MXR_STATUS_REG_IDLE (1 << 1) | ||
| 81 | #define MXR_STATUS_REG_RUN (1 << 0) | 82 | #define MXR_STATUS_REG_RUN (1 << 0) |
| 82 | 83 | ||
| 83 | /* bits for MXR_CFG */ | 84 | /* bits for MXR_CFG */ |
