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-rw-r--r--drivers/gpu/drm/i915/gvt/handlers.c18
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index aeecf315c5db..d85264d48585 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -113,9 +113,17 @@ static int new_mmio_info(struct intel_gvt *gvt,
113 113
114 info->offset = i; 114 info->offset = i;
115 p = find_mmio_info(gvt, info->offset); 115 p = find_mmio_info(gvt, info->offset);
116 if (p) 116 if (p) {
117 gvt_err("dup mmio definition offset %x\n", 117 WARN(1, "dup mmio definition offset %x\n",
118 info->offset); 118 info->offset);
119 kfree(info);
120
121 /* We return -EEXIST here to make GVT-g load fail.
122 * So duplicated MMIO can be found as soon as
123 * possible.
124 */
125 return -EEXIST;
126 }
119 127
120 info->ro_mask = ro_mask; 128 info->ro_mask = ro_mask;
121 info->device = device; 129 info->device = device;
@@ -2583,7 +2591,6 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2583 MMIO_F(0x24d0, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, 2591 MMIO_F(0x24d0, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
2584 NULL, force_nonpriv_write); 2592 NULL, force_nonpriv_write);
2585 2593
2586 MMIO_D(0x22040, D_BDW_PLUS);
2587 MMIO_D(0x44484, D_BDW_PLUS); 2594 MMIO_D(0x44484, D_BDW_PLUS);
2588 MMIO_D(0x4448c, D_BDW_PLUS); 2595 MMIO_D(0x4448c, D_BDW_PLUS);
2589 2596
@@ -2641,7 +2648,6 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
2641 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL_PLUS); 2648 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL_PLUS);
2642 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL_PLUS, NULL, 2649 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL_PLUS, NULL,
2643 skl_power_well_ctl_write); 2650 skl_power_well_ctl_write);
2644 MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL_PLUS, NULL, mailbox_write);
2645 2651
2646 MMIO_D(0xa210, D_SKL_PLUS); 2652 MMIO_D(0xa210, D_SKL_PLUS);
2647 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2653 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
@@ -2833,7 +2839,6 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
2833 MMIO_D(0x320f0, D_SKL | D_KBL); 2839 MMIO_D(0x320f0, D_SKL | D_KBL);
2834 2840
2835 MMIO_DFH(_REG_VCS2_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2841 MMIO_DFH(_REG_VCS2_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2836 MMIO_DFH(_REG_VECS_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2837 MMIO_D(0x70034, D_SKL_PLUS); 2842 MMIO_D(0x70034, D_SKL_PLUS);
2838 MMIO_D(0x71034, D_SKL_PLUS); 2843 MMIO_D(0x71034, D_SKL_PLUS);
2839 MMIO_D(0x72034, D_SKL_PLUS); 2844 MMIO_D(0x72034, D_SKL_PLUS);
@@ -2851,10 +2856,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
2851 NULL, NULL); 2856 NULL, NULL);
2852 2857
2853 MMIO_D(0x4ab8, D_KBL); 2858 MMIO_D(0x4ab8, D_KBL);
2854 MMIO_D(0x940c, D_SKL_PLUS);
2855 MMIO_D(0x2248, D_SKL_PLUS | D_KBL); 2859 MMIO_D(0x2248, D_SKL_PLUS | D_KBL);
2856 MMIO_D(0x4ab0, D_SKL | D_KBL);
2857 MMIO_D(0x20d4, D_SKL | D_KBL);
2858 2860
2859 return 0; 2861 return 0;
2860} 2862}