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-rw-r--r--Documentation/devicetree/bindings/mtd/nand.txt9
-rw-r--r--MAINTAINERS6
-rw-r--r--drivers/mtd/mtdcore.c104
-rw-r--r--drivers/mtd/mtdpart.c19
-rw-r--r--drivers/mtd/nand/Kconfig12
-rw-r--r--drivers/mtd/nand/bf5xx_nand.c3
-rw-r--r--drivers/mtd/nand/brcmnand/brcmnand.c15
-rw-r--r--drivers/mtd/nand/brcmnand/brcmnand.h13
-rw-r--r--drivers/mtd/nand/brcmnand/iproc_nand.c18
-rw-r--r--drivers/mtd/nand/docg4.c3
-rw-r--r--drivers/mtd/nand/fsl_elbc_nand.c3
-rw-r--r--drivers/mtd/nand/fsl_ifc_nand.c3
-rw-r--r--drivers/mtd/nand/gpmi-nand/gpmi-nand.c3
-rw-r--r--drivers/mtd/nand/jz4780_nand.c3
-rw-r--r--drivers/mtd/nand/mxc_nand.c137
-rw-r--r--drivers/mtd/nand/nand_base.c260
-rw-r--r--drivers/mtd/nand/nand_bbt.c161
-rw-r--r--drivers/mtd/nand/nand_timings.c470
-rw-r--r--drivers/mtd/nand/ndfc.c3
-rw-r--r--drivers/mtd/nand/pxa3xx_nand.c3
-rw-r--r--drivers/mtd/nand/qcom_nandc.c3
-rw-r--r--drivers/mtd/nand/s3c2410.c7
-rw-r--r--drivers/mtd/nand/sh_flctl.c8
-rw-r--r--drivers/mtd/nand/sunxi_nand.c108
-rw-r--r--drivers/mtd/nand/txx9ndfmc.c3
-rw-r--r--drivers/of/Kconfig4
-rw-r--r--include/linux/mtd/mtd.h107
-rw-r--r--include/linux/mtd/nand.h234
28 files changed, 1263 insertions, 459 deletions
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt
index 3733300de8dd..b05601600083 100644
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ b/Documentation/devicetree/bindings/mtd/nand.txt
@@ -35,6 +35,15 @@ Optional NAND chip properties:
35- nand-ecc-step-size: integer representing the number of data bytes 35- nand-ecc-step-size: integer representing the number of data bytes
36 that are covered by a single ECC step. 36 that are covered by a single ECC step.
37 37
38- nand-ecc-maximize: boolean used to specify that you want to maximize ECC
39 strength. The maximum ECC strength is both controller and
40 chip dependent. The controller side has to select the ECC
41 config providing the best strength and taking the OOB area
42 size constraint into account.
43 This is particularly useful when only the in-band area is
44 used by the upper layers, and you want to make your NAND
45 as reliable as possible.
46
38The ECC strength and ECC step size properties define the correction capability 47The ECC strength and ECC step size properties define the correction capability
39of a controller. Together, they say a controller can correct "{strength} bit 48of a controller. Together, they say a controller can correct "{strength} bit
40errors per {size} bytes". 49errors per {size} bytes".
diff --git a/MAINTAINERS b/MAINTAINERS
index a009e004f8f7..4347bce8ada6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6142,6 +6142,12 @@ M: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
6142S: Maintained 6142S: Maintained
6143F: drivers/dma/dma-jz4780.c 6143F: drivers/dma/dma-jz4780.c
6144 6144
6145INGENIC JZ4780 NAND DRIVER
6146M: Harvey Hunt <harveyhuntnexus@gmail.com>
6147L: linux-mtd@lists.infradead.org
6148S: Maintained
6149F: drivers/mtd/nand/jz4780_*
6150
6145INTEGRITY MEASUREMENT ARCHITECTURE (IMA) 6151INTEGRITY MEASUREMENT ARCHITECTURE (IMA)
6146M: Mimi Zohar <zohar@linux.vnet.ibm.com> 6152M: Mimi Zohar <zohar@linux.vnet.ibm.com>
6147M: Dmitry Kasatkin <dmitry.kasatkin@gmail.com> 6153M: Dmitry Kasatkin <dmitry.kasatkin@gmail.com>
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index e3936b847c6b..4f270482cfd0 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -376,6 +376,110 @@ static int mtd_reboot_notifier(struct notifier_block *n, unsigned long state,
376} 376}
377 377
378/** 378/**
379 * mtd_wunit_to_pairing_info - get pairing information of a wunit
380 * @mtd: pointer to new MTD device info structure
381 * @wunit: write unit we are interested in
382 * @info: returned pairing information
383 *
384 * Retrieve pairing information associated to the wunit.
385 * This is mainly useful when dealing with MLC/TLC NANDs where pages can be
386 * paired together, and where programming a page may influence the page it is
387 * paired with.
388 * The notion of page is replaced by the term wunit (write-unit) to stay
389 * consistent with the ->writesize field.
390 *
391 * The @wunit argument can be extracted from an absolute offset using
392 * mtd_offset_to_wunit(). @info is filled with the pairing information attached
393 * to @wunit.
394 *
395 * From the pairing info the MTD user can find all the wunits paired with
396 * @wunit using the following loop:
397 *
398 * for (i = 0; i < mtd_pairing_groups(mtd); i++) {
399 * info.pair = i;
400 * mtd_pairing_info_to_wunit(mtd, &info);
401 * ...
402 * }
403 */
404int mtd_wunit_to_pairing_info(struct mtd_info *mtd, int wunit,
405 struct mtd_pairing_info *info)
406{
407 int npairs = mtd_wunit_per_eb(mtd) / mtd_pairing_groups(mtd);
408
409 if (wunit < 0 || wunit >= npairs)
410 return -EINVAL;
411
412 if (mtd->pairing && mtd->pairing->get_info)
413 return mtd->pairing->get_info(mtd, wunit, info);
414
415 info->group = 0;
416 info->pair = wunit;
417
418 return 0;
419}
420EXPORT_SYMBOL_GPL(mtd_wunit_to_pairing_info);
421
422/**
423 * mtd_wunit_to_pairing_info - get wunit from pairing information
424 * @mtd: pointer to new MTD device info structure
425 * @info: pairing information struct
426 *
427 * Returns a positive number representing the wunit associated to the info
428 * struct, or a negative error code.
429 *
430 * This is the reverse of mtd_wunit_to_pairing_info(), and can help one to
431 * iterate over all wunits of a given pair (see mtd_wunit_to_pairing_info()
432 * doc).
433 *
434 * It can also be used to only program the first page of each pair (i.e.
435 * page attached to group 0), which allows one to use an MLC NAND in
436 * software-emulated SLC mode:
437 *
438 * info.group = 0;
439 * npairs = mtd_wunit_per_eb(mtd) / mtd_pairing_groups(mtd);
440 * for (info.pair = 0; info.pair < npairs; info.pair++) {
441 * wunit = mtd_pairing_info_to_wunit(mtd, &info);
442 * mtd_write(mtd, mtd_wunit_to_offset(mtd, blkoffs, wunit),
443 * mtd->writesize, &retlen, buf + (i * mtd->writesize));
444 * }
445 */
446int mtd_pairing_info_to_wunit(struct mtd_info *mtd,
447 const struct mtd_pairing_info *info)
448{
449 int ngroups = mtd_pairing_groups(mtd);
450 int npairs = mtd_wunit_per_eb(mtd) / ngroups;
451
452 if (!info || info->pair < 0 || info->pair >= npairs ||
453 info->group < 0 || info->group >= ngroups)
454 return -EINVAL;
455
456 if (mtd->pairing && mtd->pairing->get_wunit)
457 return mtd->pairing->get_wunit(mtd, info);
458
459 return info->pair;
460}
461EXPORT_SYMBOL_GPL(mtd_pairing_info_to_wunit);
462
463/**
464 * mtd_pairing_groups - get the number of pairing groups
465 * @mtd: pointer to new MTD device info structure
466 *
467 * Returns the number of pairing groups.
468 *
469 * This number is usually equal to the number of bits exposed by a single
470 * cell, and can be used in conjunction with mtd_pairing_info_to_wunit()
471 * to iterate over all pages of a given pair.
472 */
473int mtd_pairing_groups(struct mtd_info *mtd)
474{
475 if (!mtd->pairing || !mtd->pairing->ngroups)
476 return 1;
477
478 return mtd->pairing->ngroups;
479}
480EXPORT_SYMBOL_GPL(mtd_pairing_groups);
481
482/**
379 * add_mtd_device - register an MTD device 483 * add_mtd_device - register an MTD device
380 * @mtd: pointer to new MTD device info structure 484 * @mtd: pointer to new MTD device info structure
381 * 485 *
diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c
index 1f13e32556f8..c1f34f04e338 100644
--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
@@ -317,6 +317,18 @@ static int part_block_markbad(struct mtd_info *mtd, loff_t ofs)
317 return res; 317 return res;
318} 318}
319 319
320static int part_get_device(struct mtd_info *mtd)
321{
322 struct mtd_part *part = mtd_to_part(mtd);
323 return part->master->_get_device(part->master);
324}
325
326static void part_put_device(struct mtd_info *mtd)
327{
328 struct mtd_part *part = mtd_to_part(mtd);
329 part->master->_put_device(part->master);
330}
331
320static int part_ooblayout_ecc(struct mtd_info *mtd, int section, 332static int part_ooblayout_ecc(struct mtd_info *mtd, int section,
321 struct mtd_oob_region *oobregion) 333 struct mtd_oob_region *oobregion)
322{ 334{
@@ -397,6 +409,7 @@ static struct mtd_part *allocate_partition(struct mtd_info *master,
397 slave->mtd.oobsize = master->oobsize; 409 slave->mtd.oobsize = master->oobsize;
398 slave->mtd.oobavail = master->oobavail; 410 slave->mtd.oobavail = master->oobavail;
399 slave->mtd.subpage_sft = master->subpage_sft; 411 slave->mtd.subpage_sft = master->subpage_sft;
412 slave->mtd.pairing = master->pairing;
400 413
401 slave->mtd.name = name; 414 slave->mtd.name = name;
402 slave->mtd.owner = master->owner; 415 slave->mtd.owner = master->owner;
@@ -463,6 +476,12 @@ static struct mtd_part *allocate_partition(struct mtd_info *master,
463 slave->mtd._block_isbad = part_block_isbad; 476 slave->mtd._block_isbad = part_block_isbad;
464 if (master->_block_markbad) 477 if (master->_block_markbad)
465 slave->mtd._block_markbad = part_block_markbad; 478 slave->mtd._block_markbad = part_block_markbad;
479
480 if (master->_get_device)
481 slave->mtd._get_device = part_get_device;
482 if (master->_put_device)
483 slave->mtd._put_device = part_put_device;
484
466 slave->mtd._erase = part_erase; 485 slave->mtd._erase = part_erase;
467 slave->master = master; 486 slave->master = master;
468 slave->offset = part->offset; 487 slave->offset = part->offset;
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 21ff58099f3b..7b7a887b4709 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -88,11 +88,11 @@ config MTD_NAND_AMS_DELTA
88 Support for NAND flash on Amstrad E3 (Delta). 88 Support for NAND flash on Amstrad E3 (Delta).
89 89
90config MTD_NAND_OMAP2 90config MTD_NAND_OMAP2
91 tristate "NAND Flash device on OMAP2, OMAP3 and OMAP4" 91 tristate "NAND Flash device on OMAP2, OMAP3, OMAP4 and Keystone"
92 depends on ARCH_OMAP2PLUS 92 depends on (ARCH_OMAP2PLUS || ARCH_KEYSTONE)
93 help 93 help
94 Support for NAND flash on Texas Instruments OMAP2, OMAP3 and OMAP4 94 Support for NAND flash on Texas Instruments OMAP2, OMAP3, OMAP4
95 platforms. 95 and Keystone platforms.
96 96
97config MTD_NAND_OMAP_BCH 97config MTD_NAND_OMAP_BCH
98 depends on MTD_NAND_OMAP2 98 depends on MTD_NAND_OMAP2
@@ -428,7 +428,7 @@ config MTD_NAND_ORION
428 428
429config MTD_NAND_FSL_ELBC 429config MTD_NAND_FSL_ELBC
430 tristate "NAND support for Freescale eLBC controllers" 430 tristate "NAND support for Freescale eLBC controllers"
431 depends on PPC 431 depends on FSL_SOC
432 select FSL_LBC 432 select FSL_LBC
433 help 433 help
434 Various Freescale chips, including the 8313, include a NAND Flash 434 Various Freescale chips, including the 8313, include a NAND Flash
@@ -438,7 +438,7 @@ config MTD_NAND_FSL_ELBC
438 438
439config MTD_NAND_FSL_IFC 439config MTD_NAND_FSL_IFC
440 tristate "NAND support for Freescale IFC controller" 440 tristate "NAND support for Freescale IFC controller"
441 depends on MTD_NAND && (FSL_SOC || ARCH_LAYERSCAPE) 441 depends on FSL_SOC || ARCH_LAYERSCAPE
442 select FSL_IFC 442 select FSL_IFC
443 select MEMORY 443 select MEMORY
444 help 444 help
diff --git a/drivers/mtd/nand/bf5xx_nand.c b/drivers/mtd/nand/bf5xx_nand.c
index 37da4236ab90..3962f55bd034 100644
--- a/drivers/mtd/nand/bf5xx_nand.c
+++ b/drivers/mtd/nand/bf5xx_nand.c
@@ -761,8 +761,7 @@ static int bf5xx_nand_probe(struct platform_device *pdev)
761 761
762 platform_set_drvdata(pdev, info); 762 platform_set_drvdata(pdev, info);
763 763
764 spin_lock_init(&info->controller.lock); 764 nand_hw_control_init(&info->controller);
765 init_waitqueue_head(&info->controller.wq);
766 765
767 info->device = &pdev->dev; 766 info->device = &pdev->dev;
768 info->platform = plat; 767 info->platform = plat;
diff --git a/drivers/mtd/nand/brcmnand/brcmnand.c b/drivers/mtd/nand/brcmnand/brcmnand.c
index 8eb2c64df38c..9d2424bfdbf5 100644
--- a/drivers/mtd/nand/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/brcmnand/brcmnand.c
@@ -1336,7 +1336,7 @@ static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1336 u32 *flash_cache = (u32 *)ctrl->flash_cache; 1336 u32 *flash_cache = (u32 *)ctrl->flash_cache;
1337 int i; 1337 int i;
1338 1338
1339 brcmnand_soc_data_bus_prepare(ctrl->soc); 1339 brcmnand_soc_data_bus_prepare(ctrl->soc, true);
1340 1340
1341 /* 1341 /*
1342 * Must cache the FLASH_CACHE now, since changes in 1342 * Must cache the FLASH_CACHE now, since changes in
@@ -1349,7 +1349,7 @@ static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1349 */ 1349 */
1350 flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i)); 1350 flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i));
1351 1351
1352 brcmnand_soc_data_bus_unprepare(ctrl->soc); 1352 brcmnand_soc_data_bus_unprepare(ctrl->soc, true);
1353 1353
1354 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */ 1354 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1355 if (host->hwcfg.sector_size_1k) 1355 if (host->hwcfg.sector_size_1k)
@@ -1565,12 +1565,12 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1565 brcmnand_waitfunc(mtd, chip); 1565 brcmnand_waitfunc(mtd, chip);
1566 1566
1567 if (likely(buf)) { 1567 if (likely(buf)) {
1568 brcmnand_soc_data_bus_prepare(ctrl->soc); 1568 brcmnand_soc_data_bus_prepare(ctrl->soc, false);
1569 1569
1570 for (j = 0; j < FC_WORDS; j++, buf++) 1570 for (j = 0; j < FC_WORDS; j++, buf++)
1571 *buf = brcmnand_read_fc(ctrl, j); 1571 *buf = brcmnand_read_fc(ctrl, j);
1572 1572
1573 brcmnand_soc_data_bus_unprepare(ctrl->soc); 1573 brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
1574 } 1574 }
1575 1575
1576 if (oob) 1576 if (oob)
@@ -1815,12 +1815,12 @@ static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1815 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); 1815 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1816 1816
1817 if (buf) { 1817 if (buf) {
1818 brcmnand_soc_data_bus_prepare(ctrl->soc); 1818 brcmnand_soc_data_bus_prepare(ctrl->soc, false);
1819 1819
1820 for (j = 0; j < FC_WORDS; j++, buf++) 1820 for (j = 0; j < FC_WORDS; j++, buf++)
1821 brcmnand_write_fc(ctrl, j, *buf); 1821 brcmnand_write_fc(ctrl, j, *buf);
1822 1822
1823 brcmnand_soc_data_bus_unprepare(ctrl->soc); 1823 brcmnand_soc_data_bus_unprepare(ctrl->soc, false);
1824 } else if (oob) { 1824 } else if (oob) {
1825 for (j = 0; j < FC_WORDS; j++) 1825 for (j = 0; j < FC_WORDS; j++)
1826 brcmnand_write_fc(ctrl, j, 0xffffffff); 1826 brcmnand_write_fc(ctrl, j, 0xffffffff);
@@ -2370,8 +2370,7 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2370 2370
2371 init_completion(&ctrl->done); 2371 init_completion(&ctrl->done);
2372 init_completion(&ctrl->dma_done); 2372 init_completion(&ctrl->dma_done);
2373 spin_lock_init(&ctrl->controller.lock); 2373 nand_hw_control_init(&ctrl->controller);
2374 init_waitqueue_head(&ctrl->controller.wq);
2375 INIT_LIST_HEAD(&ctrl->host_list); 2374 INIT_LIST_HEAD(&ctrl->host_list);
2376 2375
2377 /* NAND register range */ 2376 /* NAND register range */
diff --git a/drivers/mtd/nand/brcmnand/brcmnand.h b/drivers/mtd/nand/brcmnand/brcmnand.h
index ef5eabba88e5..5c44cd4aba87 100644
--- a/drivers/mtd/nand/brcmnand/brcmnand.h
+++ b/drivers/mtd/nand/brcmnand/brcmnand.h
@@ -23,19 +23,22 @@ struct dev_pm_ops;
23struct brcmnand_soc { 23struct brcmnand_soc {
24 bool (*ctlrdy_ack)(struct brcmnand_soc *soc); 24 bool (*ctlrdy_ack)(struct brcmnand_soc *soc);
25 void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en); 25 void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en);
26 void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare); 26 void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare,
27 bool is_param);
27}; 28};
28 29
29static inline void brcmnand_soc_data_bus_prepare(struct brcmnand_soc *soc) 30static inline void brcmnand_soc_data_bus_prepare(struct brcmnand_soc *soc,
31 bool is_param)
30{ 32{
31 if (soc && soc->prepare_data_bus) 33 if (soc && soc->prepare_data_bus)
32 soc->prepare_data_bus(soc, true); 34 soc->prepare_data_bus(soc, true, is_param);
33} 35}
34 36
35static inline void brcmnand_soc_data_bus_unprepare(struct brcmnand_soc *soc) 37static inline void brcmnand_soc_data_bus_unprepare(struct brcmnand_soc *soc,
38 bool is_param)
36{ 39{
37 if (soc && soc->prepare_data_bus) 40 if (soc && soc->prepare_data_bus)
38 soc->prepare_data_bus(soc, false); 41 soc->prepare_data_bus(soc, false, is_param);
39} 42}
40 43
41static inline u32 brcmnand_readl(void __iomem *addr) 44static inline u32 brcmnand_readl(void __iomem *addr)
diff --git a/drivers/mtd/nand/brcmnand/iproc_nand.c b/drivers/mtd/nand/brcmnand/iproc_nand.c
index 585596c549b2..4c6ae113664d 100644
--- a/drivers/mtd/nand/brcmnand/iproc_nand.c
+++ b/drivers/mtd/nand/brcmnand/iproc_nand.c
@@ -74,7 +74,8 @@ static void iproc_nand_intc_set(struct brcmnand_soc *soc, bool en)
74 spin_unlock_irqrestore(&priv->idm_lock, flags); 74 spin_unlock_irqrestore(&priv->idm_lock, flags);
75} 75}
76 76
77static void iproc_nand_apb_access(struct brcmnand_soc *soc, bool prepare) 77static void iproc_nand_apb_access(struct brcmnand_soc *soc, bool prepare,
78 bool is_param)
78{ 79{
79 struct iproc_nand_soc *priv = 80 struct iproc_nand_soc *priv =
80 container_of(soc, struct iproc_nand_soc, soc); 81 container_of(soc, struct iproc_nand_soc, soc);
@@ -86,10 +87,19 @@ static void iproc_nand_apb_access(struct brcmnand_soc *soc, bool prepare)
86 87
87 val = brcmnand_readl(mmio); 88 val = brcmnand_readl(mmio);
88 89
89 if (prepare) 90 /*
90 val |= IPROC_NAND_APB_LE_MODE; 91 * In the case of BE or when dealing with NAND data, alway configure
91 else 92 * the APB bus to LE mode before accessing the FIFO and back to BE mode
93 * after the access is done
94 */
95 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) || !is_param) {
96 if (prepare)
97 val |= IPROC_NAND_APB_LE_MODE;
98 else
99 val &= ~IPROC_NAND_APB_LE_MODE;
100 } else { /* when in LE accessing the parameter page, keep APB in BE */
92 val &= ~IPROC_NAND_APB_LE_MODE; 101 val &= ~IPROC_NAND_APB_LE_MODE;
102 }
93 103
94 brcmnand_writel(val, mmio); 104 brcmnand_writel(val, mmio);
95 105
diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c
index 47316998017f..7af2a3cd949e 100644
--- a/drivers/mtd/nand/docg4.c
+++ b/drivers/mtd/nand/docg4.c
@@ -1249,8 +1249,7 @@ static void __init init_mtd_structs(struct mtd_info *mtd)
1249 nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE; 1249 nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE;
1250 nand->IO_ADDR_R = nand->IO_ADDR_W = doc->virtadr + DOC_IOSPACE_DATA; 1250 nand->IO_ADDR_R = nand->IO_ADDR_W = doc->virtadr + DOC_IOSPACE_DATA;
1251 nand->controller = &nand->hwcontrol; 1251 nand->controller = &nand->hwcontrol;
1252 spin_lock_init(&nand->controller->lock); 1252 nand_hw_control_init(nand->controller);
1253 init_waitqueue_head(&nand->controller->wq);
1254 1253
1255 /* methods */ 1254 /* methods */
1256 nand->cmdfunc = docg4_command; 1255 nand->cmdfunc = docg4_command;
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 60a88f24c6b3..113f76e59937 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -879,8 +879,7 @@ static int fsl_elbc_nand_probe(struct platform_device *pdev)
879 } 879 }
880 elbc_fcm_ctrl->counter++; 880 elbc_fcm_ctrl->counter++;
881 881
882 spin_lock_init(&elbc_fcm_ctrl->controller.lock); 882 nand_hw_control_init(&elbc_fcm_ctrl->controller);
883 init_waitqueue_head(&elbc_fcm_ctrl->controller.wq);
884 fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl; 883 fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
885 } else { 884 } else {
886 elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; 885 elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 4e9e5fd8faf3..0a177b1bfe3e 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -987,8 +987,7 @@ static int fsl_ifc_nand_probe(struct platform_device *dev)
987 ifc_nand_ctrl->addr = NULL; 987 ifc_nand_ctrl->addr = NULL;
988 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl; 988 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
989 989
990 spin_lock_init(&ifc_nand_ctrl->controller.lock); 990 nand_hw_control_init(&ifc_nand_ctrl->controller);
991 init_waitqueue_head(&ifc_nand_ctrl->controller.wq);
992 } else { 991 } else {
993 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand; 992 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
994 } 993 }
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 6e461560c6a8..6c062b8251d2 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -318,7 +318,8 @@ static int legacy_set_geometry(struct gpmi_nand_data *this)
318 return -EINVAL; 318 return -EINVAL;
319 } 319 }
320 320
321 geo->page_size = mtd->writesize + mtd->oobsize; 321 geo->page_size = mtd->writesize + geo->metadata_size +
322 (geo->gf_len * geo->ecc_strength * geo->ecc_chunk_count) / 8;
322 geo->payload_size = mtd->writesize; 323 geo->payload_size = mtd->writesize;
323 324
324 /* 325 /*
diff --git a/drivers/mtd/nand/jz4780_nand.c b/drivers/mtd/nand/jz4780_nand.c
index 175f67da25af..a39bb70175ee 100644
--- a/drivers/mtd/nand/jz4780_nand.c
+++ b/drivers/mtd/nand/jz4780_nand.c
@@ -368,9 +368,8 @@ static int jz4780_nand_probe(struct platform_device *pdev)
368 nfc->dev = dev; 368 nfc->dev = dev;
369 nfc->num_banks = num_banks; 369 nfc->num_banks = num_banks;
370 370
371 spin_lock_init(&nfc->controller.lock); 371 nand_hw_control_init(&nfc->controller);
372 INIT_LIST_HEAD(&nfc->chips); 372 INIT_LIST_HEAD(&nfc->chips);
373 init_waitqueue_head(&nfc->controller.wq);
374 373
375 ret = jz4780_nand_init_chips(nfc, pdev); 374 ret = jz4780_nand_init_chips(nfc, pdev);
376 if (ret) { 375 if (ret) {
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 57cbe2b83849..d7f724b24fd7 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -152,6 +152,9 @@ struct mxc_nand_devtype_data {
152 void (*select_chip)(struct mtd_info *mtd, int chip); 152 void (*select_chip)(struct mtd_info *mtd, int chip);
153 int (*correct_data)(struct mtd_info *mtd, u_char *dat, 153 int (*correct_data)(struct mtd_info *mtd, u_char *dat,
154 u_char *read_ecc, u_char *calc_ecc); 154 u_char *read_ecc, u_char *calc_ecc);
155 int (*setup_data_interface)(struct mtd_info *mtd,
156 const struct nand_data_interface *conf,
157 bool check_only);
155 158
156 /* 159 /*
157 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked 160 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
@@ -1012,6 +1015,82 @@ static void preset_v1(struct mtd_info *mtd)
1012 writew(0x4, NFC_V1_V2_WRPROT); 1015 writew(0x4, NFC_V1_V2_WRPROT);
1013} 1016}
1014 1017
1018static int mxc_nand_v2_setup_data_interface(struct mtd_info *mtd,
1019 const struct nand_data_interface *conf,
1020 bool check_only)
1021{
1022 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1023 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1024 int tRC_min_ns, tRC_ps, ret;
1025 unsigned long rate, rate_round;
1026 const struct nand_sdr_timings *timings;
1027 u16 config1;
1028
1029 timings = nand_get_sdr_timings(conf);
1030 if (IS_ERR(timings))
1031 return -ENOTSUPP;
1032
1033 config1 = readw(NFC_V1_V2_CONFIG1);
1034
1035 tRC_min_ns = timings->tRC_min / 1000;
1036 rate = 1000000000 / tRC_min_ns;
1037
1038 /*
1039 * For tRC < 30ns we have to use EDO mode. In this case the controller
1040 * does one access per clock cycle. Otherwise the controller does one
1041 * access in two clock cycles, thus we have to double the rate to the
1042 * controller.
1043 */
1044 if (tRC_min_ns < 30) {
1045 rate_round = clk_round_rate(host->clk, rate);
1046 config1 |= NFC_V2_CONFIG1_ONE_CYCLE;
1047 tRC_ps = 1000000000 / (rate_round / 1000);
1048 } else {
1049 rate *= 2;
1050 rate_round = clk_round_rate(host->clk, rate);
1051 config1 &= ~NFC_V2_CONFIG1_ONE_CYCLE;
1052 tRC_ps = 1000000000 / (rate_round / 1000 / 2);
1053 }
1054
1055 /*
1056 * The timing values compared against are from the i.MX25 Automotive
1057 * datasheet, Table 50. NFC Timing Parameters
1058 */
1059 if (timings->tCLS_min > tRC_ps - 1000 ||
1060 timings->tCLH_min > tRC_ps - 2000 ||
1061 timings->tCS_min > tRC_ps - 1000 ||
1062 timings->tCH_min > tRC_ps - 2000 ||
1063 timings->tWP_min > tRC_ps - 1500 ||
1064 timings->tALS_min > tRC_ps ||
1065 timings->tALH_min > tRC_ps - 3000 ||
1066 timings->tDS_min > tRC_ps ||
1067 timings->tDH_min > tRC_ps - 5000 ||
1068 timings->tWC_min > 2 * tRC_ps ||
1069 timings->tWH_min > tRC_ps - 2500 ||
1070 timings->tRR_min > 6 * tRC_ps ||
1071 timings->tRP_min > 3 * tRC_ps / 2 ||
1072 timings->tRC_min > 2 * tRC_ps ||
1073 timings->tREH_min > (tRC_ps / 2) - 2500) {
1074 dev_dbg(host->dev, "Timing out of bounds\n");
1075 return -EINVAL;
1076 }
1077
1078 if (check_only)
1079 return 0;
1080
1081 ret = clk_set_rate(host->clk, rate);
1082 if (ret)
1083 return ret;
1084
1085 writew(config1, NFC_V1_V2_CONFIG1);
1086
1087 dev_dbg(host->dev, "Setting rate to %ldHz, %s mode\n", rate_round,
1088 config1 & NFC_V2_CONFIG1_ONE_CYCLE ? "One cycle (EDO)" :
1089 "normal");
1090
1091 return 0;
1092}
1093
1015static void preset_v2(struct mtd_info *mtd) 1094static void preset_v2(struct mtd_info *mtd)
1016{ 1095{
1017 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1096 struct nand_chip *nand_chip = mtd_to_nand(mtd);
@@ -1239,6 +1318,57 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1239 } 1318 }
1240} 1319}
1241 1320
1321static int mxc_nand_onfi_set_features(struct mtd_info *mtd,
1322 struct nand_chip *chip, int addr,
1323 u8 *subfeature_param)
1324{
1325 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1326 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1327 int i;
1328
1329 if (!chip->onfi_version ||
1330 !(le16_to_cpu(chip->onfi_params.opt_cmd)
1331 & ONFI_OPT_CMD_SET_GET_FEATURES))
1332 return -EINVAL;
1333
1334 host->buf_start = 0;
1335
1336 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1337 chip->write_byte(mtd, subfeature_param[i]);
1338
1339 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1340 host->devtype_data->send_cmd(host, NAND_CMD_SET_FEATURES, false);
1341 mxc_do_addr_cycle(mtd, addr, -1);
1342 host->devtype_data->send_page(mtd, NFC_INPUT);
1343
1344 return 0;
1345}
1346
1347static int mxc_nand_onfi_get_features(struct mtd_info *mtd,
1348 struct nand_chip *chip, int addr,
1349 u8 *subfeature_param)
1350{
1351 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1352 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1353 int i;
1354
1355 if (!chip->onfi_version ||
1356 !(le16_to_cpu(chip->onfi_params.opt_cmd)
1357 & ONFI_OPT_CMD_SET_GET_FEATURES))
1358 return -EINVAL;
1359
1360 host->devtype_data->send_cmd(host, NAND_CMD_GET_FEATURES, false);
1361 mxc_do_addr_cycle(mtd, addr, -1);
1362 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1363 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1364 host->buf_start = 0;
1365
1366 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1367 *subfeature_param++ = chip->read_byte(mtd);
1368
1369 return 0;
1370}
1371
1242/* 1372/*
1243 * The generic flash bbt decriptors overlap with our ecc 1373 * The generic flash bbt decriptors overlap with our ecc
1244 * hardware, so define some i.MX specific ones. 1374 * hardware, so define some i.MX specific ones.
@@ -1327,6 +1457,7 @@ static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1327 .ooblayout = &mxc_v2_ooblayout_ops, 1457 .ooblayout = &mxc_v2_ooblayout_ops,
1328 .select_chip = mxc_nand_select_chip_v2, 1458 .select_chip = mxc_nand_select_chip_v2,
1329 .correct_data = mxc_nand_correct_data_v2_v3, 1459 .correct_data = mxc_nand_correct_data_v2_v3,
1460 .setup_data_interface = mxc_nand_v2_setup_data_interface,
1330 .irqpending_quirk = 0, 1461 .irqpending_quirk = 0,
1331 .needs_ip = 0, 1462 .needs_ip = 0,
1332 .regs_offset = 0x1e00, 1463 .regs_offset = 0x1e00,
@@ -1434,7 +1565,7 @@ static const struct platform_device_id mxcnd_devtype[] = {
1434}; 1565};
1435MODULE_DEVICE_TABLE(platform, mxcnd_devtype); 1566MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1436 1567
1437#ifdef CONFIG_OF_MTD 1568#ifdef CONFIG_OF
1438static const struct of_device_id mxcnd_dt_ids[] = { 1569static const struct of_device_id mxcnd_dt_ids[] = {
1439 { 1570 {
1440 .compatible = "fsl,imx21-nand", 1571 .compatible = "fsl,imx21-nand",
@@ -1513,6 +1644,8 @@ static int mxcnd_probe(struct platform_device *pdev)
1513 this->read_word = mxc_nand_read_word; 1644 this->read_word = mxc_nand_read_word;
1514 this->write_buf = mxc_nand_write_buf; 1645 this->write_buf = mxc_nand_write_buf;
1515 this->read_buf = mxc_nand_read_buf; 1646 this->read_buf = mxc_nand_read_buf;
1647 this->onfi_set_features = mxc_nand_onfi_set_features;
1648 this->onfi_get_features = mxc_nand_onfi_get_features;
1516 1649
1517 host->clk = devm_clk_get(&pdev->dev, NULL); 1650 host->clk = devm_clk_get(&pdev->dev, NULL);
1518 if (IS_ERR(host->clk)) 1651 if (IS_ERR(host->clk))
@@ -1533,6 +1666,8 @@ static int mxcnd_probe(struct platform_device *pdev)
1533 if (err < 0) 1666 if (err < 0)
1534 return err; 1667 return err;
1535 1668
1669 this->setup_data_interface = host->devtype_data->setup_data_interface;
1670
1536 if (host->devtype_data->needs_ip) { 1671 if (host->devtype_data->needs_ip) {
1537 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1672 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1538 host->regs_ip = devm_ioremap_resource(&pdev->dev, res); 1673 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 77533f7f2429..e5718e5ecf92 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -745,7 +745,10 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
745 column >>= 1; 745 column >>= 1;
746 chip->cmd_ctrl(mtd, column, ctrl); 746 chip->cmd_ctrl(mtd, column, ctrl);
747 ctrl &= ~NAND_CTRL_CHANGE; 747 ctrl &= ~NAND_CTRL_CHANGE;
748 chip->cmd_ctrl(mtd, column >> 8, ctrl); 748
749 /* Only output a single addr cycle for 8bits opcodes. */
750 if (!nand_opcode_8bits(command))
751 chip->cmd_ctrl(mtd, column >> 8, ctrl);
749 } 752 }
750 if (page_addr != -1) { 753 if (page_addr != -1) {
751 chip->cmd_ctrl(mtd, page_addr, ctrl); 754 chip->cmd_ctrl(mtd, page_addr, ctrl);
@@ -948,6 +951,172 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
948} 951}
949 952
950/** 953/**
954 * nand_reset_data_interface - Reset data interface and timings
955 * @chip: The NAND chip
956 *
957 * Reset the Data interface and timings to ONFI mode 0.
958 *
959 * Returns 0 for success or negative error code otherwise.
960 */
961static int nand_reset_data_interface(struct nand_chip *chip)
962{
963 struct mtd_info *mtd = nand_to_mtd(chip);
964 const struct nand_data_interface *conf;
965 int ret;
966
967 if (!chip->setup_data_interface)
968 return 0;
969
970 /*
971 * The ONFI specification says:
972 * "
973 * To transition from NV-DDR or NV-DDR2 to the SDR data
974 * interface, the host shall use the Reset (FFh) command
975 * using SDR timing mode 0. A device in any timing mode is
976 * required to recognize Reset (FFh) command issued in SDR
977 * timing mode 0.
978 * "
979 *
980 * Configure the data interface in SDR mode and set the
981 * timings to timing mode 0.
982 */
983
984 conf = nand_get_default_data_interface();
985 ret = chip->setup_data_interface(mtd, conf, false);
986 if (ret)
987 pr_err("Failed to configure data interface to SDR timing mode 0\n");
988
989 return ret;
990}
991
992/**
993 * nand_setup_data_interface - Setup the best data interface and timings
994 * @chip: The NAND chip
995 *
996 * Find and configure the best data interface and NAND timings supported by
997 * the chip and the driver.
998 * First tries to retrieve supported timing modes from ONFI information,
999 * and if the NAND chip does not support ONFI, relies on the
1000 * ->onfi_timing_mode_default specified in the nand_ids table.
1001 *
1002 * Returns 0 for success or negative error code otherwise.
1003 */
1004static int nand_setup_data_interface(struct nand_chip *chip)
1005{
1006 struct mtd_info *mtd = nand_to_mtd(chip);
1007 int ret;
1008
1009 if (!chip->setup_data_interface || !chip->data_interface)
1010 return 0;
1011
1012 /*
1013 * Ensure the timing mode has been changed on the chip side
1014 * before changing timings on the controller side.
1015 */
1016 if (chip->onfi_version) {
1017 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
1018 chip->onfi_timing_mode_default,
1019 };
1020
1021 ret = chip->onfi_set_features(mtd, chip,
1022 ONFI_FEATURE_ADDR_TIMING_MODE,
1023 tmode_param);
1024 if (ret)
1025 goto err;
1026 }
1027
1028 ret = chip->setup_data_interface(mtd, chip->data_interface, false);
1029err:
1030 return ret;
1031}
1032
1033/**
1034 * nand_init_data_interface - find the best data interface and timings
1035 * @chip: The NAND chip
1036 *
1037 * Find the best data interface and NAND timings supported by the chip
1038 * and the driver.
1039 * First tries to retrieve supported timing modes from ONFI information,
1040 * and if the NAND chip does not support ONFI, relies on the
1041 * ->onfi_timing_mode_default specified in the nand_ids table. After this
1042 * function nand_chip->data_interface is initialized with the best timing mode
1043 * available.
1044 *
1045 * Returns 0 for success or negative error code otherwise.
1046 */
1047static int nand_init_data_interface(struct nand_chip *chip)
1048{
1049 struct mtd_info *mtd = nand_to_mtd(chip);
1050 int modes, mode, ret;
1051
1052 if (!chip->setup_data_interface)
1053 return 0;
1054
1055 /*
1056 * First try to identify the best timings from ONFI parameters and
1057 * if the NAND does not support ONFI, fallback to the default ONFI
1058 * timing mode.
1059 */
1060 modes = onfi_get_async_timing_mode(chip);
1061 if (modes == ONFI_TIMING_MODE_UNKNOWN) {
1062 if (!chip->onfi_timing_mode_default)
1063 return 0;
1064
1065 modes = GENMASK(chip->onfi_timing_mode_default, 0);
1066 }
1067
1068 chip->data_interface = kzalloc(sizeof(*chip->data_interface),
1069 GFP_KERNEL);
1070 if (!chip->data_interface)
1071 return -ENOMEM;
1072
1073 for (mode = fls(modes) - 1; mode >= 0; mode--) {
1074 ret = onfi_init_data_interface(chip, chip->data_interface,
1075 NAND_SDR_IFACE, mode);
1076 if (ret)
1077 continue;
1078
1079 ret = chip->setup_data_interface(mtd, chip->data_interface,
1080 true);
1081 if (!ret) {
1082 chip->onfi_timing_mode_default = mode;
1083 break;
1084 }
1085 }
1086
1087 return 0;
1088}
1089
1090static void nand_release_data_interface(struct nand_chip *chip)
1091{
1092 kfree(chip->data_interface);
1093}
1094
1095/**
1096 * nand_reset - Reset and initialize a NAND device
1097 * @chip: The NAND chip
1098 *
1099 * Returns 0 for success or negative error code otherwise
1100 */
1101int nand_reset(struct nand_chip *chip)
1102{
1103 struct mtd_info *mtd = nand_to_mtd(chip);
1104 int ret;
1105
1106 ret = nand_reset_data_interface(chip);
1107 if (ret)
1108 return ret;
1109
1110 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1111
1112 ret = nand_setup_data_interface(chip);
1113 if (ret)
1114 return ret;
1115
1116 return 0;
1117}
1118
1119/**
951 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks 1120 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
952 * @mtd: mtd info 1121 * @mtd: mtd info
953 * @ofs: offset to start unlock from 1122 * @ofs: offset to start unlock from
@@ -1025,7 +1194,7 @@ int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1025 * some operation can also clear the bit 7 of status register 1194 * some operation can also clear the bit 7 of status register
1026 * eg. erase/program a locked block 1195 * eg. erase/program a locked block
1027 */ 1196 */
1028 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 1197 nand_reset(chip);
1029 1198
1030 /* Check, if it is write protected */ 1199 /* Check, if it is write protected */
1031 if (nand_check_wp(mtd)) { 1200 if (nand_check_wp(mtd)) {
@@ -1084,7 +1253,7 @@ int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1084 * some operation can also clear the bit 7 of status register 1253 * some operation can also clear the bit 7 of status register
1085 * eg. erase/program a locked block 1254 * eg. erase/program a locked block
1086 */ 1255 */
1087 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 1256 nand_reset(chip);
1088 1257
1089 /* Check, if it is write protected */ 1258 /* Check, if it is write protected */
1090 if (nand_check_wp(mtd)) { 1259 if (nand_check_wp(mtd)) {
@@ -2162,7 +2331,7 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2162static int nand_read_oob(struct mtd_info *mtd, loff_t from, 2331static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2163 struct mtd_oob_ops *ops) 2332 struct mtd_oob_ops *ops)
2164{ 2333{
2165 int ret = -ENOTSUPP; 2334 int ret;
2166 2335
2167 ops->retlen = 0; 2336 ops->retlen = 0;
2168 2337
@@ -2173,24 +2342,18 @@ static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2173 return -EINVAL; 2342 return -EINVAL;
2174 } 2343 }
2175 2344
2176 nand_get_device(mtd, FL_READING); 2345 if (ops->mode != MTD_OPS_PLACE_OOB &&
2177 2346 ops->mode != MTD_OPS_AUTO_OOB &&
2178 switch (ops->mode) { 2347 ops->mode != MTD_OPS_RAW)
2179 case MTD_OPS_PLACE_OOB: 2348 return -ENOTSUPP;
2180 case MTD_OPS_AUTO_OOB:
2181 case MTD_OPS_RAW:
2182 break;
2183 2349
2184 default: 2350 nand_get_device(mtd, FL_READING);
2185 goto out;
2186 }
2187 2351
2188 if (!ops->datbuf) 2352 if (!ops->datbuf)
2189 ret = nand_do_read_oob(mtd, from, ops); 2353 ret = nand_do_read_oob(mtd, from, ops);
2190 else 2354 else
2191 ret = nand_do_read_ops(mtd, from, ops); 2355 ret = nand_do_read_ops(mtd, from, ops);
2192 2356
2193out:
2194 nand_release_device(mtd); 2357 nand_release_device(mtd);
2195 return ret; 2358 return ret;
2196} 2359}
@@ -2788,7 +2951,7 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2788 * if we don't do this. I have no clue why, but I seem to have 'fixed' 2951 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2789 * it in the doc2000 driver in August 1999. dwmw2. 2952 * it in the doc2000 driver in August 1999. dwmw2.
2790 */ 2953 */
2791 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 2954 nand_reset(chip);
2792 2955
2793 /* Check, if it is write protected */ 2956 /* Check, if it is write protected */
2794 if (nand_check_wp(mtd)) { 2957 if (nand_check_wp(mtd)) {
@@ -3191,8 +3354,7 @@ static void nand_set_defaults(struct nand_chip *chip, int busw)
3191 3354
3192 if (!chip->controller) { 3355 if (!chip->controller) {
3193 chip->controller = &chip->hwcontrol; 3356 chip->controller = &chip->hwcontrol;
3194 spin_lock_init(&chip->controller->lock); 3357 nand_hw_control_init(chip->controller);
3195 init_waitqueue_head(&chip->controller->wq);
3196 } 3358 }
3197 3359
3198} 3360}
@@ -3829,7 +3991,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3829 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) 3991 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3830 * after power-up. 3992 * after power-up.
3831 */ 3993 */
3832 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 3994 nand_reset(chip);
3833 3995
3834 /* Send the command for reading device ID */ 3996 /* Send the command for reading device ID */
3835 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 3997 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
@@ -4113,6 +4275,9 @@ static int nand_dt_init(struct nand_chip *chip)
4113 if (ecc_step > 0) 4275 if (ecc_step > 0)
4114 chip->ecc.size = ecc_step; 4276 chip->ecc.size = ecc_step;
4115 4277
4278 if (of_property_read_bool(dn, "nand-ecc-maximize"))
4279 chip->ecc.options |= NAND_ECC_MAXIMIZE;
4280
4116 return 0; 4281 return 0;
4117} 4282}
4118 4283
@@ -4141,6 +4306,15 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips,
4141 if (!mtd->name && mtd->dev.parent) 4306 if (!mtd->name && mtd->dev.parent)
4142 mtd->name = dev_name(mtd->dev.parent); 4307 mtd->name = dev_name(mtd->dev.parent);
4143 4308
4309 if ((!chip->cmdfunc || !chip->select_chip) && !chip->cmd_ctrl) {
4310 /*
4311 * Default functions assigned for chip_select() and
4312 * cmdfunc() both expect cmd_ctrl() to be populated,
4313 * so we need to check that that's the case
4314 */
4315 pr_err("chip.cmd_ctrl() callback is not provided");
4316 return -EINVAL;
4317 }
4144 /* Set the default functions */ 4318 /* Set the default functions */
4145 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); 4319 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
4146 4320
@@ -4155,13 +4329,17 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips,
4155 return PTR_ERR(type); 4329 return PTR_ERR(type);
4156 } 4330 }
4157 4331
4332 ret = nand_init_data_interface(chip);
4333 if (ret)
4334 return ret;
4335
4158 chip->select_chip(mtd, -1); 4336 chip->select_chip(mtd, -1);
4159 4337
4160 /* Check for a chip array */ 4338 /* Check for a chip array */
4161 for (i = 1; i < maxchips; i++) { 4339 for (i = 1; i < maxchips; i++) {
4162 chip->select_chip(mtd, i); 4340 chip->select_chip(mtd, i);
4163 /* See comment in nand_get_flash_type for reset */ 4341 /* See comment in nand_get_flash_type for reset */
4164 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 4342 nand_reset(chip);
4165 /* Send the command for reading device ID */ 4343 /* Send the command for reading device ID */
4166 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 4344 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4167 /* Read manufacturer and device IDs */ 4345 /* Read manufacturer and device IDs */
@@ -4221,6 +4399,7 @@ static int nand_set_ecc_soft_ops(struct mtd_info *mtd)
4221 ecc->write_page_raw = nand_write_page_raw; 4399 ecc->write_page_raw = nand_write_page_raw;
4222 ecc->read_oob = nand_read_oob_std; 4400 ecc->read_oob = nand_read_oob_std;
4223 ecc->write_oob = nand_write_oob_std; 4401 ecc->write_oob = nand_write_oob_std;
4402
4224 /* 4403 /*
4225 * Board driver should supply ecc.size and ecc.strength 4404 * Board driver should supply ecc.size and ecc.strength
4226 * values to select how many bits are correctable. 4405 * values to select how many bits are correctable.
@@ -4243,6 +4422,25 @@ static int nand_set_ecc_soft_ops(struct mtd_info *mtd)
4243 } 4422 }
4244 4423
4245 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); 4424 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
4425
4426 }
4427
4428 /*
4429 * We can only maximize ECC config when the default layout is
4430 * used, otherwise we don't know how many bytes can really be
4431 * used.
4432 */
4433 if (mtd->ooblayout == &nand_ooblayout_lp_ops &&
4434 ecc->options & NAND_ECC_MAXIMIZE) {
4435 int steps, bytes;
4436
4437 /* Always prefer 1k blocks over 512bytes ones */
4438 ecc->size = 1024;
4439 steps = mtd->writesize / ecc->size;
4440
4441 /* Reserve 2 bytes for the BBM */
4442 bytes = (mtd->oobsize - 2) / steps;
4443 ecc->strength = bytes * 8 / fls(8 * ecc->size);
4246 } 4444 }
4247 4445
4248 /* See nand_bch_init() for details. */ 4446 /* See nand_bch_init() for details. */
@@ -4601,18 +4799,16 @@ int nand_scan(struct mtd_info *mtd, int maxchips)
4601EXPORT_SYMBOL(nand_scan); 4799EXPORT_SYMBOL(nand_scan);
4602 4800
4603/** 4801/**
4604 * nand_release - [NAND Interface] Free resources held by the NAND device 4802 * nand_cleanup - [NAND Interface] Free resources held by the NAND device
4605 * @mtd: MTD device structure 4803 * @chip: NAND chip object
4606 */ 4804 */
4607void nand_release(struct mtd_info *mtd) 4805void nand_cleanup(struct nand_chip *chip)
4608{ 4806{
4609 struct nand_chip *chip = mtd_to_nand(mtd);
4610
4611 if (chip->ecc.mode == NAND_ECC_SOFT && 4807 if (chip->ecc.mode == NAND_ECC_SOFT &&
4612 chip->ecc.algo == NAND_ECC_BCH) 4808 chip->ecc.algo == NAND_ECC_BCH)
4613 nand_bch_free((struct nand_bch_control *)chip->ecc.priv); 4809 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4614 4810
4615 mtd_device_unregister(mtd); 4811 nand_release_data_interface(chip);
4616 4812
4617 /* Free bad block table memory */ 4813 /* Free bad block table memory */
4618 kfree(chip->bbt); 4814 kfree(chip->bbt);
@@ -4624,6 +4820,18 @@ void nand_release(struct mtd_info *mtd)
4624 & NAND_BBT_DYNAMICSTRUCT) 4820 & NAND_BBT_DYNAMICSTRUCT)
4625 kfree(chip->badblock_pattern); 4821 kfree(chip->badblock_pattern);
4626} 4822}
4823EXPORT_SYMBOL_GPL(nand_cleanup);
4824
4825/**
4826 * nand_release - [NAND Interface] Unregister the MTD device and free resources
4827 * held by the NAND device
4828 * @mtd: MTD device structure
4829 */
4830void nand_release(struct mtd_info *mtd)
4831{
4832 mtd_device_unregister(mtd);
4833 nand_cleanup(mtd_to_nand(mtd));
4834}
4627EXPORT_SYMBOL_GPL(nand_release); 4835EXPORT_SYMBOL_GPL(nand_release);
4628 4836
4629MODULE_LICENSE("GPL"); 4837MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 2fbb523df066..7695efea65f2 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -605,6 +605,100 @@ static void search_read_bbts(struct mtd_info *mtd, uint8_t *buf,
605} 605}
606 606
607/** 607/**
608 * get_bbt_block - Get the first valid eraseblock suitable to store a BBT
609 * @this: the NAND device
610 * @td: the BBT description
611 * @md: the mirror BBT descriptor
612 * @chip: the CHIP selector
613 *
614 * This functions returns a positive block number pointing a valid eraseblock
615 * suitable to store a BBT (i.e. in the range reserved for BBT), or -ENOSPC if
616 * all blocks are already used of marked bad. If td->pages[chip] was already
617 * pointing to a valid block we re-use it, otherwise we search for the next
618 * valid one.
619 */
620static int get_bbt_block(struct nand_chip *this, struct nand_bbt_descr *td,
621 struct nand_bbt_descr *md, int chip)
622{
623 int startblock, dir, page, numblocks, i;
624
625 /*
626 * There was already a version of the table, reuse the page. This
627 * applies for absolute placement too, as we have the page number in
628 * td->pages.
629 */
630 if (td->pages[chip] != -1)
631 return td->pages[chip] >>
632 (this->bbt_erase_shift - this->page_shift);
633
634 numblocks = (int)(this->chipsize >> this->bbt_erase_shift);
635 if (!(td->options & NAND_BBT_PERCHIP))
636 numblocks *= this->numchips;
637
638 /*
639 * Automatic placement of the bad block table. Search direction
640 * top -> down?
641 */
642 if (td->options & NAND_BBT_LASTBLOCK) {
643 startblock = numblocks * (chip + 1) - 1;
644 dir = -1;
645 } else {
646 startblock = chip * numblocks;
647 dir = 1;
648 }
649
650 for (i = 0; i < td->maxblocks; i++) {
651 int block = startblock + dir * i;
652
653 /* Check, if the block is bad */
654 switch (bbt_get_entry(this, block)) {
655 case BBT_BLOCK_WORN:
656 case BBT_BLOCK_FACTORY_BAD:
657 continue;
658 }
659
660 page = block << (this->bbt_erase_shift - this->page_shift);
661
662 /* Check, if the block is used by the mirror table */
663 if (!md || md->pages[chip] != page)
664 return block;
665 }
666
667 return -ENOSPC;
668}
669
670/**
671 * mark_bbt_block_bad - Mark one of the block reserved for BBT bad
672 * @this: the NAND device
673 * @td: the BBT description
674 * @chip: the CHIP selector
675 * @block: the BBT block to mark
676 *
677 * Blocks reserved for BBT can become bad. This functions is an helper to mark
678 * such blocks as bad. It takes care of updating the in-memory BBT, marking the
679 * block as bad using a bad block marker and invalidating the associated
680 * td->pages[] entry.
681 */
682static void mark_bbt_block_bad(struct nand_chip *this,
683 struct nand_bbt_descr *td,
684 int chip, int block)
685{
686 struct mtd_info *mtd = nand_to_mtd(this);
687 loff_t to;
688 int res;
689
690 bbt_mark_entry(this, block, BBT_BLOCK_WORN);
691
692 to = (loff_t)block << this->bbt_erase_shift;
693 res = this->block_markbad(mtd, to);
694 if (res)
695 pr_warn("nand_bbt: error %d while marking block %d bad\n",
696 res, block);
697
698 td->pages[chip] = -1;
699}
700
701/**
608 * write_bbt - [GENERIC] (Re)write the bad block table 702 * write_bbt - [GENERIC] (Re)write the bad block table
609 * @mtd: MTD device structure 703 * @mtd: MTD device structure
610 * @buf: temporary buffer 704 * @buf: temporary buffer
@@ -621,7 +715,7 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
621 struct nand_chip *this = mtd_to_nand(mtd); 715 struct nand_chip *this = mtd_to_nand(mtd);
622 struct erase_info einfo; 716 struct erase_info einfo;
623 int i, res, chip = 0; 717 int i, res, chip = 0;
624 int bits, startblock, dir, page, offs, numblocks, sft, sftmsk; 718 int bits, page, offs, numblocks, sft, sftmsk;
625 int nrchips, pageoffs, ooboffs; 719 int nrchips, pageoffs, ooboffs;
626 uint8_t msk[4]; 720 uint8_t msk[4];
627 uint8_t rcode = td->reserved_block_code; 721 uint8_t rcode = td->reserved_block_code;
@@ -652,46 +746,21 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
652 } 746 }
653 747
654 /* Loop through the chips */ 748 /* Loop through the chips */
655 for (; chip < nrchips; chip++) { 749 while (chip < nrchips) {
656 /* 750 int block;
657 * There was already a version of the table, reuse the page 751
658 * This applies for absolute placement too, as we have the 752 block = get_bbt_block(this, td, md, chip);
659 * page nr. in td->pages. 753 if (block < 0) {
660 */ 754 pr_err("No space left to write bad block table\n");
661 if (td->pages[chip] != -1) { 755 res = block;
662 page = td->pages[chip]; 756 goto outerr;
663 goto write;
664 } 757 }
665 758
666 /* 759 /*
667 * Automatic placement of the bad block table. Search direction 760 * get_bbt_block() returns a block number, shift the value to
668 * top -> down? 761 * get a page number.
669 */ 762 */
670 if (td->options & NAND_BBT_LASTBLOCK) { 763 page = block << (this->bbt_erase_shift - this->page_shift);
671 startblock = numblocks * (chip + 1) - 1;
672 dir = -1;
673 } else {
674 startblock = chip * numblocks;
675 dir = 1;
676 }
677
678 for (i = 0; i < td->maxblocks; i++) {
679 int block = startblock + dir * i;
680 /* Check, if the block is bad */
681 switch (bbt_get_entry(this, block)) {
682 case BBT_BLOCK_WORN:
683 case BBT_BLOCK_FACTORY_BAD:
684 continue;
685 }
686 page = block <<
687 (this->bbt_erase_shift - this->page_shift);
688 /* Check, if the block is used by the mirror table */
689 if (!md || md->pages[chip] != page)
690 goto write;
691 }
692 pr_err("No space left to write bad block table\n");
693 return -ENOSPC;
694 write:
695 764
696 /* Set up shift count and masks for the flash table */ 765 /* Set up shift count and masks for the flash table */
697 bits = td->options & NAND_BBT_NRBITS_MSK; 766 bits = td->options & NAND_BBT_NRBITS_MSK;
@@ -787,20 +856,28 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
787 einfo.addr = to; 856 einfo.addr = to;
788 einfo.len = 1 << this->bbt_erase_shift; 857 einfo.len = 1 << this->bbt_erase_shift;
789 res = nand_erase_nand(mtd, &einfo, 1); 858 res = nand_erase_nand(mtd, &einfo, 1);
790 if (res < 0) 859 if (res < 0) {
791 goto outerr; 860 pr_warn("nand_bbt: error while erasing BBT block %d\n",
861 res);
862 mark_bbt_block_bad(this, td, chip, block);
863 continue;
864 }
792 865
793 res = scan_write_bbt(mtd, to, len, buf, 866 res = scan_write_bbt(mtd, to, len, buf,
794 td->options & NAND_BBT_NO_OOB ? NULL : 867 td->options & NAND_BBT_NO_OOB ? NULL :
795 &buf[len]); 868 &buf[len]);
796 if (res < 0) 869 if (res < 0) {
797 goto outerr; 870 pr_warn("nand_bbt: error while writing BBT block %d\n",
871 res);
872 mark_bbt_block_bad(this, td, chip, block);
873 continue;
874 }
798 875
799 pr_info("Bad block table written to 0x%012llx, version 0x%02X\n", 876 pr_info("Bad block table written to 0x%012llx, version 0x%02X\n",
800 (unsigned long long)to, td->version[chip]); 877 (unsigned long long)to, td->version[chip]);
801 878
802 /* Mark it as used */ 879 /* Mark it as used */
803 td->pages[chip] = page; 880 td->pages[chip++] = page;
804 } 881 }
805 return 0; 882 return 0;
806 883
diff --git a/drivers/mtd/nand/nand_timings.c b/drivers/mtd/nand/nand_timings.c
index e81470a8ac67..13a587407be3 100644
--- a/drivers/mtd/nand/nand_timings.c
+++ b/drivers/mtd/nand/nand_timings.c
@@ -13,228 +13,246 @@
13#include <linux/export.h> 13#include <linux/export.h>
14#include <linux/mtd/nand.h> 14#include <linux/mtd/nand.h>
15 15
16static const struct nand_sdr_timings onfi_sdr_timings[] = { 16static const struct nand_data_interface onfi_sdr_timings[] = {
17 /* Mode 0 */ 17 /* Mode 0 */
18 { 18 {
19 .tADL_min = 200000, 19 .type = NAND_SDR_IFACE,
20 .tALH_min = 20000, 20 .timings.sdr = {
21 .tALS_min = 50000, 21 .tADL_min = 400000,
22 .tAR_min = 25000, 22 .tALH_min = 20000,
23 .tCEA_max = 100000, 23 .tALS_min = 50000,
24 .tCEH_min = 20000, 24 .tAR_min = 25000,
25 .tCH_min = 20000, 25 .tCEA_max = 100000,
26 .tCHZ_max = 100000, 26 .tCEH_min = 20000,
27 .tCLH_min = 20000, 27 .tCH_min = 20000,
28 .tCLR_min = 20000, 28 .tCHZ_max = 100000,
29 .tCLS_min = 50000, 29 .tCLH_min = 20000,
30 .tCOH_min = 0, 30 .tCLR_min = 20000,
31 .tCS_min = 70000, 31 .tCLS_min = 50000,
32 .tDH_min = 20000, 32 .tCOH_min = 0,
33 .tDS_min = 40000, 33 .tCS_min = 70000,
34 .tFEAT_max = 1000000, 34 .tDH_min = 20000,
35 .tIR_min = 10000, 35 .tDS_min = 40000,
36 .tITC_max = 1000000, 36 .tFEAT_max = 1000000,
37 .tRC_min = 100000, 37 .tIR_min = 10000,
38 .tREA_max = 40000, 38 .tITC_max = 1000000,
39 .tREH_min = 30000, 39 .tRC_min = 100000,
40 .tRHOH_min = 0, 40 .tREA_max = 40000,
41 .tRHW_min = 200000, 41 .tREH_min = 30000,
42 .tRHZ_max = 200000, 42 .tRHOH_min = 0,
43 .tRLOH_min = 0, 43 .tRHW_min = 200000,
44 .tRP_min = 50000, 44 .tRHZ_max = 200000,
45 .tRST_max = 250000000000ULL, 45 .tRLOH_min = 0,
46 .tWB_max = 200000, 46 .tRP_min = 50000,
47 .tRR_min = 40000, 47 .tRR_min = 40000,
48 .tWC_min = 100000, 48 .tRST_max = 250000000000ULL,
49 .tWH_min = 30000, 49 .tWB_max = 200000,
50 .tWHR_min = 120000, 50 .tWC_min = 100000,
51 .tWP_min = 50000, 51 .tWH_min = 30000,
52 .tWW_min = 100000, 52 .tWHR_min = 120000,
53 .tWP_min = 50000,
54 .tWW_min = 100000,
55 },
53 }, 56 },
54 /* Mode 1 */ 57 /* Mode 1 */
55 { 58 {
56 .tADL_min = 100000, 59 .type = NAND_SDR_IFACE,
57 .tALH_min = 10000, 60 .timings.sdr = {
58 .tALS_min = 25000, 61 .tADL_min = 400000,
59 .tAR_min = 10000, 62 .tALH_min = 10000,
60 .tCEA_max = 45000, 63 .tALS_min = 25000,
61 .tCEH_min = 20000, 64 .tAR_min = 10000,
62 .tCH_min = 10000, 65 .tCEA_max = 45000,
63 .tCHZ_max = 50000, 66 .tCEH_min = 20000,
64 .tCLH_min = 10000, 67 .tCH_min = 10000,
65 .tCLR_min = 10000, 68 .tCHZ_max = 50000,
66 .tCLS_min = 25000, 69 .tCLH_min = 10000,
67 .tCOH_min = 15000, 70 .tCLR_min = 10000,
68 .tCS_min = 35000, 71 .tCLS_min = 25000,
69 .tDH_min = 10000, 72 .tCOH_min = 15000,
70 .tDS_min = 20000, 73 .tCS_min = 35000,
71 .tFEAT_max = 1000000, 74 .tDH_min = 10000,
72 .tIR_min = 0, 75 .tDS_min = 20000,
73 .tITC_max = 1000000, 76 .tFEAT_max = 1000000,
74 .tRC_min = 50000, 77 .tIR_min = 0,
75 .tREA_max = 30000, 78 .tITC_max = 1000000,
76 .tREH_min = 15000, 79 .tRC_min = 50000,
77 .tRHOH_min = 15000, 80 .tREA_max = 30000,
78 .tRHW_min = 100000, 81 .tREH_min = 15000,
79 .tRHZ_max = 100000, 82 .tRHOH_min = 15000,
80 .tRLOH_min = 0, 83 .tRHW_min = 100000,
81 .tRP_min = 25000, 84 .tRHZ_max = 100000,
82 .tRR_min = 20000, 85 .tRLOH_min = 0,
83 .tRST_max = 500000000, 86 .tRP_min = 25000,
84 .tWB_max = 100000, 87 .tRR_min = 20000,
85 .tWC_min = 45000, 88 .tRST_max = 500000000,
86 .tWH_min = 15000, 89 .tWB_max = 100000,
87 .tWHR_min = 80000, 90 .tWC_min = 45000,
88 .tWP_min = 25000, 91 .tWH_min = 15000,
89 .tWW_min = 100000, 92 .tWHR_min = 80000,
93 .tWP_min = 25000,
94 .tWW_min = 100000,
95 },
90 }, 96 },
91 /* Mode 2 */ 97 /* Mode 2 */
92 { 98 {
93 .tADL_min = 100000, 99 .type = NAND_SDR_IFACE,
94 .tALH_min = 10000, 100 .timings.sdr = {
95 .tALS_min = 15000, 101 .tADL_min = 400000,
96 .tAR_min = 10000, 102 .tALH_min = 10000,
97 .tCEA_max = 30000, 103 .tALS_min = 15000,
98 .tCEH_min = 20000, 104 .tAR_min = 10000,
99 .tCH_min = 10000, 105 .tCEA_max = 30000,
100 .tCHZ_max = 50000, 106 .tCEH_min = 20000,
101 .tCLH_min = 10000, 107 .tCH_min = 10000,
102 .tCLR_min = 10000, 108 .tCHZ_max = 50000,
103 .tCLS_min = 15000, 109 .tCLH_min = 10000,
104 .tCOH_min = 15000, 110 .tCLR_min = 10000,
105 .tCS_min = 25000, 111 .tCLS_min = 15000,
106 .tDH_min = 5000, 112 .tCOH_min = 15000,
107 .tDS_min = 15000, 113 .tCS_min = 25000,
108 .tFEAT_max = 1000000, 114 .tDH_min = 5000,
109 .tIR_min = 0, 115 .tDS_min = 15000,
110 .tITC_max = 1000000, 116 .tFEAT_max = 1000000,
111 .tRC_min = 35000, 117 .tIR_min = 0,
112 .tREA_max = 25000, 118 .tITC_max = 1000000,
113 .tREH_min = 15000, 119 .tRC_min = 35000,
114 .tRHOH_min = 15000, 120 .tREA_max = 25000,
115 .tRHW_min = 100000, 121 .tREH_min = 15000,
116 .tRHZ_max = 100000, 122 .tRHOH_min = 15000,
117 .tRLOH_min = 0, 123 .tRHW_min = 100000,
118 .tRR_min = 20000, 124 .tRHZ_max = 100000,
119 .tRST_max = 500000000, 125 .tRLOH_min = 0,
120 .tWB_max = 100000, 126 .tRR_min = 20000,
121 .tRP_min = 17000, 127 .tRST_max = 500000000,
122 .tWC_min = 35000, 128 .tWB_max = 100000,
123 .tWH_min = 15000, 129 .tRP_min = 17000,
124 .tWHR_min = 80000, 130 .tWC_min = 35000,
125 .tWP_min = 17000, 131 .tWH_min = 15000,
126 .tWW_min = 100000, 132 .tWHR_min = 80000,
133 .tWP_min = 17000,
134 .tWW_min = 100000,
135 },
127 }, 136 },
128 /* Mode 3 */ 137 /* Mode 3 */
129 { 138 {
130 .tADL_min = 100000, 139 .type = NAND_SDR_IFACE,
131 .tALH_min = 5000, 140 .timings.sdr = {
132 .tALS_min = 10000, 141 .tADL_min = 400000,
133 .tAR_min = 10000, 142 .tALH_min = 5000,
134 .tCEA_max = 25000, 143 .tALS_min = 10000,
135 .tCEH_min = 20000, 144 .tAR_min = 10000,
136 .tCH_min = 5000, 145 .tCEA_max = 25000,
137 .tCHZ_max = 50000, 146 .tCEH_min = 20000,
138 .tCLH_min = 5000, 147 .tCH_min = 5000,
139 .tCLR_min = 10000, 148 .tCHZ_max = 50000,
140 .tCLS_min = 10000, 149 .tCLH_min = 5000,
141 .tCOH_min = 15000, 150 .tCLR_min = 10000,
142 .tCS_min = 25000, 151 .tCLS_min = 10000,
143 .tDH_min = 5000, 152 .tCOH_min = 15000,
144 .tDS_min = 10000, 153 .tCS_min = 25000,
145 .tFEAT_max = 1000000, 154 .tDH_min = 5000,
146 .tIR_min = 0, 155 .tDS_min = 10000,
147 .tITC_max = 1000000, 156 .tFEAT_max = 1000000,
148 .tRC_min = 30000, 157 .tIR_min = 0,
149 .tREA_max = 20000, 158 .tITC_max = 1000000,
150 .tREH_min = 10000, 159 .tRC_min = 30000,
151 .tRHOH_min = 15000, 160 .tREA_max = 20000,
152 .tRHW_min = 100000, 161 .tREH_min = 10000,
153 .tRHZ_max = 100000, 162 .tRHOH_min = 15000,
154 .tRLOH_min = 0, 163 .tRHW_min = 100000,
155 .tRP_min = 15000, 164 .tRHZ_max = 100000,
156 .tRR_min = 20000, 165 .tRLOH_min = 0,
157 .tRST_max = 500000000, 166 .tRP_min = 15000,
158 .tWB_max = 100000, 167 .tRR_min = 20000,
159 .tWC_min = 30000, 168 .tRST_max = 500000000,
160 .tWH_min = 10000, 169 .tWB_max = 100000,
161 .tWHR_min = 80000, 170 .tWC_min = 30000,
162 .tWP_min = 15000, 171 .tWH_min = 10000,
163 .tWW_min = 100000, 172 .tWHR_min = 80000,
173 .tWP_min = 15000,
174 .tWW_min = 100000,
175 },
164 }, 176 },
165 /* Mode 4 */ 177 /* Mode 4 */
166 { 178 {
167 .tADL_min = 70000, 179 .type = NAND_SDR_IFACE,
168 .tALH_min = 5000, 180 .timings.sdr = {
169 .tALS_min = 10000, 181 .tADL_min = 400000,
170 .tAR_min = 10000, 182 .tALH_min = 5000,
171 .tCEA_max = 25000, 183 .tALS_min = 10000,
172 .tCEH_min = 20000, 184 .tAR_min = 10000,
173 .tCH_min = 5000, 185 .tCEA_max = 25000,
174 .tCHZ_max = 30000, 186 .tCEH_min = 20000,
175 .tCLH_min = 5000, 187 .tCH_min = 5000,
176 .tCLR_min = 10000, 188 .tCHZ_max = 30000,
177 .tCLS_min = 10000, 189 .tCLH_min = 5000,
178 .tCOH_min = 15000, 190 .tCLR_min = 10000,
179 .tCS_min = 20000, 191 .tCLS_min = 10000,
180 .tDH_min = 5000, 192 .tCOH_min = 15000,
181 .tDS_min = 10000, 193 .tCS_min = 20000,
182 .tFEAT_max = 1000000, 194 .tDH_min = 5000,
183 .tIR_min = 0, 195 .tDS_min = 10000,
184 .tITC_max = 1000000, 196 .tFEAT_max = 1000000,
185 .tRC_min = 25000, 197 .tIR_min = 0,
186 .tREA_max = 20000, 198 .tITC_max = 1000000,
187 .tREH_min = 10000, 199 .tRC_min = 25000,
188 .tRHOH_min = 15000, 200 .tREA_max = 20000,
189 .tRHW_min = 100000, 201 .tREH_min = 10000,
190 .tRHZ_max = 100000, 202 .tRHOH_min = 15000,
191 .tRLOH_min = 5000, 203 .tRHW_min = 100000,
192 .tRP_min = 12000, 204 .tRHZ_max = 100000,
193 .tRR_min = 20000, 205 .tRLOH_min = 5000,
194 .tRST_max = 500000000, 206 .tRP_min = 12000,
195 .tWB_max = 100000, 207 .tRR_min = 20000,
196 .tWC_min = 25000, 208 .tRST_max = 500000000,
197 .tWH_min = 10000, 209 .tWB_max = 100000,
198 .tWHR_min = 80000, 210 .tWC_min = 25000,
199 .tWP_min = 12000, 211 .tWH_min = 10000,
200 .tWW_min = 100000, 212 .tWHR_min = 80000,
213 .tWP_min = 12000,
214 .tWW_min = 100000,
215 },
201 }, 216 },
202 /* Mode 5 */ 217 /* Mode 5 */
203 { 218 {
204 .tADL_min = 70000, 219 .type = NAND_SDR_IFACE,
205 .tALH_min = 5000, 220 .timings.sdr = {
206 .tALS_min = 10000, 221 .tADL_min = 400000,
207 .tAR_min = 10000, 222 .tALH_min = 5000,
208 .tCEA_max = 25000, 223 .tALS_min = 10000,
209 .tCEH_min = 20000, 224 .tAR_min = 10000,
210 .tCH_min = 5000, 225 .tCEA_max = 25000,
211 .tCHZ_max = 30000, 226 .tCEH_min = 20000,
212 .tCLH_min = 5000, 227 .tCH_min = 5000,
213 .tCLR_min = 10000, 228 .tCHZ_max = 30000,
214 .tCLS_min = 10000, 229 .tCLH_min = 5000,
215 .tCOH_min = 15000, 230 .tCLR_min = 10000,
216 .tCS_min = 15000, 231 .tCLS_min = 10000,
217 .tDH_min = 5000, 232 .tCOH_min = 15000,
218 .tDS_min = 7000, 233 .tCS_min = 15000,
219 .tFEAT_max = 1000000, 234 .tDH_min = 5000,
220 .tIR_min = 0, 235 .tDS_min = 7000,
221 .tITC_max = 1000000, 236 .tFEAT_max = 1000000,
222 .tRC_min = 20000, 237 .tIR_min = 0,
223 .tREA_max = 16000, 238 .tITC_max = 1000000,
224 .tREH_min = 7000, 239 .tRC_min = 20000,
225 .tRHOH_min = 15000, 240 .tREA_max = 16000,
226 .tRHW_min = 100000, 241 .tREH_min = 7000,
227 .tRHZ_max = 100000, 242 .tRHOH_min = 15000,
228 .tRLOH_min = 5000, 243 .tRHW_min = 100000,
229 .tRP_min = 10000, 244 .tRHZ_max = 100000,
230 .tRR_min = 20000, 245 .tRLOH_min = 5000,
231 .tRST_max = 500000000, 246 .tRP_min = 10000,
232 .tWB_max = 100000, 247 .tRR_min = 20000,
233 .tWC_min = 20000, 248 .tRST_max = 500000000,
234 .tWH_min = 7000, 249 .tWB_max = 100000,
235 .tWHR_min = 80000, 250 .tWC_min = 20000,
236 .tWP_min = 10000, 251 .tWH_min = 7000,
237 .tWW_min = 100000, 252 .tWHR_min = 80000,
253 .tWP_min = 10000,
254 .tWW_min = 100000,
255 },
238 }, 256 },
239}; 257};
240 258
@@ -248,6 +266,46 @@ const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode)
248 if (mode < 0 || mode >= ARRAY_SIZE(onfi_sdr_timings)) 266 if (mode < 0 || mode >= ARRAY_SIZE(onfi_sdr_timings))
249 return ERR_PTR(-EINVAL); 267 return ERR_PTR(-EINVAL);
250 268
251 return &onfi_sdr_timings[mode]; 269 return &onfi_sdr_timings[mode].timings.sdr;
252} 270}
253EXPORT_SYMBOL(onfi_async_timing_mode_to_sdr_timings); 271EXPORT_SYMBOL(onfi_async_timing_mode_to_sdr_timings);
272
273/**
274 * onfi_init_data_interface - [NAND Interface] Initialize a data interface from
275 * given ONFI mode
276 * @iface: The data interface to be initialized
277 * @mode: The ONFI timing mode
278 */
279int onfi_init_data_interface(struct nand_chip *chip,
280 struct nand_data_interface *iface,
281 enum nand_data_interface_type type,
282 int timing_mode)
283{
284 if (type != NAND_SDR_IFACE)
285 return -EINVAL;
286
287 if (timing_mode < 0 || timing_mode >= ARRAY_SIZE(onfi_sdr_timings))
288 return -EINVAL;
289
290 *iface = onfi_sdr_timings[timing_mode];
291
292 /*
293 * TODO: initialize timings that cannot be deduced from timing mode:
294 * tR, tPROG, tCCS, ...
295 * These information are part of the ONFI parameter page.
296 */
297
298 return 0;
299}
300EXPORT_SYMBOL(onfi_init_data_interface);
301
302/**
303 * nand_get_default_data_interface - [NAND Interface] Retrieve NAND
304 * data interface for mode 0. This is used as default timing after
305 * reset.
306 */
307const struct nand_data_interface *nand_get_default_data_interface(void)
308{
309 return &onfi_sdr_timings[0];
310}
311EXPORT_SYMBOL(nand_get_default_data_interface);
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index 218c789ca7ab..28e6118362f7 100644
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -218,8 +218,7 @@ static int ndfc_probe(struct platform_device *ofdev)
218 ndfc = &ndfc_ctrl[cs]; 218 ndfc = &ndfc_ctrl[cs];
219 ndfc->chip_select = cs; 219 ndfc->chip_select = cs;
220 220
221 spin_lock_init(&ndfc->ndfc_control.lock); 221 nand_hw_control_init(&ndfc->ndfc_control);
222 init_waitqueue_head(&ndfc->ndfc_control.wq);
223 ndfc->ofdev = ofdev; 222 ndfc->ofdev = ofdev;
224 dev_set_drvdata(&ofdev->dev, ndfc); 223 dev_set_drvdata(&ofdev->dev, ndfc);
225 224
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 436dd6dc11f4..b121bf4ed73a 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1810,8 +1810,7 @@ static int alloc_nand_resource(struct platform_device *pdev)
1810 chip->cmdfunc = nand_cmdfunc; 1810 chip->cmdfunc = nand_cmdfunc;
1811 } 1811 }
1812 1812
1813 spin_lock_init(&chip->controller->lock); 1813 nand_hw_control_init(chip->controller);
1814 init_waitqueue_head(&chip->controller->wq);
1815 info->clk = devm_clk_get(&pdev->dev, NULL); 1814 info->clk = devm_clk_get(&pdev->dev, NULL);
1816 if (IS_ERR(info->clk)) { 1815 if (IS_ERR(info->clk)) {
1817 dev_err(&pdev->dev, "failed to get nand clock\n"); 1816 dev_err(&pdev->dev, "failed to get nand clock\n");
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index de7d28e62d4e..57d483ac5765 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -1957,8 +1957,7 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
1957 INIT_LIST_HEAD(&nandc->desc_list); 1957 INIT_LIST_HEAD(&nandc->desc_list);
1958 INIT_LIST_HEAD(&nandc->host_list); 1958 INIT_LIST_HEAD(&nandc->host_list);
1959 1959
1960 spin_lock_init(&nandc->controller.lock); 1960 nand_hw_control_init(&nandc->controller);
1961 init_waitqueue_head(&nandc->controller.wq);
1962 1961
1963 return 0; 1962 return 0;
1964} 1963}
diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c
index d9309cf0ce2e..d459c19d78de 100644
--- a/drivers/mtd/nand/s3c2410.c
+++ b/drivers/mtd/nand/s3c2410.c
@@ -180,7 +180,7 @@ struct s3c2410_nand_info {
180 180
181 enum s3c_cpu_type cpu_type; 181 enum s3c_cpu_type cpu_type;
182 182
183#ifdef CONFIG_CPU_FREQ 183#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
184 struct notifier_block freq_transition; 184 struct notifier_block freq_transition;
185#endif 185#endif
186}; 186};
@@ -701,7 +701,7 @@ static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
701 701
702/* cpufreq driver support */ 702/* cpufreq driver support */
703 703
704#ifdef CONFIG_CPU_FREQ 704#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
705 705
706static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb, 706static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb,
707 unsigned long val, void *data) 707 unsigned long val, void *data)
@@ -977,8 +977,7 @@ static int s3c24xx_nand_probe(struct platform_device *pdev)
977 977
978 platform_set_drvdata(pdev, info); 978 platform_set_drvdata(pdev, info);
979 979
980 spin_lock_init(&info->controller.lock); 980 nand_hw_control_init(&info->controller);
981 init_waitqueue_head(&info->controller.wq);
982 981
983 /* get the clock source and enable it */ 982 /* get the clock source and enable it */
984 983
diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index 6fa3bcd59769..442ce619b3b6 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -397,7 +397,7 @@ static int flctl_dma_fifo0_transfer(struct sh_flctl *flctl, unsigned long *buf,
397 struct dma_chan *chan; 397 struct dma_chan *chan;
398 enum dma_transfer_direction tr_dir; 398 enum dma_transfer_direction tr_dir;
399 dma_addr_t dma_addr; 399 dma_addr_t dma_addr;
400 dma_cookie_t cookie = -EINVAL; 400 dma_cookie_t cookie;
401 uint32_t reg; 401 uint32_t reg;
402 int ret; 402 int ret;
403 403
@@ -423,6 +423,12 @@ static int flctl_dma_fifo0_transfer(struct sh_flctl *flctl, unsigned long *buf,
423 desc->callback = flctl_dma_complete; 423 desc->callback = flctl_dma_complete;
424 desc->callback_param = flctl; 424 desc->callback_param = flctl;
425 cookie = dmaengine_submit(desc); 425 cookie = dmaengine_submit(desc);
426 if (dma_submit_error(cookie)) {
427 ret = dma_submit_error(cookie);
428 dev_warn(&flctl->pdev->dev,
429 "DMA submit failed, falling back to PIO\n");
430 goto out;
431 }
426 432
427 dma_async_issue_pending(chan); 433 dma_async_issue_pending(chan);
428 } else { 434 } else {
diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
index e414b31b71c1..8b8470c4e6d0 100644
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -1572,14 +1572,22 @@ static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
1572#define sunxi_nand_lookup_timing(l, p, c) \ 1572#define sunxi_nand_lookup_timing(l, p, c) \
1573 _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c) 1573 _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
1574 1574
1575static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip, 1575static int sunxi_nfc_setup_data_interface(struct mtd_info *mtd,
1576 const struct nand_sdr_timings *timings) 1576 const struct nand_data_interface *conf,
1577 bool check_only)
1577{ 1578{
1579 struct nand_chip *nand = mtd_to_nand(mtd);
1580 struct sunxi_nand_chip *chip = to_sunxi_nand(nand);
1578 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller); 1581 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller);
1582 const struct nand_sdr_timings *timings;
1579 u32 min_clk_period = 0; 1583 u32 min_clk_period = 0;
1580 s32 tWB, tADL, tWHR, tRHW, tCAD; 1584 s32 tWB, tADL, tWHR, tRHW, tCAD;
1581 long real_clk_rate; 1585 long real_clk_rate;
1582 1586
1587 timings = nand_get_sdr_timings(conf);
1588 if (IS_ERR(timings))
1589 return -ENOTSUPP;
1590
1583 /* T1 <=> tCLS */ 1591 /* T1 <=> tCLS */
1584 if (timings->tCLS_min > min_clk_period) 1592 if (timings->tCLS_min > min_clk_period)
1585 min_clk_period = timings->tCLS_min; 1593 min_clk_period = timings->tCLS_min;
@@ -1679,6 +1687,9 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
1679 return tRHW; 1687 return tRHW;
1680 } 1688 }
1681 1689
1690 if (check_only)
1691 return 0;
1692
1682 /* 1693 /*
1683 * TODO: according to ONFI specs this value only applies for DDR NAND, 1694 * TODO: according to ONFI specs this value only applies for DDR NAND,
1684 * but Allwinner seems to set this to 0x7. Mimic them for now. 1695 * but Allwinner seems to set this to 0x7. Mimic them for now.
@@ -1712,44 +1723,6 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
1712 return 0; 1723 return 0;
1713} 1724}
1714 1725
1715static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
1716 struct device_node *np)
1717{
1718 struct mtd_info *mtd = nand_to_mtd(&chip->nand);
1719 const struct nand_sdr_timings *timings;
1720 int ret;
1721 int mode;
1722
1723 mode = onfi_get_async_timing_mode(&chip->nand);
1724 if (mode == ONFI_TIMING_MODE_UNKNOWN) {
1725 mode = chip->nand.onfi_timing_mode_default;
1726 } else {
1727 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
1728 int i;
1729
1730 mode = fls(mode) - 1;
1731 if (mode < 0)
1732 mode = 0;
1733
1734 feature[0] = mode;
1735 for (i = 0; i < chip->nsels; i++) {
1736 chip->nand.select_chip(mtd, i);
1737 ret = chip->nand.onfi_set_features(mtd, &chip->nand,
1738 ONFI_FEATURE_ADDR_TIMING_MODE,
1739 feature);
1740 chip->nand.select_chip(mtd, -1);
1741 if (ret)
1742 return ret;
1743 }
1744 }
1745
1746 timings = onfi_async_timing_mode_to_sdr_timings(mode);
1747 if (IS_ERR(timings))
1748 return PTR_ERR(timings);
1749
1750 return sunxi_nand_chip_set_timings(chip, timings);
1751}
1752
1753static int sunxi_nand_ooblayout_ecc(struct mtd_info *mtd, int section, 1726static int sunxi_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
1754 struct mtd_oob_region *oobregion) 1727 struct mtd_oob_region *oobregion)
1755{ 1728{
@@ -1814,6 +1787,35 @@ static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
1814 int ret; 1787 int ret;
1815 int i; 1788 int i;
1816 1789
1790 if (ecc->options & NAND_ECC_MAXIMIZE) {
1791 int bytes;
1792
1793 ecc->size = 1024;
1794 nsectors = mtd->writesize / ecc->size;
1795
1796 /* Reserve 2 bytes for the BBM */
1797 bytes = (mtd->oobsize - 2) / nsectors;
1798
1799 /* 4 non-ECC bytes are added before each ECC bytes section */
1800 bytes -= 4;
1801
1802 /* and bytes has to be even. */
1803 if (bytes % 2)
1804 bytes--;
1805
1806 ecc->strength = bytes * 8 / fls(8 * ecc->size);
1807
1808 for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1809 if (strengths[i] > ecc->strength)
1810 break;
1811 }
1812
1813 if (!i)
1814 ecc->strength = 0;
1815 else
1816 ecc->strength = strengths[i - 1];
1817 }
1818
1817 if (ecc->size != 512 && ecc->size != 1024) 1819 if (ecc->size != 512 && ecc->size != 1024)
1818 return -EINVAL; 1820 return -EINVAL;
1819 1821
@@ -1975,7 +1977,6 @@ static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
1975static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc, 1977static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
1976 struct device_node *np) 1978 struct device_node *np)
1977{ 1979{
1978 const struct nand_sdr_timings *timings;
1979 struct sunxi_nand_chip *chip; 1980 struct sunxi_nand_chip *chip;
1980 struct mtd_info *mtd; 1981 struct mtd_info *mtd;
1981 struct nand_chip *nand; 1982 struct nand_chip *nand;
@@ -2065,25 +2066,11 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
2065 nand->read_buf = sunxi_nfc_read_buf; 2066 nand->read_buf = sunxi_nfc_read_buf;
2066 nand->write_buf = sunxi_nfc_write_buf; 2067 nand->write_buf = sunxi_nfc_write_buf;
2067 nand->read_byte = sunxi_nfc_read_byte; 2068 nand->read_byte = sunxi_nfc_read_byte;
2069 nand->setup_data_interface = sunxi_nfc_setup_data_interface;
2068 2070
2069 mtd = nand_to_mtd(nand); 2071 mtd = nand_to_mtd(nand);
2070 mtd->dev.parent = dev; 2072 mtd->dev.parent = dev;
2071 2073
2072 timings = onfi_async_timing_mode_to_sdr_timings(0);
2073 if (IS_ERR(timings)) {
2074 ret = PTR_ERR(timings);
2075 dev_err(dev,
2076 "could not retrieve timings for ONFI mode 0: %d\n",
2077 ret);
2078 return ret;
2079 }
2080
2081 ret = sunxi_nand_chip_set_timings(chip, timings);
2082 if (ret) {
2083 dev_err(dev, "could not configure chip timings: %d\n", ret);
2084 return ret;
2085 }
2086
2087 ret = nand_scan_ident(mtd, nsels, NULL); 2074 ret = nand_scan_ident(mtd, nsels, NULL);
2088 if (ret) 2075 if (ret)
2089 return ret; 2076 return ret;
@@ -2096,12 +2083,6 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
2096 2083
2097 nand->options |= NAND_SUBPAGE_READ; 2084 nand->options |= NAND_SUBPAGE_READ;
2098 2085
2099 ret = sunxi_nand_chip_init_timings(chip, np);
2100 if (ret) {
2101 dev_err(dev, "could not configure chip timings: %d\n", ret);
2102 return ret;
2103 }
2104
2105 ret = sunxi_nand_ecc_init(mtd, &nand->ecc, np); 2086 ret = sunxi_nand_ecc_init(mtd, &nand->ecc, np);
2106 if (ret) { 2087 if (ret) {
2107 dev_err(dev, "ECC init failed: %d\n", ret); 2088 dev_err(dev, "ECC init failed: %d\n", ret);
@@ -2175,8 +2156,7 @@ static int sunxi_nfc_probe(struct platform_device *pdev)
2175 return -ENOMEM; 2156 return -ENOMEM;
2176 2157
2177 nfc->dev = dev; 2158 nfc->dev = dev;
2178 spin_lock_init(&nfc->controller.lock); 2159 nand_hw_control_init(&nfc->controller);
2179 init_waitqueue_head(&nfc->controller.wq);
2180 INIT_LIST_HEAD(&nfc->chips); 2160 INIT_LIST_HEAD(&nfc->chips);
2181 2161
2182 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2162 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/drivers/mtd/nand/txx9ndfmc.c b/drivers/mtd/nand/txx9ndfmc.c
index 04d63f56baa4..0a14fda2e41b 100644
--- a/drivers/mtd/nand/txx9ndfmc.c
+++ b/drivers/mtd/nand/txx9ndfmc.c
@@ -303,8 +303,7 @@ static int __init txx9ndfmc_probe(struct platform_device *dev)
303 dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n", 303 dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
304 (gbusclk + 500000) / 1000000, hold, spw); 304 (gbusclk + 500000) / 1000000, hold, spw);
305 305
306 spin_lock_init(&drvdata->hw_control.lock); 306 nand_hw_control_init(&drvdata->hw_control);
307 init_waitqueue_head(&drvdata->hw_control.wq);
308 307
309 platform_set_drvdata(dev, drvdata); 308 platform_set_drvdata(dev, drvdata);
310 txx9ndfmc_initialize(dev); 309 txx9ndfmc_initialize(dev);
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index bc07ad30c9bf..ba7b034b2b91 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -90,10 +90,6 @@ config OF_PCI_IRQ
90 help 90 help
91 OpenFirmware PCI IRQ routing helpers 91 OpenFirmware PCI IRQ routing helpers
92 92
93config OF_MTD
94 depends on MTD
95 def_bool y
96
97config OF_RESERVED_MEM 93config OF_RESERVED_MEM
98 depends on OF_EARLY_FLATTREE 94 depends on OF_EARLY_FLATTREE
99 bool 95 bool
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 29a170612203..13f8052b9ff9 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -127,6 +127,82 @@ struct mtd_ooblayout_ops {
127 struct mtd_oob_region *oobfree); 127 struct mtd_oob_region *oobfree);
128}; 128};
129 129
130/**
131 * struct mtd_pairing_info - page pairing information
132 *
133 * @pair: pair id
134 * @group: group id
135 *
136 * The term "pair" is used here, even though TLC NANDs might group pages by 3
137 * (3 bits in a single cell). A pair should regroup all pages that are sharing
138 * the same cell. Pairs are then indexed in ascending order.
139 *
140 * @group is defining the position of a page in a given pair. It can also be
141 * seen as the bit position in the cell: page attached to bit 0 belongs to
142 * group 0, page attached to bit 1 belongs to group 1, etc.
143 *
144 * Example:
145 * The H27UCG8T2BTR-BC datasheet describes the following pairing scheme:
146 *
147 * group-0 group-1
148 *
149 * pair-0 page-0 page-4
150 * pair-1 page-1 page-5
151 * pair-2 page-2 page-8
152 * ...
153 * pair-127 page-251 page-255
154 *
155 *
156 * Note that the "group" and "pair" terms were extracted from Samsung and
157 * Hynix datasheets, and might be referenced under other names in other
158 * datasheets (Micron is describing this concept as "shared pages").
159 */
160struct mtd_pairing_info {
161 int pair;
162 int group;
163};
164
165/**
166 * struct mtd_pairing_scheme - page pairing scheme description
167 *
168 * @ngroups: number of groups. Should be related to the number of bits
169 * per cell.
170 * @get_info: converts a write-unit (page number within an erase block) into
171 * mtd_pairing information (pair + group). This function should
172 * fill the info parameter based on the wunit index or return
173 * -EINVAL if the wunit parameter is invalid.
174 * @get_wunit: converts pairing information into a write-unit (page) number.
175 * This function should return the wunit index pointed by the
176 * pairing information described in the info argument. It should
177 * return -EINVAL, if there's no wunit corresponding to the
178 * passed pairing information.
179 *
180 * See mtd_pairing_info documentation for a detailed explanation of the
181 * pair and group concepts.
182 *
183 * The mtd_pairing_scheme structure provides a generic solution to represent
184 * NAND page pairing scheme. Instead of exposing two big tables to do the
185 * write-unit <-> (pair + group) conversions, we ask the MTD drivers to
186 * implement the ->get_info() and ->get_wunit() functions.
187 *
188 * MTD users will then be able to query these information by using the
189 * mtd_pairing_info_to_wunit() and mtd_wunit_to_pairing_info() helpers.
190 *
191 * @ngroups is here to help MTD users iterating over all the pages in a
192 * given pair. This value can be retrieved by MTD users using the
193 * mtd_pairing_groups() helper.
194 *
195 * Examples are given in the mtd_pairing_info_to_wunit() and
196 * mtd_wunit_to_pairing_info() documentation.
197 */
198struct mtd_pairing_scheme {
199 int ngroups;
200 int (*get_info)(struct mtd_info *mtd, int wunit,
201 struct mtd_pairing_info *info);
202 int (*get_wunit)(struct mtd_info *mtd,
203 const struct mtd_pairing_info *info);
204};
205
130struct module; /* only needed for owner field in mtd_info */ 206struct module; /* only needed for owner field in mtd_info */
131 207
132struct mtd_info { 208struct mtd_info {
@@ -188,6 +264,9 @@ struct mtd_info {
188 /* OOB layout description */ 264 /* OOB layout description */
189 const struct mtd_ooblayout_ops *ooblayout; 265 const struct mtd_ooblayout_ops *ooblayout;
190 266
267 /* NAND pairing scheme, only provided for MLC/TLC NANDs */
268 const struct mtd_pairing_scheme *pairing;
269
191 /* the ecc step size. */ 270 /* the ecc step size. */
192 unsigned int ecc_step_size; 271 unsigned int ecc_step_size;
193 272
@@ -296,6 +375,12 @@ static inline void mtd_set_ooblayout(struct mtd_info *mtd,
296 mtd->ooblayout = ooblayout; 375 mtd->ooblayout = ooblayout;
297} 376}
298 377
378static inline void mtd_set_pairing_scheme(struct mtd_info *mtd,
379 const struct mtd_pairing_scheme *pairing)
380{
381 mtd->pairing = pairing;
382}
383
299static inline void mtd_set_of_node(struct mtd_info *mtd, 384static inline void mtd_set_of_node(struct mtd_info *mtd,
300 struct device_node *np) 385 struct device_node *np)
301{ 386{
@@ -312,6 +397,11 @@ static inline int mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops)
312 return ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize; 397 return ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize;
313} 398}
314 399
400int mtd_wunit_to_pairing_info(struct mtd_info *mtd, int wunit,
401 struct mtd_pairing_info *info);
402int mtd_pairing_info_to_wunit(struct mtd_info *mtd,
403 const struct mtd_pairing_info *info);
404int mtd_pairing_groups(struct mtd_info *mtd);
315int mtd_erase(struct mtd_info *mtd, struct erase_info *instr); 405int mtd_erase(struct mtd_info *mtd, struct erase_info *instr);
316int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, 406int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
317 void **virt, resource_size_t *phys); 407 void **virt, resource_size_t *phys);
@@ -397,6 +487,23 @@ static inline uint32_t mtd_mod_by_ws(uint64_t sz, struct mtd_info *mtd)
397 return do_div(sz, mtd->writesize); 487 return do_div(sz, mtd->writesize);
398} 488}
399 489
490static inline int mtd_wunit_per_eb(struct mtd_info *mtd)
491{
492 return mtd->erasesize / mtd->writesize;
493}
494
495static inline int mtd_offset_to_wunit(struct mtd_info *mtd, loff_t offs)
496{
497 return mtd_div_by_ws(mtd_mod_by_eb(offs, mtd), mtd);
498}
499
500static inline loff_t mtd_wunit_to_offset(struct mtd_info *mtd, loff_t base,
501 int wunit)
502{
503 return base + (wunit * mtd->writesize);
504}
505
506
400static inline int mtd_has_oob(const struct mtd_info *mtd) 507static inline int mtd_has_oob(const struct mtd_info *mtd)
401{ 508{
402 return mtd->_read_oob && mtd->_write_oob; 509 return mtd->_read_oob && mtd->_write_oob;
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 8dd6e01f45c0..c5d3d5024fc8 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -29,26 +29,26 @@ struct nand_flash_dev;
29struct device_node; 29struct device_node;
30 30
31/* Scan and identify a NAND device */ 31/* Scan and identify a NAND device */
32extern int nand_scan(struct mtd_info *mtd, int max_chips); 32int nand_scan(struct mtd_info *mtd, int max_chips);
33/* 33/*
34 * Separate phases of nand_scan(), allowing board driver to intervene 34 * Separate phases of nand_scan(), allowing board driver to intervene
35 * and override command or ECC setup according to flash type. 35 * and override command or ECC setup according to flash type.
36 */ 36 */
37extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, 37int nand_scan_ident(struct mtd_info *mtd, int max_chips,
38 struct nand_flash_dev *table); 38 struct nand_flash_dev *table);
39extern int nand_scan_tail(struct mtd_info *mtd); 39int nand_scan_tail(struct mtd_info *mtd);
40 40
41/* Free resources held by the NAND device */ 41/* Unregister the MTD device and free resources held by the NAND device */
42extern void nand_release(struct mtd_info *mtd); 42void nand_release(struct mtd_info *mtd);
43 43
44/* Internal helper for board drivers which need to override command function */ 44/* Internal helper for board drivers which need to override command function */
45extern void nand_wait_ready(struct mtd_info *mtd); 45void nand_wait_ready(struct mtd_info *mtd);
46 46
47/* locks all blocks present in the device */ 47/* locks all blocks present in the device */
48extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 48int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
49 49
50/* unlocks specified locked blocks */ 50/* unlocks specified locked blocks */
51extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 51int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
52 52
53/* The maximum number of NAND chips in an array */ 53/* The maximum number of NAND chips in an array */
54#define NAND_MAX_CHIPS 8 54#define NAND_MAX_CHIPS 8
@@ -141,6 +141,7 @@ enum nand_ecc_algo {
141 * pages and you want to rely on the default implementation. 141 * pages and you want to rely on the default implementation.
142 */ 142 */
143#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 143#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
144#define NAND_ECC_MAXIMIZE BIT(1)
144 145
145/* Bit mask for flags passed to do_nand_read_ecc */ 146/* Bit mask for flags passed to do_nand_read_ecc */
146#define NAND_GET_DEVICE 0x80 147#define NAND_GET_DEVICE 0x80
@@ -460,6 +461,13 @@ struct nand_hw_control {
460 wait_queue_head_t wq; 461 wait_queue_head_t wq;
461}; 462};
462 463
464static inline void nand_hw_control_init(struct nand_hw_control *nfc)
465{
466 nfc->active = NULL;
467 spin_lock_init(&nfc->lock);
468 init_waitqueue_head(&nfc->wq);
469}
470
463/** 471/**
464 * struct nand_ecc_ctrl - Control structure for ECC 472 * struct nand_ecc_ctrl - Control structure for ECC
465 * @mode: ECC mode 473 * @mode: ECC mode
@@ -566,6 +574,123 @@ struct nand_buffers {
566}; 574};
567 575
568/** 576/**
577 * struct nand_sdr_timings - SDR NAND chip timings
578 *
579 * This struct defines the timing requirements of a SDR NAND chip.
580 * These information can be found in every NAND datasheets and the timings
581 * meaning are described in the ONFI specifications:
582 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
583 * Parameters)
584 *
585 * All these timings are expressed in picoseconds.
586 *
587 * @tALH_min: ALE hold time
588 * @tADL_min: ALE to data loading time
589 * @tALS_min: ALE setup time
590 * @tAR_min: ALE to RE# delay
591 * @tCEA_max: CE# access time
592 * @tCEH_min:
593 * @tCH_min: CE# hold time
594 * @tCHZ_max: CE# high to output hi-Z
595 * @tCLH_min: CLE hold time
596 * @tCLR_min: CLE to RE# delay
597 * @tCLS_min: CLE setup time
598 * @tCOH_min: CE# high to output hold
599 * @tCS_min: CE# setup time
600 * @tDH_min: Data hold time
601 * @tDS_min: Data setup time
602 * @tFEAT_max: Busy time for Set Features and Get Features
603 * @tIR_min: Output hi-Z to RE# low
604 * @tITC_max: Interface and Timing Mode Change time
605 * @tRC_min: RE# cycle time
606 * @tREA_max: RE# access time
607 * @tREH_min: RE# high hold time
608 * @tRHOH_min: RE# high to output hold
609 * @tRHW_min: RE# high to WE# low
610 * @tRHZ_max: RE# high to output hi-Z
611 * @tRLOH_min: RE# low to output hold
612 * @tRP_min: RE# pulse width
613 * @tRR_min: Ready to RE# low (data only)
614 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
615 * rising edge of R/B#.
616 * @tWB_max: WE# high to SR[6] low
617 * @tWC_min: WE# cycle time
618 * @tWH_min: WE# high hold time
619 * @tWHR_min: WE# high to RE# low
620 * @tWP_min: WE# pulse width
621 * @tWW_min: WP# transition to WE# low
622 */
623struct nand_sdr_timings {
624 u32 tALH_min;
625 u32 tADL_min;
626 u32 tALS_min;
627 u32 tAR_min;
628 u32 tCEA_max;
629 u32 tCEH_min;
630 u32 tCH_min;
631 u32 tCHZ_max;
632 u32 tCLH_min;
633 u32 tCLR_min;
634 u32 tCLS_min;
635 u32 tCOH_min;
636 u32 tCS_min;
637 u32 tDH_min;
638 u32 tDS_min;
639 u32 tFEAT_max;
640 u32 tIR_min;
641 u32 tITC_max;
642 u32 tRC_min;
643 u32 tREA_max;
644 u32 tREH_min;
645 u32 tRHOH_min;
646 u32 tRHW_min;
647 u32 tRHZ_max;
648 u32 tRLOH_min;
649 u32 tRP_min;
650 u32 tRR_min;
651 u64 tRST_max;
652 u32 tWB_max;
653 u32 tWC_min;
654 u32 tWH_min;
655 u32 tWHR_min;
656 u32 tWP_min;
657 u32 tWW_min;
658};
659
660/**
661 * enum nand_data_interface_type - NAND interface timing type
662 * @NAND_SDR_IFACE: Single Data Rate interface
663 */
664enum nand_data_interface_type {
665 NAND_SDR_IFACE,
666};
667
668/**
669 * struct nand_data_interface - NAND interface timing
670 * @type: type of the timing
671 * @timings: The timing, type according to @type
672 */
673struct nand_data_interface {
674 enum nand_data_interface_type type;
675 union {
676 struct nand_sdr_timings sdr;
677 } timings;
678};
679
680/**
681 * nand_get_sdr_timings - get SDR timing from data interface
682 * @conf: The data interface
683 */
684static inline const struct nand_sdr_timings *
685nand_get_sdr_timings(const struct nand_data_interface *conf)
686{
687 if (conf->type != NAND_SDR_IFACE)
688 return ERR_PTR(-EINVAL);
689
690 return &conf->timings.sdr;
691}
692
693/**
569 * struct nand_chip - NAND Private Flash Chip Data 694 * struct nand_chip - NAND Private Flash Chip Data
570 * @mtd: MTD device registered to the MTD framework 695 * @mtd: MTD device registered to the MTD framework
571 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the 696 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
@@ -627,10 +752,9 @@ struct nand_buffers {
627 * also from the datasheet. It is the recommended ECC step 752 * also from the datasheet. It is the recommended ECC step
628 * size, if known; if unknown, set to zero. 753 * size, if known; if unknown, set to zero.
629 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 754 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
630 * either deduced from the datasheet if the NAND 755 * set to the actually used ONFI mode if the chip is
631 * chip is not ONFI compliant or set to 0 if it is 756 * ONFI compliant or deduced from the datasheet if
632 * (an ONFI chip is always configured in mode 0 757 * the NAND chip is not ONFI compliant.
633 * after a NAND reset)
634 * @numchips: [INTERN] number of physical chips 758 * @numchips: [INTERN] number of physical chips
635 * @chipsize: [INTERN] the size of one chip for multichip arrays 759 * @chipsize: [INTERN] the size of one chip for multichip arrays
636 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 760 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
@@ -650,6 +774,7 @@ struct nand_buffers {
650 * @read_retries: [INTERN] the number of read retry modes supported 774 * @read_retries: [INTERN] the number of read retry modes supported
651 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand 775 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
652 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand 776 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
777 * @setup_data_interface: [OPTIONAL] setup the data interface and timing
653 * @bbt: [INTERN] bad block table pointer 778 * @bbt: [INTERN] bad block table pointer
654 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 779 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
655 * lookup. 780 * lookup.
@@ -696,6 +821,10 @@ struct nand_chip {
696 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, 821 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
697 int feature_addr, uint8_t *subfeature_para); 822 int feature_addr, uint8_t *subfeature_para);
698 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); 823 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
824 int (*setup_data_interface)(struct mtd_info *mtd,
825 const struct nand_data_interface *conf,
826 bool check_only);
827
699 828
700 int chip_delay; 829 int chip_delay;
701 unsigned int options; 830 unsigned int options;
@@ -725,6 +854,8 @@ struct nand_chip {
725 struct nand_jedec_params jedec_params; 854 struct nand_jedec_params jedec_params;
726 }; 855 };
727 856
857 struct nand_data_interface *data_interface;
858
728 int read_retries; 859 int read_retries;
729 860
730 flstate_t state; 861 flstate_t state;
@@ -893,14 +1024,14 @@ struct nand_manufacturers {
893extern struct nand_flash_dev nand_flash_ids[]; 1024extern struct nand_flash_dev nand_flash_ids[];
894extern struct nand_manufacturers nand_manuf_ids[]; 1025extern struct nand_manufacturers nand_manuf_ids[];
895 1026
896extern int nand_default_bbt(struct mtd_info *mtd); 1027int nand_default_bbt(struct mtd_info *mtd);
897extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); 1028int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
898extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 1029int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
899extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 1030int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
900extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 1031int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
901 int allowbbt); 1032 int allowbbt);
902extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 1033int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
903 size_t *retlen, uint8_t *buf); 1034 size_t *retlen, uint8_t *buf);
904 1035
905/** 1036/**
906 * struct platform_nand_chip - chip level device structure 1037 * struct platform_nand_chip - chip level device structure
@@ -988,6 +1119,11 @@ static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
988 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); 1119 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
989} 1120}
990 1121
1122int onfi_init_data_interface(struct nand_chip *chip,
1123 struct nand_data_interface *iface,
1124 enum nand_data_interface_type type,
1125 int timing_mode);
1126
991/* 1127/*
992 * Check if it is a SLC nand. 1128 * Check if it is a SLC nand.
993 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1129 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
@@ -1023,57 +1159,10 @@ static inline int jedec_feature(struct nand_chip *chip)
1023 : 0; 1159 : 0;
1024} 1160}
1025 1161
1026/*
1027 * struct nand_sdr_timings - SDR NAND chip timings
1028 *
1029 * This struct defines the timing requirements of a SDR NAND chip.
1030 * These informations can be found in every NAND datasheets and the timings
1031 * meaning are described in the ONFI specifications:
1032 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
1033 * Parameters)
1034 *
1035 * All these timings are expressed in picoseconds.
1036 */
1037
1038struct nand_sdr_timings {
1039 u32 tALH_min;
1040 u32 tADL_min;
1041 u32 tALS_min;
1042 u32 tAR_min;
1043 u32 tCEA_max;
1044 u32 tCEH_min;
1045 u32 tCH_min;
1046 u32 tCHZ_max;
1047 u32 tCLH_min;
1048 u32 tCLR_min;
1049 u32 tCLS_min;
1050 u32 tCOH_min;
1051 u32 tCS_min;
1052 u32 tDH_min;
1053 u32 tDS_min;
1054 u32 tFEAT_max;
1055 u32 tIR_min;
1056 u32 tITC_max;
1057 u32 tRC_min;
1058 u32 tREA_max;
1059 u32 tREH_min;
1060 u32 tRHOH_min;
1061 u32 tRHW_min;
1062 u32 tRHZ_max;
1063 u32 tRLOH_min;
1064 u32 tRP_min;
1065 u32 tRR_min;
1066 u64 tRST_max;
1067 u32 tWB_max;
1068 u32 tWC_min;
1069 u32 tWH_min;
1070 u32 tWHR_min;
1071 u32 tWP_min;
1072 u32 tWW_min;
1073};
1074
1075/* get timing characteristics from ONFI timing mode. */ 1162/* get timing characteristics from ONFI timing mode. */
1076const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); 1163const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1164/* get data interface from ONFI timing mode 0, used after reset. */
1165const struct nand_data_interface *nand_get_default_data_interface(void);
1077 1166
1078int nand_check_erased_ecc_chunk(void *data, int datalen, 1167int nand_check_erased_ecc_chunk(void *data, int datalen,
1079 void *ecc, int ecclen, 1168 void *ecc, int ecclen,
@@ -1093,4 +1182,11 @@ int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1093/* Default read_oob syndrome implementation */ 1182/* Default read_oob syndrome implementation */
1094int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1183int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1095 int page); 1184 int page);
1185
1186/* Reset and initialize a NAND device */
1187int nand_reset(struct nand_chip *chip);
1188
1189/* Free resources held by the NAND device */
1190void nand_cleanup(struct nand_chip *chip);
1191
1096#endif /* __LINUX_MTD_NAND_H */ 1192#endif /* __LINUX_MTD_NAND_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 15:19:37 -0400