aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/staging/Kconfig2
-rw-r--r--drivers/staging/Makefile1
-rw-r--r--drivers/staging/axis-fifo/Kconfig1
-rw-r--r--drivers/staging/comedi/comedidev.h2
-rw-r--r--drivers/staging/comedi/drivers.c33
-rw-r--r--drivers/staging/comedi/drivers/ni_mio_common.c10
-rw-r--r--drivers/staging/erofs/dir.c45
-rw-r--r--drivers/staging/erofs/unzip_vle.c45
-rw-r--r--drivers/staging/erofs/unzip_vle_lz4.c7
-rw-r--r--drivers/staging/mt7621-dts/gbpc1.dts29
-rw-r--r--drivers/staging/mt7621-dts/mt7621.dtsi73
-rw-r--r--drivers/staging/mt7621-eth/Documentation/devicetree/bindings/net/mediatek-net-gsw.txt48
-rw-r--r--drivers/staging/mt7621-eth/Kconfig39
-rw-r--r--drivers/staging/mt7621-eth/Makefile14
-rw-r--r--drivers/staging/mt7621-eth/TODO13
-rw-r--r--drivers/staging/mt7621-eth/ethtool.c250
-rw-r--r--drivers/staging/mt7621-eth/ethtool.h15
-rw-r--r--drivers/staging/mt7621-eth/gsw_mt7620.h277
-rw-r--r--drivers/staging/mt7621-eth/gsw_mt7621.c297
-rw-r--r--drivers/staging/mt7621-eth/mdio.c275
-rw-r--r--drivers/staging/mt7621-eth/mdio.h27
-rw-r--r--drivers/staging/mt7621-eth/mdio_mt7620.c173
-rw-r--r--drivers/staging/mt7621-eth/mtk_eth_soc.c2176
-rw-r--r--drivers/staging/mt7621-eth/mtk_eth_soc.h716
-rw-r--r--drivers/staging/mt7621-eth/soc_mt7621.c161
-rw-r--r--drivers/staging/mt7621-pci/Kconfig1
-rw-r--r--drivers/staging/octeon/ethernet-mdio.c2
-rw-r--r--drivers/staging/octeon/ethernet.c40
-rw-r--r--drivers/staging/octeon/octeon-ethernet.h4
-rw-r--r--drivers/staging/olpc_dcon/olpc_dcon_xo_1.c2
-rw-r--r--drivers/staging/rtl8188eu/core/rtw_xmit.c9
-rw-r--r--drivers/staging/rtl8188eu/include/rtw_xmit.h2
-rw-r--r--drivers/staging/rtl8712/rtl8712_cmd.c10
-rw-r--r--drivers/staging/rtl8712/rtl8712_cmd.h2
-rw-r--r--drivers/staging/rtl8723bs/core/rtw_xmit.c14
-rw-r--r--drivers/staging/rtl8723bs/include/rtw_xmit.h2
-rw-r--r--drivers/staging/rtlwifi/phydm/rtl_phydm.c2
-rw-r--r--drivers/staging/rtlwifi/rtl8822be/fw.c2
-rw-r--r--drivers/staging/speakup/speakup_soft.c16
-rw-r--r--drivers/staging/speakup/spk_priv.h1
-rw-r--r--drivers/staging/speakup/synth.c6
-rw-r--r--drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c8
-rw-r--r--drivers/staging/vt6655/device_main.c11
43 files changed, 276 insertions, 4587 deletions
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index c0901b96cfe4..62951e836cbc 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -114,8 +114,6 @@ source "drivers/staging/ralink-gdma/Kconfig"
114 114
115source "drivers/staging/mt7621-mmc/Kconfig" 115source "drivers/staging/mt7621-mmc/Kconfig"
116 116
117source "drivers/staging/mt7621-eth/Kconfig"
118
119source "drivers/staging/mt7621-dts/Kconfig" 117source "drivers/staging/mt7621-dts/Kconfig"
120 118
121source "drivers/staging/gasket/Kconfig" 119source "drivers/staging/gasket/Kconfig"
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index 57c6bce13ff4..d1b17ddcd354 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -47,7 +47,6 @@ obj-$(CONFIG_SPI_MT7621) += mt7621-spi/
47obj-$(CONFIG_SOC_MT7621) += mt7621-dma/ 47obj-$(CONFIG_SOC_MT7621) += mt7621-dma/
48obj-$(CONFIG_DMA_RALINK) += ralink-gdma/ 48obj-$(CONFIG_DMA_RALINK) += ralink-gdma/
49obj-$(CONFIG_MTK_MMC) += mt7621-mmc/ 49obj-$(CONFIG_MTK_MMC) += mt7621-mmc/
50obj-$(CONFIG_NET_MEDIATEK_SOC_STAGING) += mt7621-eth/
51obj-$(CONFIG_SOC_MT7621) += mt7621-dts/ 50obj-$(CONFIG_SOC_MT7621) += mt7621-dts/
52obj-$(CONFIG_STAGING_GASKET_FRAMEWORK) += gasket/ 51obj-$(CONFIG_STAGING_GASKET_FRAMEWORK) += gasket/
53obj-$(CONFIG_XIL_AXIS_FIFO) += axis-fifo/ 52obj-$(CONFIG_XIL_AXIS_FIFO) += axis-fifo/
diff --git a/drivers/staging/axis-fifo/Kconfig b/drivers/staging/axis-fifo/Kconfig
index 687537203d9c..d9725888af6f 100644
--- a/drivers/staging/axis-fifo/Kconfig
+++ b/drivers/staging/axis-fifo/Kconfig
@@ -3,6 +3,7 @@
3# 3#
4config XIL_AXIS_FIFO 4config XIL_AXIS_FIFO
5 tristate "Xilinx AXI-Stream FIFO IP core driver" 5 tristate "Xilinx AXI-Stream FIFO IP core driver"
6 depends on OF
6 default n 7 default n
7 help 8 help
8 This adds support for the Xilinx AXI-Stream 9 This adds support for the Xilinx AXI-Stream
diff --git a/drivers/staging/comedi/comedidev.h b/drivers/staging/comedi/comedidev.h
index a7d569cfca5d..0dff1ac057cd 100644
--- a/drivers/staging/comedi/comedidev.h
+++ b/drivers/staging/comedi/comedidev.h
@@ -1001,6 +1001,8 @@ int comedi_dio_insn_config(struct comedi_device *dev,
1001 unsigned int mask); 1001 unsigned int mask);
1002unsigned int comedi_dio_update_state(struct comedi_subdevice *s, 1002unsigned int comedi_dio_update_state(struct comedi_subdevice *s,
1003 unsigned int *data); 1003 unsigned int *data);
1004unsigned int comedi_bytes_per_scan_cmd(struct comedi_subdevice *s,
1005 struct comedi_cmd *cmd);
1004unsigned int comedi_bytes_per_scan(struct comedi_subdevice *s); 1006unsigned int comedi_bytes_per_scan(struct comedi_subdevice *s);
1005unsigned int comedi_nscans_left(struct comedi_subdevice *s, 1007unsigned int comedi_nscans_left(struct comedi_subdevice *s,
1006 unsigned int nscans); 1008 unsigned int nscans);
diff --git a/drivers/staging/comedi/drivers.c b/drivers/staging/comedi/drivers.c
index eefa62f42c0f..5a32b8fc000e 100644
--- a/drivers/staging/comedi/drivers.c
+++ b/drivers/staging/comedi/drivers.c
@@ -394,11 +394,13 @@ unsigned int comedi_dio_update_state(struct comedi_subdevice *s,
394EXPORT_SYMBOL_GPL(comedi_dio_update_state); 394EXPORT_SYMBOL_GPL(comedi_dio_update_state);
395 395
396/** 396/**
397 * comedi_bytes_per_scan() - Get length of asynchronous command "scan" in bytes 397 * comedi_bytes_per_scan_cmd() - Get length of asynchronous command "scan" in
398 * bytes
398 * @s: COMEDI subdevice. 399 * @s: COMEDI subdevice.
400 * @cmd: COMEDI command.
399 * 401 *
400 * Determines the overall scan length according to the subdevice type and the 402 * Determines the overall scan length according to the subdevice type and the
401 * number of channels in the scan. 403 * number of channels in the scan for the specified command.
402 * 404 *
403 * For digital input, output or input/output subdevices, samples for 405 * For digital input, output or input/output subdevices, samples for
404 * multiple channels are assumed to be packed into one or more unsigned 406 * multiple channels are assumed to be packed into one or more unsigned
@@ -408,9 +410,9 @@ EXPORT_SYMBOL_GPL(comedi_dio_update_state);
408 * 410 *
409 * Returns the overall scan length in bytes. 411 * Returns the overall scan length in bytes.
410 */ 412 */
411unsigned int comedi_bytes_per_scan(struct comedi_subdevice *s) 413unsigned int comedi_bytes_per_scan_cmd(struct comedi_subdevice *s,
414 struct comedi_cmd *cmd)
412{ 415{
413 struct comedi_cmd *cmd = &s->async->cmd;
414 unsigned int num_samples; 416 unsigned int num_samples;
415 unsigned int bits_per_sample; 417 unsigned int bits_per_sample;
416 418
@@ -427,6 +429,29 @@ unsigned int comedi_bytes_per_scan(struct comedi_subdevice *s)
427 } 429 }
428 return comedi_samples_to_bytes(s, num_samples); 430 return comedi_samples_to_bytes(s, num_samples);
429} 431}
432EXPORT_SYMBOL_GPL(comedi_bytes_per_scan_cmd);
433
434/**
435 * comedi_bytes_per_scan() - Get length of asynchronous command "scan" in bytes
436 * @s: COMEDI subdevice.
437 *
438 * Determines the overall scan length according to the subdevice type and the
439 * number of channels in the scan for the current command.
440 *
441 * For digital input, output or input/output subdevices, samples for
442 * multiple channels are assumed to be packed into one or more unsigned
443 * short or unsigned int values according to the subdevice's %SDF_LSAMPL
444 * flag. For other types of subdevice, samples are assumed to occupy a
445 * whole unsigned short or unsigned int according to the %SDF_LSAMPL flag.
446 *
447 * Returns the overall scan length in bytes.
448 */
449unsigned int comedi_bytes_per_scan(struct comedi_subdevice *s)
450{
451 struct comedi_cmd *cmd = &s->async->cmd;
452
453 return comedi_bytes_per_scan_cmd(s, cmd);
454}
430EXPORT_SYMBOL_GPL(comedi_bytes_per_scan); 455EXPORT_SYMBOL_GPL(comedi_bytes_per_scan);
431 456
432static unsigned int __comedi_nscans_left(struct comedi_subdevice *s, 457static unsigned int __comedi_nscans_left(struct comedi_subdevice *s,
diff --git a/drivers/staging/comedi/drivers/ni_mio_common.c b/drivers/staging/comedi/drivers/ni_mio_common.c
index 5edf59ac6706..b04dad8c7092 100644
--- a/drivers/staging/comedi/drivers/ni_mio_common.c
+++ b/drivers/staging/comedi/drivers/ni_mio_common.c
@@ -3545,6 +3545,7 @@ static int ni_cdio_cmdtest(struct comedi_device *dev,
3545 struct comedi_subdevice *s, struct comedi_cmd *cmd) 3545 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3546{ 3546{
3547 struct ni_private *devpriv = dev->private; 3547 struct ni_private *devpriv = dev->private;
3548 unsigned int bytes_per_scan;
3548 int err = 0; 3549 int err = 0;
3549 3550
3550 /* Step 1 : check if triggers are trivially valid */ 3551 /* Step 1 : check if triggers are trivially valid */
@@ -3579,9 +3580,12 @@ static int ni_cdio_cmdtest(struct comedi_device *dev,
3579 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0); 3580 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3580 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, 3581 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3581 cmd->chanlist_len); 3582 cmd->chanlist_len);
3582 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 3583 bytes_per_scan = comedi_bytes_per_scan_cmd(s, cmd);
3583 s->async->prealloc_bufsz / 3584 if (bytes_per_scan) {
3584 comedi_bytes_per_scan(s)); 3585 err |= comedi_check_trigger_arg_max(&cmd->stop_arg,
3586 s->async->prealloc_bufsz /
3587 bytes_per_scan);
3588 }
3585 3589
3586 if (err) 3590 if (err)
3587 return 3; 3591 return 3;
diff --git a/drivers/staging/erofs/dir.c b/drivers/staging/erofs/dir.c
index 829f7b12e0dc..9bbc68729c11 100644
--- a/drivers/staging/erofs/dir.c
+++ b/drivers/staging/erofs/dir.c
@@ -23,6 +23,21 @@ static const unsigned char erofs_filetype_table[EROFS_FT_MAX] = {
23 [EROFS_FT_SYMLINK] = DT_LNK, 23 [EROFS_FT_SYMLINK] = DT_LNK,
24}; 24};
25 25
26static void debug_one_dentry(unsigned char d_type, const char *de_name,
27 unsigned int de_namelen)
28{
29#ifdef CONFIG_EROFS_FS_DEBUG
30 /* since the on-disk name could not have the trailing '\0' */
31 unsigned char dbg_namebuf[EROFS_NAME_LEN + 1];
32
33 memcpy(dbg_namebuf, de_name, de_namelen);
34 dbg_namebuf[de_namelen] = '\0';
35
36 debugln("found dirent %s de_len %u d_type %d", dbg_namebuf,
37 de_namelen, d_type);
38#endif
39}
40
26static int erofs_fill_dentries(struct dir_context *ctx, 41static int erofs_fill_dentries(struct dir_context *ctx,
27 void *dentry_blk, unsigned int *ofs, 42 void *dentry_blk, unsigned int *ofs,
28 unsigned int nameoff, unsigned int maxsize) 43 unsigned int nameoff, unsigned int maxsize)
@@ -33,14 +48,10 @@ static int erofs_fill_dentries(struct dir_context *ctx,
33 de = dentry_blk + *ofs; 48 de = dentry_blk + *ofs;
34 while (de < end) { 49 while (de < end) {
35 const char *de_name; 50 const char *de_name;
36 int de_namelen; 51 unsigned int de_namelen;
37 unsigned char d_type; 52 unsigned char d_type;
38#ifdef CONFIG_EROFS_FS_DEBUG
39 unsigned int dbg_namelen;
40 unsigned char dbg_namebuf[EROFS_NAME_LEN];
41#endif
42 53
43 if (unlikely(de->file_type < EROFS_FT_MAX)) 54 if (de->file_type < EROFS_FT_MAX)
44 d_type = erofs_filetype_table[de->file_type]; 55 d_type = erofs_filetype_table[de->file_type];
45 else 56 else
46 d_type = DT_UNKNOWN; 57 d_type = DT_UNKNOWN;
@@ -48,26 +59,20 @@ static int erofs_fill_dentries(struct dir_context *ctx,
48 nameoff = le16_to_cpu(de->nameoff); 59 nameoff = le16_to_cpu(de->nameoff);
49 de_name = (char *)dentry_blk + nameoff; 60 de_name = (char *)dentry_blk + nameoff;
50 61
51 de_namelen = unlikely(de + 1 >= end) ? 62 /* the last dirent in the block? */
52 /* last directory entry */ 63 if (de + 1 >= end)
53 strnlen(de_name, maxsize - nameoff) : 64 de_namelen = strnlen(de_name, maxsize - nameoff);
54 le16_to_cpu(de[1].nameoff) - nameoff; 65 else
66 de_namelen = le16_to_cpu(de[1].nameoff) - nameoff;
55 67
56 /* a corrupted entry is found */ 68 /* a corrupted entry is found */
57 if (unlikely(de_namelen < 0)) { 69 if (unlikely(nameoff + de_namelen > maxsize ||
70 de_namelen > EROFS_NAME_LEN)) {
58 DBG_BUGON(1); 71 DBG_BUGON(1);
59 return -EIO; 72 return -EIO;
60 } 73 }
61 74
62#ifdef CONFIG_EROFS_FS_DEBUG 75 debug_one_dentry(d_type, de_name, de_namelen);
63 dbg_namelen = min(EROFS_NAME_LEN - 1, de_namelen);
64 memcpy(dbg_namebuf, de_name, dbg_namelen);
65 dbg_namebuf[dbg_namelen] = '\0';
66
67 debugln("%s, found de_name %s de_len %d d_type %d", __func__,
68 dbg_namebuf, de_namelen, d_type);
69#endif
70
71 if (!dir_emit(ctx, de_name, de_namelen, 76 if (!dir_emit(ctx, de_name, de_namelen,
72 le64_to_cpu(de->nid), d_type)) 77 le64_to_cpu(de->nid), d_type))
73 /* stopped by some reason */ 78 /* stopped by some reason */
diff --git a/drivers/staging/erofs/unzip_vle.c b/drivers/staging/erofs/unzip_vle.c
index 8715bc50e09c..31eef8395774 100644
--- a/drivers/staging/erofs/unzip_vle.c
+++ b/drivers/staging/erofs/unzip_vle.c
@@ -972,6 +972,7 @@ repeat:
972 overlapped = false; 972 overlapped = false;
973 compressed_pages = grp->compressed_pages; 973 compressed_pages = grp->compressed_pages;
974 974
975 err = 0;
975 for (i = 0; i < clusterpages; ++i) { 976 for (i = 0; i < clusterpages; ++i) {
976 unsigned int pagenr; 977 unsigned int pagenr;
977 978
@@ -981,26 +982,39 @@ repeat:
981 DBG_BUGON(!page); 982 DBG_BUGON(!page);
982 DBG_BUGON(!page->mapping); 983 DBG_BUGON(!page->mapping);
983 984
984 if (z_erofs_is_stagingpage(page)) 985 if (!z_erofs_is_stagingpage(page)) {
985 continue;
986#ifdef EROFS_FS_HAS_MANAGED_CACHE 986#ifdef EROFS_FS_HAS_MANAGED_CACHE
987 if (page->mapping == MNGD_MAPPING(sbi)) { 987 if (page->mapping == MNGD_MAPPING(sbi)) {
988 DBG_BUGON(!PageUptodate(page)); 988 if (unlikely(!PageUptodate(page)))
989 continue; 989 err = -EIO;
990 } 990 continue;
991 }
991#endif 992#endif
992 993
993 /* only non-head page could be reused as a compressed page */ 994 /*
994 pagenr = z_erofs_onlinepage_index(page); 995 * only if non-head page can be selected
996 * for inplace decompression
997 */
998 pagenr = z_erofs_onlinepage_index(page);
995 999
996 DBG_BUGON(pagenr >= nr_pages); 1000 DBG_BUGON(pagenr >= nr_pages);
997 DBG_BUGON(pages[pagenr]); 1001 DBG_BUGON(pages[pagenr]);
998 ++sparsemem_pages; 1002 ++sparsemem_pages;
999 pages[pagenr] = page; 1003 pages[pagenr] = page;
1000 1004
1001 overlapped = true; 1005 overlapped = true;
1006 }
1007
1008 /* PG_error needs checking for inplaced and staging pages */
1009 if (unlikely(PageError(page))) {
1010 DBG_BUGON(PageUptodate(page));
1011 err = -EIO;
1012 }
1002 } 1013 }
1003 1014
1015 if (unlikely(err))
1016 goto out;
1017
1004 llen = (nr_pages << PAGE_SHIFT) - work->pageofs; 1018 llen = (nr_pages << PAGE_SHIFT) - work->pageofs;
1005 1019
1006 if (z_erofs_vle_workgrp_fmt(grp) == Z_EROFS_VLE_WORKGRP_FMT_PLAIN) { 1020 if (z_erofs_vle_workgrp_fmt(grp) == Z_EROFS_VLE_WORKGRP_FMT_PLAIN) {
@@ -1029,6 +1043,10 @@ repeat:
1029 1043
1030skip_allocpage: 1044skip_allocpage:
1031 vout = erofs_vmap(pages, nr_pages); 1045 vout = erofs_vmap(pages, nr_pages);
1046 if (!vout) {
1047 err = -ENOMEM;
1048 goto out;
1049 }
1032 1050
1033 err = z_erofs_vle_unzip_vmap(compressed_pages, 1051 err = z_erofs_vle_unzip_vmap(compressed_pages,
1034 clusterpages, vout, llen, work->pageofs, overlapped); 1052 clusterpages, vout, llen, work->pageofs, overlapped);
@@ -1194,6 +1212,7 @@ repeat:
1194 if (page->mapping == mc) { 1212 if (page->mapping == mc) {
1195 WRITE_ONCE(grp->compressed_pages[nr], page); 1213 WRITE_ONCE(grp->compressed_pages[nr], page);
1196 1214
1215 ClearPageError(page);
1197 if (!PagePrivate(page)) { 1216 if (!PagePrivate(page)) {
1198 /* 1217 /*
1199 * impossible to be !PagePrivate(page) for 1218 * impossible to be !PagePrivate(page) for
diff --git a/drivers/staging/erofs/unzip_vle_lz4.c b/drivers/staging/erofs/unzip_vle_lz4.c
index 48b263a2731a..0daac9b984a8 100644
--- a/drivers/staging/erofs/unzip_vle_lz4.c
+++ b/drivers/staging/erofs/unzip_vle_lz4.c
@@ -136,10 +136,13 @@ int z_erofs_vle_unzip_fast_percpu(struct page **compressed_pages,
136 136
137 nr_pages = DIV_ROUND_UP(outlen + pageofs, PAGE_SIZE); 137 nr_pages = DIV_ROUND_UP(outlen + pageofs, PAGE_SIZE);
138 138
139 if (clusterpages == 1) 139 if (clusterpages == 1) {
140 vin = kmap_atomic(compressed_pages[0]); 140 vin = kmap_atomic(compressed_pages[0]);
141 else 141 } else {
142 vin = erofs_vmap(compressed_pages, clusterpages); 142 vin = erofs_vmap(compressed_pages, clusterpages);
143 if (!vin)
144 return -ENOMEM;
145 }
143 146
144 preempt_disable(); 147 preempt_disable();
145 vout = erofs_pcpubuf[smp_processor_id()].data; 148 vout = erofs_pcpubuf[smp_processor_id()].data;
diff --git a/drivers/staging/mt7621-dts/gbpc1.dts b/drivers/staging/mt7621-dts/gbpc1.dts
index b73385540216..250c15ace2a7 100644
--- a/drivers/staging/mt7621-dts/gbpc1.dts
+++ b/drivers/staging/mt7621-dts/gbpc1.dts
@@ -117,22 +117,6 @@
117 status = "okay"; 117 status = "okay";
118}; 118};
119 119
120&ethernet {
121 //mtd-mac-address = <&factory 0xe000>;
122 gmac1: mac@0 {
123 compatible = "mediatek,eth-mac";
124 reg = <0>;
125 phy-handle = <&phy1>;
126 };
127
128 mdio-bus {
129 phy1: ethernet-phy@1 {
130 reg = <1>;
131 phy-mode = "rgmii";
132 };
133 };
134};
135
136&pinctrl { 120&pinctrl {
137 state_default: pinctrl0 { 121 state_default: pinctrl0 {
138 gpio { 122 gpio {
@@ -141,3 +125,16 @@
141 }; 125 };
142 }; 126 };
143}; 127};
128
129&switch0 {
130 ports {
131 port@0 {
132 label = "ethblack";
133 status = "ok";
134 };
135 port@4 {
136 label = "ethblue";
137 status = "ok";
138 };
139 };
140};
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 6aff3680ce4b..17020e24abd2 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -372,16 +372,83 @@
372 372
373 mediatek,ethsys = <&ethsys>; 373 mediatek,ethsys = <&ethsys>;
374 374
375 mediatek,switch = <&gsw>;
376 375
376 gmac0: mac@0 {
377 compatible = "mediatek,eth-mac";
378 reg = <0>;
379 phy-mode = "rgmii";
380 fixed-link {
381 speed = <1000>;
382 full-duplex;
383 pause;
384 };
385 };
386 gmac1: mac@1 {
387 compatible = "mediatek,eth-mac";
388 reg = <1>;
389 status = "off";
390 phy-mode = "rgmii";
391 phy-handle = <&phy5>;
392 };
377 mdio-bus { 393 mdio-bus {
378 #address-cells = <1>; 394 #address-cells = <1>;
379 #size-cells = <0>; 395 #size-cells = <0>;
380 396
381 phy1f: ethernet-phy@1f { 397 phy5: ethernet-phy@5 {
382 reg = <0x1f>; 398 reg = <5>;
383 phy-mode = "rgmii"; 399 phy-mode = "rgmii";
384 }; 400 };
401
402 switch0: switch0@0 {
403 compatible = "mediatek,mt7621";
404 #address-cells = <1>;
405 #size-cells = <0>;
406 reg = <0>;
407 mediatek,mcm;
408 resets = <&rstctrl 2>;
409 reset-names = "mcm";
410
411 ports {
412 #address-cells = <1>;
413 #size-cells = <0>;
414 reg = <0>;
415 port@0 {
416 status = "off";
417 reg = <0>;
418 label = "lan0";
419 };
420 port@1 {
421 status = "off";
422 reg = <1>;
423 label = "lan1";
424 };
425 port@2 {
426 status = "off";
427 reg = <2>;
428 label = "lan2";
429 };
430 port@3 {
431 status = "off";
432 reg = <3>;
433 label = "lan3";
434 };
435 port@4 {
436 status = "off";
437 reg = <4>;
438 label = "lan4";
439 };
440 port@6 {
441 reg = <6>;
442 label = "cpu";
443 ethernet = <&gmac0>;
444 phy-mode = "trgmii";
445 fixed-link {
446 speed = <1000>;
447 full-duplex;
448 };
449 };
450 };
451 };
385 }; 452 };
386 }; 453 };
387 454
diff --git a/drivers/staging/mt7621-eth/Documentation/devicetree/bindings/net/mediatek-net-gsw.txt b/drivers/staging/mt7621-eth/Documentation/devicetree/bindings/net/mediatek-net-gsw.txt
deleted file mode 100644
index 596b38552697..000000000000
--- a/drivers/staging/mt7621-eth/Documentation/devicetree/bindings/net/mediatek-net-gsw.txt
+++ /dev/null
@@ -1,48 +0,0 @@
1Mediatek Gigabit Switch
2=======================
3
4The mediatek gigabit switch can be found on Mediatek SoCs.
5
6Required properties:
7- compatible: Should be "mediatek,mt7620-gsw", "mediatek,mt7621-gsw",
8 "mediatek,mt7623-gsw"
9- reg: Address and length of the register set for the device
10- interrupts: Should contain the gigabit switches interrupt
11
12
13Additional required properties for ARM based SoCs:
14- mediatek,reset-pin: phandle describing the reset GPIO
15- clocks: the clocks used by the switch
16- clock-names: the names of the clocks listed in the clocks property
17 these should be "trgpll", "esw", "gp2", "gp1"
18- mt7530-supply: the phandle of the regulator used to power the switch
19- mediatek,pctl-regmap: phandle to the port control regmap. this is used to
20 setup the drive current
21
22
23Optional properties:
24- interrupt-parent: Should be the phandle for the interrupt controller
25 that services interrupts for this device
26
27Example:
28
29gsw: switch@1b100000 {
30 compatible = "mediatek,mt7623-gsw";
31 reg = <0 0x1b110000 0 0x300000>;
32
33 interrupt-parent = <&pio>;
34 interrupts = <168 IRQ_TYPE_EDGE_RISING>;
35
36 clocks = <&apmixedsys CLK_APMIXED_TRGPLL>,
37 <&ethsys CLK_ETHSYS_ESW>,
38 <&ethsys CLK_ETHSYS_GP2>,
39 <&ethsys CLK_ETHSYS_GP1>;
40 clock-names = "trgpll", "esw", "gp2", "gp1";
41
42 mt7530-supply = <&mt6323_vpa_reg>;
43
44 mediatek,pctl-regmap = <&syscfg_pctl_a>;
45 mediatek,reset-pin = <&pio 15 0>;
46
47 status = "okay";
48};
diff --git a/drivers/staging/mt7621-eth/Kconfig b/drivers/staging/mt7621-eth/Kconfig
deleted file mode 100644
index 44ea86c7a96c..000000000000
--- a/drivers/staging/mt7621-eth/Kconfig
+++ /dev/null
@@ -1,39 +0,0 @@
1config NET_VENDOR_MEDIATEK_STAGING
2 bool "MediaTek ethernet driver - staging version"
3 depends on RALINK
4 ---help---
5 If you have an MT7621 Mediatek SoC with ethernet, say Y.
6
7if NET_VENDOR_MEDIATEK_STAGING
8choice
9 prompt "MAC type"
10
11config NET_MEDIATEK_MT7621
12 bool "MT7621"
13 depends on MIPS && SOC_MT7621
14
15endchoice
16
17config NET_MEDIATEK_SOC_STAGING
18 tristate "MediaTek SoC Gigabit Ethernet support"
19 depends on NET_VENDOR_MEDIATEK_STAGING
20 select PHYLIB
21 ---help---
22 This driver supports the gigabit ethernet MACs in the
23 MediaTek SoC family.
24
25config NET_MEDIATEK_MDIO
26 def_bool NET_MEDIATEK_SOC_STAGING
27 depends on NET_MEDIATEK_MT7621
28 select PHYLIB
29
30config NET_MEDIATEK_MDIO_MT7620
31 def_bool NET_MEDIATEK_SOC_STAGING
32 depends on NET_MEDIATEK_MT7621
33 select NET_MEDIATEK_MDIO
34
35config NET_MEDIATEK_GSW_MT7621
36 def_tristate NET_MEDIATEK_SOC_STAGING
37 depends on NET_MEDIATEK_MT7621
38
39endif #NET_VENDOR_MEDIATEK_STAGING
diff --git a/drivers/staging/mt7621-eth/Makefile b/drivers/staging/mt7621-eth/Makefile
deleted file mode 100644
index 018bcc3596b3..000000000000
--- a/drivers/staging/mt7621-eth/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
1#
2# Makefile for the Ralink SoCs built-in ethernet macs
3#
4
5mtk-eth-soc-y += mtk_eth_soc.o ethtool.o
6
7mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MDIO) += mdio.o
8mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MDIO_MT7620) += mdio_mt7620.o
9
10mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MT7621) += soc_mt7621.o
11
12obj-$(CONFIG_NET_MEDIATEK_GSW_MT7621) += gsw_mt7621.o
13
14obj-$(CONFIG_NET_MEDIATEK_SOC_STAGING) += mtk-eth-soc.o
diff --git a/drivers/staging/mt7621-eth/TODO b/drivers/staging/mt7621-eth/TODO
deleted file mode 100644
index f9e47d4b4cd4..000000000000
--- a/drivers/staging/mt7621-eth/TODO
+++ /dev/null
@@ -1,13 +0,0 @@
1
2- verify devicetree documentation is consistent with code
3- fix ethtool - currently doesn't return valid data.
4- general code review and clean up
5- add support for second MAC on mt7621
6- convert gsw code to use switchdev interfaces
7- md7620_mmi_write etc should probably be wrapped
8 in a regmap abstraction.
9- Get soc_mt7621 to work with QDMA TX if possible.
10- Ensure phys are correctly configured when a cable
11 is plugged in.
12
13Cc: NeilBrown <neil@brown.name>
diff --git a/drivers/staging/mt7621-eth/ethtool.c b/drivers/staging/mt7621-eth/ethtool.c
deleted file mode 100644
index 8c4228e2c987..000000000000
--- a/drivers/staging/mt7621-eth/ethtool.c
+++ /dev/null
@@ -1,250 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0
2/* This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
12 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
13 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
14 */
15
16#include "mtk_eth_soc.h"
17#include "ethtool.h"
18
19struct mtk_stat {
20 char name[ETH_GSTRING_LEN];
21 unsigned int idx;
22};
23
24#define MTK_HW_STAT(stat) { \
25 .name = #stat, \
26 .idx = offsetof(struct mtk_hw_stats, stat) / sizeof(u64) \
27}
28
29static const struct mtk_stat mtk_ethtool_hw_stats[] = {
30 MTK_HW_STAT(tx_bytes),
31 MTK_HW_STAT(tx_packets),
32 MTK_HW_STAT(tx_skip),
33 MTK_HW_STAT(tx_collisions),
34 MTK_HW_STAT(rx_bytes),
35 MTK_HW_STAT(rx_packets),
36 MTK_HW_STAT(rx_overflow),
37 MTK_HW_STAT(rx_fcs_errors),
38 MTK_HW_STAT(rx_short_errors),
39 MTK_HW_STAT(rx_long_errors),
40 MTK_HW_STAT(rx_checksum_errors),
41 MTK_HW_STAT(rx_flow_control_packets),
42};
43
44#define MTK_HW_STATS_LEN ARRAY_SIZE(mtk_ethtool_hw_stats)
45
46static int mtk_get_link_ksettings(struct net_device *dev,
47 struct ethtool_link_ksettings *cmd)
48{
49 struct mtk_mac *mac = netdev_priv(dev);
50 int err;
51
52 if (!mac->phy_dev)
53 return -ENODEV;
54
55 if (mac->phy_flags == MTK_PHY_FLAG_ATTACH) {
56 err = phy_read_status(mac->phy_dev);
57 if (err)
58 return -ENODEV;
59 }
60
61 phy_ethtool_ksettings_get(mac->phy_dev, cmd);
62 return 0;
63}
64
65static int mtk_set_link_ksettings(struct net_device *dev,
66 const struct ethtool_link_ksettings *cmd)
67{
68 struct mtk_mac *mac = netdev_priv(dev);
69
70 if (!mac->phy_dev)
71 return -ENODEV;
72
73 if (cmd->base.phy_address != mac->phy_dev->mdio.addr) {
74 if (mac->hw->phy->phy_node[cmd->base.phy_address]) {
75 mac->phy_dev = mac->hw->phy->phy[cmd->base.phy_address];
76 mac->phy_flags = MTK_PHY_FLAG_PORT;
77 } else if (mac->hw->mii_bus) {
78 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
79 cmd->base.phy_address);
80 if (!mac->phy_dev)
81 return -ENODEV;
82 mac->phy_flags = MTK_PHY_FLAG_ATTACH;
83 } else {
84 return -ENODEV;
85 }
86 }
87
88 return phy_ethtool_ksettings_set(mac->phy_dev, cmd);
89}
90
91static void mtk_get_drvinfo(struct net_device *dev,
92 struct ethtool_drvinfo *info)
93{
94 struct mtk_mac *mac = netdev_priv(dev);
95 struct mtk_soc_data *soc = mac->hw->soc;
96
97 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
98 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
99
100 if (soc->reg_table[MTK_REG_MTK_COUNTER_BASE])
101 info->n_stats = MTK_HW_STATS_LEN;
102}
103
104static u32 mtk_get_msglevel(struct net_device *dev)
105{
106 struct mtk_mac *mac = netdev_priv(dev);
107
108 return mac->hw->msg_enable;
109}
110
111static void mtk_set_msglevel(struct net_device *dev, u32 value)
112{
113 struct mtk_mac *mac = netdev_priv(dev);
114
115 mac->hw->msg_enable = value;
116}
117
118static int mtk_nway_reset(struct net_device *dev)
119{
120 struct mtk_mac *mac = netdev_priv(dev);
121
122 if (!mac->phy_dev)
123 return -EOPNOTSUPP;
124
125 return genphy_restart_aneg(mac->phy_dev);
126}
127
128static u32 mtk_get_link(struct net_device *dev)
129{
130 struct mtk_mac *mac = netdev_priv(dev);
131 int err;
132
133 if (!mac->phy_dev)
134 goto out_get_link;
135
136 if (mac->phy_flags == MTK_PHY_FLAG_ATTACH) {
137 err = genphy_update_link(mac->phy_dev);
138 if (err)
139 goto out_get_link;
140 }
141
142 return mac->phy_dev->link;
143
144out_get_link:
145 return ethtool_op_get_link(dev);
146}
147
148static int mtk_set_ringparam(struct net_device *dev,
149 struct ethtool_ringparam *ring)
150{
151 struct mtk_mac *mac = netdev_priv(dev);
152
153 if ((ring->tx_pending < 2) ||
154 (ring->rx_pending < 2) ||
155 (ring->rx_pending > mac->hw->soc->dma_ring_size) ||
156 (ring->tx_pending > mac->hw->soc->dma_ring_size))
157 return -EINVAL;
158
159 dev->netdev_ops->ndo_stop(dev);
160
161 mac->hw->tx_ring.tx_ring_size = BIT(fls(ring->tx_pending) - 1);
162 mac->hw->rx_ring[0].rx_ring_size = BIT(fls(ring->rx_pending) - 1);
163
164 return dev->netdev_ops->ndo_open(dev);
165}
166
167static void mtk_get_ringparam(struct net_device *dev,
168 struct ethtool_ringparam *ring)
169{
170 struct mtk_mac *mac = netdev_priv(dev);
171
172 ring->rx_max_pending = mac->hw->soc->dma_ring_size;
173 ring->tx_max_pending = mac->hw->soc->dma_ring_size;
174 ring->rx_pending = mac->hw->rx_ring[0].rx_ring_size;
175 ring->tx_pending = mac->hw->tx_ring.tx_ring_size;
176}
177
178static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
179{
180 int i;
181
182 switch (stringset) {
183 case ETH_SS_STATS:
184 for (i = 0; i < MTK_HW_STATS_LEN; i++) {
185 memcpy(data, mtk_ethtool_hw_stats[i].name,
186 ETH_GSTRING_LEN);
187 data += ETH_GSTRING_LEN;
188 }
189 break;
190 }
191}
192
193static int mtk_get_sset_count(struct net_device *dev, int sset)
194{
195 switch (sset) {
196 case ETH_SS_STATS:
197 return MTK_HW_STATS_LEN;
198 default:
199 return -EOPNOTSUPP;
200 }
201}
202
203static void mtk_get_ethtool_stats(struct net_device *dev,
204 struct ethtool_stats *stats, u64 *data)
205{
206 struct mtk_mac *mac = netdev_priv(dev);
207 struct mtk_hw_stats *hwstats = mac->hw_stats;
208 unsigned int start;
209 int i;
210
211 if (netif_running(dev) && netif_device_present(dev)) {
212 if (spin_trylock(&hwstats->stats_lock)) {
213 mtk_stats_update_mac(mac);
214 spin_unlock(&hwstats->stats_lock);
215 }
216 }
217
218 do {
219 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
220 for (i = 0; i < MTK_HW_STATS_LEN; i++)
221 data[i] = ((u64 *)hwstats)[mtk_ethtool_hw_stats[i].idx];
222
223 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
224}
225
226static struct ethtool_ops mtk_ethtool_ops = {
227 .get_link_ksettings = mtk_get_link_ksettings,
228 .set_link_ksettings = mtk_set_link_ksettings,
229 .get_drvinfo = mtk_get_drvinfo,
230 .get_msglevel = mtk_get_msglevel,
231 .set_msglevel = mtk_set_msglevel,
232 .nway_reset = mtk_nway_reset,
233 .get_link = mtk_get_link,
234 .set_ringparam = mtk_set_ringparam,
235 .get_ringparam = mtk_get_ringparam,
236};
237
238void mtk_set_ethtool_ops(struct net_device *netdev)
239{
240 struct mtk_mac *mac = netdev_priv(netdev);
241 struct mtk_soc_data *soc = mac->hw->soc;
242
243 if (soc->reg_table[MTK_REG_MTK_COUNTER_BASE]) {
244 mtk_ethtool_ops.get_strings = mtk_get_strings;
245 mtk_ethtool_ops.get_sset_count = mtk_get_sset_count;
246 mtk_ethtool_ops.get_ethtool_stats = mtk_get_ethtool_stats;
247 }
248
249 netdev->ethtool_ops = &mtk_ethtool_ops;
250}
diff --git a/drivers/staging/mt7621-eth/ethtool.h b/drivers/staging/mt7621-eth/ethtool.h
deleted file mode 100644
index 0071469aea6c..000000000000
--- a/drivers/staging/mt7621-eth/ethtool.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
4 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
6 */
7
8#ifndef MTK_ETHTOOL_H
9#define MTK_ETHTOOL_H
10
11#include <linux/ethtool.h>
12
13void mtk_set_ethtool_ops(struct net_device *netdev);
14
15#endif /* MTK_ETHTOOL_H */
diff --git a/drivers/staging/mt7621-eth/gsw_mt7620.h b/drivers/staging/mt7621-eth/gsw_mt7620.h
deleted file mode 100644
index 70f7e5481952..000000000000
--- a/drivers/staging/mt7621-eth/gsw_mt7620.h
+++ /dev/null
@@ -1,277 +0,0 @@
1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#ifndef _RALINK_GSW_MT7620_H__
16#define _RALINK_GSW_MT7620_H__
17
18#define GSW_REG_PHY_TIMEOUT (5 * HZ)
19
20#define MT7620_GSW_REG_PIAC 0x0004
21
22#define GSW_NUM_VLANS 16
23#define GSW_NUM_VIDS 4096
24#define GSW_NUM_PORTS 7
25#define GSW_PORT6 6
26
27#define GSW_MDIO_ACCESS BIT(31)
28#define GSW_MDIO_READ BIT(19)
29#define GSW_MDIO_WRITE BIT(18)
30#define GSW_MDIO_START BIT(16)
31#define GSW_MDIO_ADDR_SHIFT 20
32#define GSW_MDIO_REG_SHIFT 25
33
34#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
35#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
36#define GSW_REG_SMACCR0 0x3fE4
37#define GSW_REG_SMACCR1 0x3fE8
38#define GSW_REG_CKGCR 0x3ff0
39
40#define GSW_REG_IMR 0x7008
41#define GSW_REG_ISR 0x700c
42#define GSW_REG_GPC1 0x7014
43
44#define SYSC_REG_CHIP_REV_ID 0x0c
45#define SYSC_REG_CFG 0x10
46#define SYSC_REG_CFG1 0x14
47#define RST_CTRL_MCM BIT(2)
48#define SYSC_PAD_RGMII2_MDIO 0x58
49#define SYSC_GPIO_MODE 0x60
50
51#define PORT_IRQ_ST_CHG 0x7f
52
53#define MT7621_ESW_PHY_POLLING 0x0000
54#define MT7620_ESW_PHY_POLLING 0x7000
55
56#define PMCR_IPG BIT(18)
57#define PMCR_MAC_MODE BIT(16)
58#define PMCR_FORCE BIT(15)
59#define PMCR_TX_EN BIT(14)
60#define PMCR_RX_EN BIT(13)
61#define PMCR_BACKOFF BIT(9)
62#define PMCR_BACKPRES BIT(8)
63#define PMCR_RX_FC BIT(5)
64#define PMCR_TX_FC BIT(4)
65#define PMCR_SPEED(_x) (_x << 2)
66#define PMCR_DUPLEX BIT(1)
67#define PMCR_LINK BIT(0)
68
69#define PHY_AN_EN BIT(31)
70#define PHY_PRE_EN BIT(30)
71#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
72
73/* ethernet subsystem config register */
74#define ETHSYS_SYSCFG0 0x14
75/* ethernet subsystem clock register */
76#define ETHSYS_CLKCFG0 0x2c
77#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
78
79/* p5 RGMII wrapper TX clock control register */
80#define MT7530_P5RGMIITXCR 0x7b04
81/* p5 RGMII wrapper RX clock control register */
82#define MT7530_P5RGMIIRXCR 0x7b00
83/* TRGMII TDX ODT registers */
84#define MT7530_TRGMII_TD0_ODT 0x7a54
85#define MT7530_TRGMII_TD1_ODT 0x7a5c
86#define MT7530_TRGMII_TD2_ODT 0x7a64
87#define MT7530_TRGMII_TD3_ODT 0x7a6c
88#define MT7530_TRGMII_TD4_ODT 0x7a74
89#define MT7530_TRGMII_TD5_ODT 0x7a7c
90/* TRGMII TCK ctrl register */
91#define MT7530_TRGMII_TCK_CTRL 0x7a78
92/* TRGMII Tx ctrl register */
93#define MT7530_TRGMII_TXCTRL 0x7a40
94/* port 6 extended control register */
95#define MT7530_P6ECR 0x7830
96/* IO driver control register */
97#define MT7530_IO_DRV_CR 0x7810
98/* top signal control register */
99#define MT7530_TOP_SIG_CTRL 0x7808
100/* modified hwtrap register */
101#define MT7530_MHWTRAP 0x7804
102/* hwtrap status register */
103#define MT7530_HWTRAP 0x7800
104/* status interrupt register */
105#define MT7530_SYS_INT_STS 0x700c
106/* system nterrupt register */
107#define MT7530_SYS_INT_EN 0x7008
108/* system control register */
109#define MT7530_SYS_CTRL 0x7000
110/* port MAC status register */
111#define MT7530_PMSR_P(x) (0x3008 + (x * 0x100))
112/* port MAC control register */
113#define MT7530_PMCR_P(x) (0x3000 + (x * 0x100))
114
115#define MT7621_XTAL_SHIFT 6
116#define MT7621_XTAL_MASK 0x7
117#define MT7621_XTAL_25 6
118#define MT7621_XTAL_40 3
119#define MT7621_MDIO_DRV_MASK (3 << 4)
120#define MT7621_GE1_MODE_MASK (3 << 12)
121
122#define TRGMII_TXCTRL_TXC_INV BIT(30)
123#define P6ECR_INTF_MODE_RGMII BIT(1)
124#define P5RGMIIRXCR_C_ALIGN BIT(8)
125#define P5RGMIIRXCR_DELAY_2 BIT(1)
126#define P5RGMIITXCR_DELAY_2 (BIT(8) | BIT(2))
127
128/* TOP_SIG_CTRL bits */
129#define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
130
131/* MHWTRAP bits */
132#define MHWTRAP_MANUAL BIT(16)
133#define MHWTRAP_P5_MAC_SEL BIT(13)
134#define MHWTRAP_P6_DIS BIT(8)
135#define MHWTRAP_P5_RGMII_MODE BIT(7)
136#define MHWTRAP_P5_DIS BIT(6)
137#define MHWTRAP_PHY_ACCESS BIT(5)
138
139/* HWTRAP bits */
140#define HWTRAP_XTAL_SHIFT 9
141#define HWTRAP_XTAL_MASK 0x3
142
143/* SYS_CTRL bits */
144#define SYS_CTRL_SW_RST BIT(1)
145#define SYS_CTRL_REG_RST BIT(0)
146
147/* PMCR bits */
148#define PMCR_IFG_XMIT_96 BIT(18)
149#define PMCR_MAC_MODE BIT(16)
150#define PMCR_FORCE_MODE BIT(15)
151#define PMCR_TX_EN BIT(14)
152#define PMCR_RX_EN BIT(13)
153#define PMCR_BACK_PRES_EN BIT(9)
154#define PMCR_BACKOFF_EN BIT(8)
155#define PMCR_TX_FC_EN BIT(5)
156#define PMCR_RX_FC_EN BIT(4)
157#define PMCR_FORCE_SPEED_1000 BIT(3)
158#define PMCR_FORCE_FDX BIT(1)
159#define PMCR_FORCE_LNK BIT(0)
160#define PMCR_FIXED_LINK (PMCR_IFG_XMIT_96 | PMCR_MAC_MODE | \
161 PMCR_FORCE_MODE | PMCR_TX_EN | PMCR_RX_EN | \
162 PMCR_BACK_PRES_EN | PMCR_BACKOFF_EN | \
163 PMCR_FORCE_SPEED_1000 | PMCR_FORCE_FDX | \
164 PMCR_FORCE_LNK)
165
166#define PMCR_FIXED_LINK_FC (PMCR_FIXED_LINK | \
167 PMCR_TX_FC_EN | PMCR_RX_FC_EN)
168
169/* TRGMII control registers */
170#define GSW_INTF_MODE 0x390
171#define GSW_TRGMII_TD0_ODT 0x354
172#define GSW_TRGMII_TD1_ODT 0x35c
173#define GSW_TRGMII_TD2_ODT 0x364
174#define GSW_TRGMII_TD3_ODT 0x36c
175#define GSW_TRGMII_TXCTL_ODT 0x374
176#define GSW_TRGMII_TCK_ODT 0x37c
177#define GSW_TRGMII_RCK_CTRL 0x300
178
179#define INTF_MODE_TRGMII BIT(1)
180#define TRGMII_RCK_CTRL_RX_RST BIT(31)
181
182/* Mac control registers */
183#define MTK_MAC_P2_MCR 0x200
184#define MTK_MAC_P1_MCR 0x100
185
186#define MAC_MCR_MAX_RX_2K BIT(29)
187#define MAC_MCR_IPG_CFG (BIT(18) | BIT(16))
188#define MAC_MCR_FORCE_MODE BIT(15)
189#define MAC_MCR_TX_EN BIT(14)
190#define MAC_MCR_RX_EN BIT(13)
191#define MAC_MCR_BACKOFF_EN BIT(9)
192#define MAC_MCR_BACKPR_EN BIT(8)
193#define MAC_MCR_FORCE_RX_FC BIT(5)
194#define MAC_MCR_FORCE_TX_FC BIT(4)
195#define MAC_MCR_SPEED_1000 BIT(3)
196#define MAC_MCR_FORCE_DPX BIT(1)
197#define MAC_MCR_FORCE_LINK BIT(0)
198#define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_2K | MAC_MCR_IPG_CFG | \
199 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \
200 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \
201 MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \
202 MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \
203 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK)
204#define MAC_MCR_FIXED_LINK_FC (MAC_MCR_MAX_RX_2K | MAC_MCR_IPG_CFG | \
205 MAC_MCR_FIXED_LINK)
206
207/* possible XTAL speed */
208#define MT7623_XTAL_40 0
209#define MT7623_XTAL_20 1
210#define MT7623_XTAL_25 3
211
212/* GPIO port control registers */
213#define GPIO_OD33_CTRL8 0x4c0
214#define GPIO_BIAS_CTRL 0xed0
215#define GPIO_DRV_SEL10 0xf00
216
217/* on MT7620 the functio of port 4 can be software configured */
218enum {
219 PORT4_EPHY = 0,
220 PORT4_EXT,
221};
222
223/* struct mt7620_gsw - the structure that holds the SoC specific data
224 * @dev: The Device struct
225 * @base: The base address
226 * @piac_offset: The PIAC base may change depending on SoC
227 * @irq: The IRQ we are using
228 * @port4: The port4 mode on MT7620
229 * @autopoll: Is MDIO autopolling enabled
230 * @ethsys: The ethsys register map
231 * @pctl: The pin control register map
232 * @clk_gsw: The switch clock
233 * @clk_gp1: The gmac1 clock
234 * @clk_gp2: The gmac2 clock
235 * @clk_trgpll: The trgmii pll clock
236 */
237struct mt7620_gsw {
238 struct device *dev;
239 void __iomem *base;
240 u32 piac_offset;
241 int irq;
242 int port4;
243 unsigned long int autopoll;
244
245 struct regmap *ethsys;
246 struct regmap *pctl;
247
248 struct clk *clk_gsw;
249 struct clk *clk_gp1;
250 struct clk *clk_gp2;
251 struct clk *clk_trgpll;
252};
253
254/* switch register I/O wrappers */
255void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned int reg);
256u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned int reg);
257
258/* the callback used by the driver core to bringup the switch */
259int mtk_gsw_init(struct mtk_eth *eth);
260
261/* MDIO access wrappers */
262int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
263int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
264void mt7620_mdio_link_adjust(struct mtk_eth *eth, int port);
265int mt7620_has_carrier(struct mtk_eth *eth);
266void mt7620_print_link_state(struct mtk_eth *eth, int port, int link,
267 int speed, int duplex);
268void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);
269u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);
270void mt7530_mdio_m32(struct mt7620_gsw *gsw, u32 mask, u32 set, u32 reg);
271
272u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
273 u32 phy_register, u32 write_data);
274u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg);
275void mt7620_handle_carrier(struct mtk_eth *eth);
276
277#endif
diff --git a/drivers/staging/mt7621-eth/gsw_mt7621.c b/drivers/staging/mt7621-eth/gsw_mt7621.c
deleted file mode 100644
index 53767b17bad9..000000000000
--- a/drivers/staging/mt7621-eth/gsw_mt7621.c
+++ /dev/null
@@ -1,297 +0,0 @@
1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/platform_device.h>
19#include <linux/of_device.h>
20#include <linux/of_irq.h>
21
22#include <ralink_regs.h>
23
24#include "mtk_eth_soc.h"
25#include "gsw_mt7620.h"
26
27void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned int reg)
28{
29 iowrite32(val, gsw->base + reg);
30}
31EXPORT_SYMBOL_GPL(mtk_switch_w32);
32
33u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned int reg)
34{
35 return ioread32(gsw->base + reg);
36}
37EXPORT_SYMBOL_GPL(mtk_switch_r32);
38
39static irqreturn_t gsw_interrupt_mt7621(int irq, void *_eth)
40{
41 struct mtk_eth *eth = (struct mtk_eth *)_eth;
42 struct mt7620_gsw *gsw = (struct mt7620_gsw *)eth->sw_priv;
43 u32 reg, i;
44
45 reg = mt7530_mdio_r32(gsw, MT7530_SYS_INT_STS);
46
47 for (i = 0; i < 5; i++) {
48 unsigned int link;
49
50 if ((reg & BIT(i)) == 0)
51 continue;
52
53 link = mt7530_mdio_r32(gsw, MT7530_PMSR_P(i)) & 0x1;
54
55 if (link == eth->link[i])
56 continue;
57
58 eth->link[i] = link;
59 if (link)
60 netdev_info(*eth->netdev,
61 "port %d link up\n", i);
62 else
63 netdev_info(*eth->netdev,
64 "port %d link down\n", i);
65 }
66
67 mt7530_mdio_w32(gsw, MT7530_SYS_INT_STS, 0x1f);
68
69 return IRQ_HANDLED;
70}
71
72static void mt7621_hw_init(struct mtk_eth *eth, struct mt7620_gsw *gsw,
73 struct device_node *np)
74{
75 u32 i;
76 u32 val;
77
78 /* hardware reset the switch */
79 mtk_reset(eth, RST_CTRL_MCM);
80 mdelay(10);
81
82 /* reduce RGMII2 PAD driving strength */
83 rt_sysc_m32(MT7621_MDIO_DRV_MASK, 0, SYSC_PAD_RGMII2_MDIO);
84
85 /* gpio mux - RGMII1=Normal mode */
86 rt_sysc_m32(BIT(14), 0, SYSC_GPIO_MODE);
87
88 /* set GMAC1 RGMII mode */
89 rt_sysc_m32(MT7621_GE1_MODE_MASK, 0, SYSC_REG_CFG1);
90
91 /* enable MDIO to control MT7530 */
92 rt_sysc_m32(3 << 12, 0, SYSC_GPIO_MODE);
93
94 /* turn off all PHYs */
95 for (i = 0; i <= 4; i++) {
96 val = _mt7620_mii_read(gsw, i, 0x0);
97 val |= BIT(11);
98 _mt7620_mii_write(gsw, i, 0x0, val);
99 }
100
101 /* reset the switch */
102 mt7530_mdio_w32(gsw, MT7530_SYS_CTRL,
103 SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
104 usleep_range(10, 20);
105
106 if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
107 /* GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536 */
108 mtk_switch_w32(gsw, MAC_MCR_FIXED_LINK, MTK_MAC_P2_MCR);
109 mt7530_mdio_w32(gsw, MT7530_PMCR_P(6), PMCR_FIXED_LINK);
110 } else {
111 /* GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536 */
112 mtk_switch_w32(gsw, MAC_MCR_FIXED_LINK_FC, MTK_MAC_P1_MCR);
113 mt7530_mdio_w32(gsw, MT7530_PMCR_P(6), PMCR_FIXED_LINK_FC);
114 }
115
116 /* GE2, Link down */
117 mtk_switch_w32(gsw, MAC_MCR_FORCE_MODE, MTK_MAC_P2_MCR);
118
119 /* Enable Port 6, P5 as GMAC5, P5 disable */
120 val = mt7530_mdio_r32(gsw, MT7530_MHWTRAP);
121 /* Enable Port 6 */
122 val &= ~MHWTRAP_P6_DIS;
123 /* Disable Port 5 */
124 val |= MHWTRAP_P5_DIS;
125 /* manual override of HW-Trap */
126 val |= MHWTRAP_MANUAL;
127 mt7530_mdio_w32(gsw, MT7530_MHWTRAP, val);
128
129 val = rt_sysc_r32(SYSC_REG_CFG);
130 val = (val >> MT7621_XTAL_SHIFT) & MT7621_XTAL_MASK;
131 if (val < MT7621_XTAL_25 && val >= MT7621_XTAL_40) {
132 /* 40Mhz */
133
134 /* disable MT7530 core clock */
135 _mt7620_mii_write(gsw, 0, 13, 0x1f);
136 _mt7620_mii_write(gsw, 0, 14, 0x410);
137 _mt7620_mii_write(gsw, 0, 13, 0x401f);
138 _mt7620_mii_write(gsw, 0, 14, 0x0);
139
140 /* disable MT7530 PLL */
141 _mt7620_mii_write(gsw, 0, 13, 0x1f);
142 _mt7620_mii_write(gsw, 0, 14, 0x40d);
143 _mt7620_mii_write(gsw, 0, 13, 0x401f);
144 _mt7620_mii_write(gsw, 0, 14, 0x2020);
145
146 /* for MT7530 core clock = 500Mhz */
147 _mt7620_mii_write(gsw, 0, 13, 0x1f);
148 _mt7620_mii_write(gsw, 0, 14, 0x40e);
149 _mt7620_mii_write(gsw, 0, 13, 0x401f);
150 _mt7620_mii_write(gsw, 0, 14, 0x119);
151
152 /* enable MT7530 PLL */
153 _mt7620_mii_write(gsw, 0, 13, 0x1f);
154 _mt7620_mii_write(gsw, 0, 14, 0x40d);
155 _mt7620_mii_write(gsw, 0, 13, 0x401f);
156 _mt7620_mii_write(gsw, 0, 14, 0x2820);
157
158 usleep_range(20, 40);
159
160 /* enable MT7530 core clock */
161 _mt7620_mii_write(gsw, 0, 13, 0x1f);
162 _mt7620_mii_write(gsw, 0, 14, 0x410);
163 _mt7620_mii_write(gsw, 0, 13, 0x401f);
164 }
165
166 /* RGMII */
167 _mt7620_mii_write(gsw, 0, 14, 0x1);
168
169 /* set MT7530 central align */
170 mt7530_mdio_m32(gsw, BIT(0), P6ECR_INTF_MODE_RGMII, MT7530_P6ECR);
171 mt7530_mdio_m32(gsw, TRGMII_TXCTRL_TXC_INV, 0,
172 MT7530_TRGMII_TXCTRL);
173 mt7530_mdio_w32(gsw, MT7530_TRGMII_TCK_CTRL, 0x855);
174
175 /* delay setting for 10/1000M */
176 mt7530_mdio_w32(gsw, MT7530_P5RGMIIRXCR,
177 P5RGMIIRXCR_C_ALIGN | P5RGMIIRXCR_DELAY_2);
178 mt7530_mdio_w32(gsw, MT7530_P5RGMIITXCR, 0x14);
179
180 /* lower Tx Driving*/
181 mt7530_mdio_w32(gsw, MT7530_TRGMII_TD0_ODT, 0x44);
182 mt7530_mdio_w32(gsw, MT7530_TRGMII_TD1_ODT, 0x44);
183 mt7530_mdio_w32(gsw, MT7530_TRGMII_TD2_ODT, 0x44);
184 mt7530_mdio_w32(gsw, MT7530_TRGMII_TD3_ODT, 0x44);
185 mt7530_mdio_w32(gsw, MT7530_TRGMII_TD4_ODT, 0x44);
186 mt7530_mdio_w32(gsw, MT7530_TRGMII_TD5_ODT, 0x44);
187
188 /* turn on all PHYs */
189 for (i = 0; i <= 4; i++) {
190 val = _mt7620_mii_read(gsw, i, 0);
191 val &= ~BIT(11);
192 _mt7620_mii_write(gsw, i, 0, val);
193 }
194
195#define MT7530_NUM_PORTS 8
196#define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
197#define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
198#define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
199#define MT7530_CPU_PORT 6
200
201 /* This is copied from mt7530_apply_config in libreCMC driver */
202 {
203 int i;
204
205 for (i = 0; i < MT7530_NUM_PORTS; i++)
206 mt7530_mdio_w32(gsw, REG_ESW_PORT_PCR(i), 0x00400000);
207
208 mt7530_mdio_w32(gsw, REG_ESW_PORT_PCR(MT7530_CPU_PORT),
209 0x00ff0000);
210
211 for (i = 0; i < MT7530_NUM_PORTS; i++)
212 mt7530_mdio_w32(gsw, REG_ESW_PORT_PVC(i), 0x810000c0);
213 }
214
215 /* enable irq */
216 mt7530_mdio_m32(gsw, 0, 3 << 16, MT7530_TOP_SIG_CTRL);
217 mt7530_mdio_w32(gsw, MT7530_SYS_INT_EN, 0x1f);
218}
219
220static const struct of_device_id mediatek_gsw_match[] = {
221 { .compatible = "mediatek,mt7621-gsw" },
222 {},
223};
224MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
225
226int mtk_gsw_init(struct mtk_eth *eth)
227{
228 struct device_node *np = eth->switch_np;
229 struct platform_device *pdev = of_find_device_by_node(np);
230 struct mt7620_gsw *gsw;
231
232 if (!pdev)
233 return -ENODEV;
234
235 if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
236 return -EINVAL;
237
238 gsw = platform_get_drvdata(pdev);
239 eth->sw_priv = gsw;
240
241 if (!gsw->irq)
242 return -EINVAL;
243
244 request_irq(gsw->irq, gsw_interrupt_mt7621, 0,
245 "gsw", eth);
246 disable_irq(gsw->irq);
247
248 mt7621_hw_init(eth, gsw, np);
249
250 enable_irq(gsw->irq);
251
252 return 0;
253}
254EXPORT_SYMBOL_GPL(mtk_gsw_init);
255
256static int mt7621_gsw_probe(struct platform_device *pdev)
257{
258 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
259 struct mt7620_gsw *gsw;
260
261 gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
262 if (!gsw)
263 return -ENOMEM;
264
265 gsw->base = devm_ioremap_resource(&pdev->dev, res);
266 if (IS_ERR(gsw->base))
267 return PTR_ERR(gsw->base);
268
269 gsw->dev = &pdev->dev;
270 gsw->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
271
272 platform_set_drvdata(pdev, gsw);
273
274 return 0;
275}
276
277static int mt7621_gsw_remove(struct platform_device *pdev)
278{
279 platform_set_drvdata(pdev, NULL);
280
281 return 0;
282}
283
284static struct platform_driver gsw_driver = {
285 .probe = mt7621_gsw_probe,
286 .remove = mt7621_gsw_remove,
287 .driver = {
288 .name = "mt7621-gsw",
289 .of_match_table = mediatek_gsw_match,
290 },
291};
292
293module_platform_driver(gsw_driver);
294
295MODULE_LICENSE("GPL");
296MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
297MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7621 SoC");
diff --git a/drivers/staging/mt7621-eth/mdio.c b/drivers/staging/mt7621-eth/mdio.c
deleted file mode 100644
index 5fea6a447eed..000000000000
--- a/drivers/staging/mt7621-eth/mdio.c
+++ /dev/null
@@ -1,275 +0,0 @@
1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
6 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
7 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
8 */
9
10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/phy.h>
13#include <linux/of_net.h>
14#include <linux/of_mdio.h>
15
16#include "mtk_eth_soc.h"
17#include "mdio.h"
18
19static int mtk_mdio_reset(struct mii_bus *bus)
20{
21 /* TODO */
22 return 0;
23}
24
25static void mtk_phy_link_adjust(struct net_device *dev)
26{
27 struct mtk_eth *eth = netdev_priv(dev);
28 unsigned long flags;
29 int i;
30
31 spin_lock_irqsave(&eth->phy->lock, flags);
32 for (i = 0; i < 8; i++) {
33 if (eth->phy->phy_node[i]) {
34 struct phy_device *phydev = eth->phy->phy[i];
35 int status_change = 0;
36
37 if (phydev->link)
38 if (eth->phy->duplex[i] != phydev->duplex ||
39 eth->phy->speed[i] != phydev->speed)
40 status_change = 1;
41
42 if (phydev->link != eth->link[i])
43 status_change = 1;
44
45 switch (phydev->speed) {
46 case SPEED_1000:
47 case SPEED_100:
48 case SPEED_10:
49 eth->link[i] = phydev->link;
50 eth->phy->duplex[i] = phydev->duplex;
51 eth->phy->speed[i] = phydev->speed;
52
53 if (status_change &&
54 eth->soc->mdio_adjust_link)
55 eth->soc->mdio_adjust_link(eth, i);
56 break;
57 }
58 }
59 }
60 spin_unlock_irqrestore(&eth->phy->lock, flags);
61}
62
63int mtk_connect_phy_node(struct mtk_eth *eth, struct mtk_mac *mac,
64 struct device_node *phy_node)
65{
66 const __be32 *_port = NULL;
67 struct phy_device *phydev;
68 int phy_mode, port;
69
70 _port = of_get_property(phy_node, "reg", NULL);
71
72 if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
73 pr_err("%pOFn: invalid port id\n", phy_node);
74 return -EINVAL;
75 }
76 port = be32_to_cpu(*_port);
77 phy_mode = of_get_phy_mode(phy_node);
78 if (phy_mode < 0) {
79 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
80 eth->phy->phy_node[port] = NULL;
81 return -EINVAL;
82 }
83
84 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
85 mtk_phy_link_adjust, 0, phy_mode);
86 if (!phydev) {
87 dev_err(eth->dev, "could not connect to PHY\n");
88 eth->phy->phy_node[port] = NULL;
89 return -ENODEV;
90 }
91
92 phydev->supported &= PHY_1000BT_FEATURES;
93 phydev->advertising = phydev->supported;
94
95 dev_info(eth->dev,
96 "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
97 port, phydev_name(phydev), phydev->phy_id,
98 phydev->drv->name);
99
100 eth->phy->phy[port] = phydev;
101 eth->link[port] = 0;
102
103 return 0;
104}
105
106static void phy_init(struct mtk_eth *eth, struct mtk_mac *mac,
107 struct phy_device *phy)
108{
109 phy_attach(eth->netdev[mac->id], phydev_name(phy),
110 PHY_INTERFACE_MODE_MII);
111
112 phy->autoneg = AUTONEG_ENABLE;
113 phy->speed = 0;
114 phy->duplex = 0;
115 phy_set_max_speed(phy, SPEED_100);
116 phy->advertising = phy->supported | ADVERTISED_Autoneg;
117
118 phy_start_aneg(phy);
119}
120
121static int mtk_phy_connect(struct mtk_mac *mac)
122{
123 struct mtk_eth *eth = mac->hw;
124 int i;
125
126 for (i = 0; i < 8; i++) {
127 if (eth->phy->phy_node[i]) {
128 if (!mac->phy_dev) {
129 mac->phy_dev = eth->phy->phy[i];
130 mac->phy_flags = MTK_PHY_FLAG_PORT;
131 }
132 } else if (eth->mii_bus) {
133 struct phy_device *phy;
134
135 phy = mdiobus_get_phy(eth->mii_bus, i);
136 if (phy) {
137 phy_init(eth, mac, phy);
138 if (!mac->phy_dev) {
139 mac->phy_dev = phy;
140 mac->phy_flags = MTK_PHY_FLAG_ATTACH;
141 }
142 }
143 }
144 }
145
146 return 0;
147}
148
149static void mtk_phy_disconnect(struct mtk_mac *mac)
150{
151 struct mtk_eth *eth = mac->hw;
152 unsigned long flags;
153 int i;
154
155 for (i = 0; i < 8; i++)
156 if (eth->phy->phy_fixed[i]) {
157 spin_lock_irqsave(&eth->phy->lock, flags);
158 eth->link[i] = 0;
159 if (eth->soc->mdio_adjust_link)
160 eth->soc->mdio_adjust_link(eth, i);
161 spin_unlock_irqrestore(&eth->phy->lock, flags);
162 } else if (eth->phy->phy[i]) {
163 phy_disconnect(eth->phy->phy[i]);
164 } else if (eth->mii_bus) {
165 struct phy_device *phy =
166 mdiobus_get_phy(eth->mii_bus, i);
167
168 if (phy)
169 phy_detach(phy);
170 }
171}
172
173static void mtk_phy_start(struct mtk_mac *mac)
174{
175 struct mtk_eth *eth = mac->hw;
176 unsigned long flags;
177 int i;
178
179 for (i = 0; i < 8; i++) {
180 if (eth->phy->phy_fixed[i]) {
181 spin_lock_irqsave(&eth->phy->lock, flags);
182 eth->link[i] = 1;
183 if (eth->soc->mdio_adjust_link)
184 eth->soc->mdio_adjust_link(eth, i);
185 spin_unlock_irqrestore(&eth->phy->lock, flags);
186 } else if (eth->phy->phy[i]) {
187 phy_start(eth->phy->phy[i]);
188 }
189 }
190}
191
192static void mtk_phy_stop(struct mtk_mac *mac)
193{
194 struct mtk_eth *eth = mac->hw;
195 unsigned long flags;
196 int i;
197
198 for (i = 0; i < 8; i++)
199 if (eth->phy->phy_fixed[i]) {
200 spin_lock_irqsave(&eth->phy->lock, flags);
201 eth->link[i] = 0;
202 if (eth->soc->mdio_adjust_link)
203 eth->soc->mdio_adjust_link(eth, i);
204 spin_unlock_irqrestore(&eth->phy->lock, flags);
205 } else if (eth->phy->phy[i]) {
206 phy_stop(eth->phy->phy[i]);
207 }
208}
209
210static struct mtk_phy phy_ralink = {
211 .connect = mtk_phy_connect,
212 .disconnect = mtk_phy_disconnect,
213 .start = mtk_phy_start,
214 .stop = mtk_phy_stop,
215};
216
217int mtk_mdio_init(struct mtk_eth *eth)
218{
219 struct device_node *mii_np;
220 int err;
221
222 if (!eth->soc->mdio_read || !eth->soc->mdio_write)
223 return 0;
224
225 spin_lock_init(&phy_ralink.lock);
226 eth->phy = &phy_ralink;
227
228 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
229 if (!mii_np) {
230 dev_err(eth->dev, "no %s child node found", "mdio-bus");
231 return -ENODEV;
232 }
233
234 if (!of_device_is_available(mii_np)) {
235 err = 0;
236 goto err_put_node;
237 }
238
239 eth->mii_bus = mdiobus_alloc();
240 if (!eth->mii_bus) {
241 err = -ENOMEM;
242 goto err_put_node;
243 }
244
245 eth->mii_bus->name = "mdio";
246 eth->mii_bus->read = eth->soc->mdio_read;
247 eth->mii_bus->write = eth->soc->mdio_write;
248 eth->mii_bus->reset = mtk_mdio_reset;
249 eth->mii_bus->priv = eth;
250 eth->mii_bus->parent = eth->dev;
251
252 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
253 err = of_mdiobus_register(eth->mii_bus, mii_np);
254 if (err)
255 goto err_free_bus;
256
257 return 0;
258
259err_free_bus:
260 kfree(eth->mii_bus);
261err_put_node:
262 of_node_put(mii_np);
263 eth->mii_bus = NULL;
264 return err;
265}
266
267void mtk_mdio_cleanup(struct mtk_eth *eth)
268{
269 if (!eth->mii_bus)
270 return;
271
272 mdiobus_unregister(eth->mii_bus);
273 of_node_put(eth->mii_bus->dev.of_node);
274 kfree(eth->mii_bus);
275}
diff --git a/drivers/staging/mt7621-eth/mdio.h b/drivers/staging/mt7621-eth/mdio.h
deleted file mode 100644
index b14e23842a01..000000000000
--- a/drivers/staging/mt7621-eth/mdio.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#ifndef _RALINK_MDIO_H__
16#define _RALINK_MDIO_H__
17
18#ifdef CONFIG_NET_MEDIATEK_MDIO
19int mtk_mdio_init(struct mtk_eth *eth);
20void mtk_mdio_cleanup(struct mtk_eth *eth);
21int mtk_connect_phy_node(struct mtk_eth *eth, struct mtk_mac *mac,
22 struct device_node *phy_node);
23#else
24static inline int mtk_mdio_init(struct mtk_eth *eth) { return 0; }
25static inline void mtk_mdio_cleanup(struct mtk_eth *eth) {}
26#endif
27#endif
diff --git a/drivers/staging/mt7621-eth/mdio_mt7620.c b/drivers/staging/mt7621-eth/mdio_mt7620.c
deleted file mode 100644
index ced605c2914e..000000000000
--- a/drivers/staging/mt7621-eth/mdio_mt7620.c
+++ /dev/null
@@ -1,173 +0,0 @@
1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18
19#include "mtk_eth_soc.h"
20#include "gsw_mt7620.h"
21#include "mdio.h"
22
23static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
24{
25 unsigned long t_start = jiffies;
26
27 while (1) {
28 if (!(mtk_switch_r32(gsw,
29 gsw->piac_offset + MT7620_GSW_REG_PIAC) &
30 GSW_MDIO_ACCESS))
31 return 0;
32 if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT))
33 break;
34 }
35
36 dev_err(gsw->dev, "mdio: MDIO timeout\n");
37 return -1;
38}
39
40u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
41 u32 phy_register, u32 write_data)
42{
43 if (mt7620_mii_busy_wait(gsw))
44 return -1;
45
46 write_data &= 0xffff;
47
48 mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
49 (phy_register << GSW_MDIO_REG_SHIFT) |
50 (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
51 MT7620_GSW_REG_PIAC);
52
53 if (mt7620_mii_busy_wait(gsw))
54 return -1;
55
56 return 0;
57}
58EXPORT_SYMBOL_GPL(_mt7620_mii_write);
59
60u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
61{
62 u32 d;
63
64 if (mt7620_mii_busy_wait(gsw))
65 return 0xffff;
66
67 mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
68 (phy_reg << GSW_MDIO_REG_SHIFT) |
69 (phy_addr << GSW_MDIO_ADDR_SHIFT),
70 MT7620_GSW_REG_PIAC);
71
72 if (mt7620_mii_busy_wait(gsw))
73 return 0xffff;
74
75 d = mtk_switch_r32(gsw, MT7620_GSW_REG_PIAC) & 0xffff;
76
77 return d;
78}
79EXPORT_SYMBOL_GPL(_mt7620_mii_read);
80
81int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
82{
83 struct mtk_eth *eth = bus->priv;
84 struct mt7620_gsw *gsw = (struct mt7620_gsw *)eth->sw_priv;
85
86 return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
87}
88
89int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
90{
91 struct mtk_eth *eth = bus->priv;
92 struct mt7620_gsw *gsw = (struct mt7620_gsw *)eth->sw_priv;
93
94 return _mt7620_mii_read(gsw, phy_addr, phy_reg);
95}
96
97void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val)
98{
99 _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
100 _mt7620_mii_write(gsw, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
101 _mt7620_mii_write(gsw, 0x1f, 0x10, val >> 16);
102}
103EXPORT_SYMBOL_GPL(mt7530_mdio_w32);
104
105u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg)
106{
107 u16 high, low;
108
109 _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
110 low = _mt7620_mii_read(gsw, 0x1f, (reg >> 2) & 0xf);
111 high = _mt7620_mii_read(gsw, 0x1f, 0x10);
112
113 return (high << 16) | (low & 0xffff);
114}
115EXPORT_SYMBOL_GPL(mt7530_mdio_r32);
116
117void mt7530_mdio_m32(struct mt7620_gsw *gsw, u32 mask, u32 set, u32 reg)
118{
119 u32 val = mt7530_mdio_r32(gsw, reg);
120
121 val &= ~mask;
122 val |= set;
123 mt7530_mdio_w32(gsw, reg, val);
124}
125EXPORT_SYMBOL_GPL(mt7530_mdio_m32);
126
127static unsigned char *mtk_speed_str(int speed)
128{
129 switch (speed) {
130 case 2:
131 case SPEED_1000:
132 return "1000";
133 case 1:
134 case SPEED_100:
135 return "100";
136 case 0:
137 case SPEED_10:
138 return "10";
139 }
140
141 return "? ";
142}
143
144int mt7620_has_carrier(struct mtk_eth *eth)
145{
146 struct mt7620_gsw *gsw = (struct mt7620_gsw *)eth->sw_priv;
147 int i;
148
149 for (i = 0; i < GSW_PORT6; i++)
150 if (mt7530_mdio_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
151 return 1;
152 return 0;
153}
154
155void mt7620_print_link_state(struct mtk_eth *eth, int port, int link,
156 int speed, int duplex)
157{
158 struct mt7620_gsw *gsw = eth->sw_priv;
159
160 if (link)
161 dev_info(gsw->dev, "port %d link up (%sMbps/%s duplex)\n",
162 port, mtk_speed_str(speed),
163 (duplex) ? "Full" : "Half");
164 else
165 dev_info(gsw->dev, "port %d link down\n", port);
166}
167
168void mt7620_mdio_link_adjust(struct mtk_eth *eth, int port)
169{
170 mt7620_print_link_state(eth, port, eth->link[port],
171 eth->phy->speed[port],
172 (eth->phy->duplex[port] == DUPLEX_FULL));
173}
diff --git a/drivers/staging/mt7621-eth/mtk_eth_soc.c b/drivers/staging/mt7621-eth/mtk_eth_soc.c
deleted file mode 100644
index 6027b19f7bc2..000000000000
--- a/drivers/staging/mt7621-eth/mtk_eth_soc.c
+++ /dev/null
@@ -1,2176 +0,0 @@
1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/dma-mapping.h>
19#include <linux/init.h>
20#include <linux/skbuff.h>
21#include <linux/etherdevice.h>
22#include <linux/ethtool.h>
23#include <linux/platform_device.h>
24#include <linux/of_device.h>
25#include <linux/mfd/syscon.h>
26#include <linux/clk.h>
27#include <linux/of_net.h>
28#include <linux/of_mdio.h>
29#include <linux/if_vlan.h>
30#include <linux/reset.h>
31#include <linux/tcp.h>
32#include <linux/io.h>
33#include <linux/bug.h>
34#include <linux/regmap.h>
35
36#include "mtk_eth_soc.h"
37#include "mdio.h"
38#include "ethtool.h"
39
40#define MAX_RX_LENGTH 1536
41#define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
42#define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
43#define DMA_DUMMY_DESC 0xffffffff
44#define MTK_DEFAULT_MSG_ENABLE \
45 (NETIF_MSG_DRV | \
46 NETIF_MSG_PROBE | \
47 NETIF_MSG_LINK | \
48 NETIF_MSG_TIMER | \
49 NETIF_MSG_IFDOWN | \
50 NETIF_MSG_IFUP | \
51 NETIF_MSG_RX_ERR | \
52 NETIF_MSG_TX_ERR)
53
54#define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
55#define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
56#define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
57
58#define SYSC_REG_RSTCTRL 0x34
59
60static int mtk_msg_level = -1;
61module_param_named(msg_level, mtk_msg_level, int, 0);
62MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
63
64static const u16 mtk_reg_table_default[MTK_REG_COUNT] = {
65 [MTK_REG_PDMA_GLO_CFG] = MTK_PDMA_GLO_CFG,
66 [MTK_REG_PDMA_RST_CFG] = MTK_PDMA_RST_CFG,
67 [MTK_REG_DLY_INT_CFG] = MTK_DLY_INT_CFG,
68 [MTK_REG_TX_BASE_PTR0] = MTK_TX_BASE_PTR0,
69 [MTK_REG_TX_MAX_CNT0] = MTK_TX_MAX_CNT0,
70 [MTK_REG_TX_CTX_IDX0] = MTK_TX_CTX_IDX0,
71 [MTK_REG_TX_DTX_IDX0] = MTK_TX_DTX_IDX0,
72 [MTK_REG_RX_BASE_PTR0] = MTK_RX_BASE_PTR0,
73 [MTK_REG_RX_MAX_CNT0] = MTK_RX_MAX_CNT0,
74 [MTK_REG_RX_CALC_IDX0] = MTK_RX_CALC_IDX0,
75 [MTK_REG_RX_DRX_IDX0] = MTK_RX_DRX_IDX0,
76 [MTK_REG_MTK_INT_ENABLE] = MTK_INT_ENABLE,
77 [MTK_REG_MTK_INT_STATUS] = MTK_INT_STATUS,
78 [MTK_REG_MTK_DMA_VID_BASE] = MTK_DMA_VID0,
79 [MTK_REG_MTK_COUNTER_BASE] = MTK_GDMA1_TX_GBCNT,
80 [MTK_REG_MTK_RST_GL] = MTK_RST_GL,
81};
82
83static const u16 *mtk_reg_table = mtk_reg_table_default;
84
85void mtk_w32(struct mtk_eth *eth, u32 val, unsigned int reg)
86{
87 __raw_writel(val, eth->base + reg);
88}
89
90u32 mtk_r32(struct mtk_eth *eth, unsigned int reg)
91{
92 return __raw_readl(eth->base + reg);
93}
94
95static void mtk_reg_w32(struct mtk_eth *eth, u32 val, enum mtk_reg reg)
96{
97 mtk_w32(eth, val, mtk_reg_table[reg]);
98}
99
100static u32 mtk_reg_r32(struct mtk_eth *eth, enum mtk_reg reg)
101{
102 return mtk_r32(eth, mtk_reg_table[reg]);
103}
104
105/* these bits are also exposed via the reset-controller API. however the switch
106 * and FE need to be brought out of reset in the exakt same moemtn and the
107 * reset-controller api does not provide this feature yet. Do the reset manually
108 * until we fixed the reset-controller api to be able to do this
109 */
110void mtk_reset(struct mtk_eth *eth, u32 reset_bits)
111{
112 u32 val;
113
114 regmap_read(eth->ethsys, SYSC_REG_RSTCTRL, &val);
115 val |= reset_bits;
116 regmap_write(eth->ethsys, SYSC_REG_RSTCTRL, val);
117 usleep_range(10, 20);
118 val &= ~reset_bits;
119 regmap_write(eth->ethsys, SYSC_REG_RSTCTRL, val);
120 usleep_range(10, 20);
121}
122EXPORT_SYMBOL(mtk_reset);
123
124static inline void mtk_irq_ack(struct mtk_eth *eth, u32 mask)
125{
126 if (eth->soc->dma_type & MTK_PDMA)
127 mtk_reg_w32(eth, mask, MTK_REG_MTK_INT_STATUS);
128 if (eth->soc->dma_type & MTK_QDMA)
129 mtk_w32(eth, mask, MTK_QMTK_INT_STATUS);
130}
131
132static inline u32 mtk_irq_pending(struct mtk_eth *eth)
133{
134 u32 status = 0;
135
136 if (eth->soc->dma_type & MTK_PDMA)
137 status |= mtk_reg_r32(eth, MTK_REG_MTK_INT_STATUS);
138 if (eth->soc->dma_type & MTK_QDMA)
139 status |= mtk_r32(eth, MTK_QMTK_INT_STATUS);
140
141 return status;
142}
143
144static void mtk_irq_ack_status(struct mtk_eth *eth, u32 mask)
145{
146 u32 status_reg = MTK_REG_MTK_INT_STATUS;
147
148 if (mtk_reg_table[MTK_REG_MTK_INT_STATUS2])
149 status_reg = MTK_REG_MTK_INT_STATUS2;
150
151 mtk_reg_w32(eth, mask, status_reg);
152}
153
154static u32 mtk_irq_pending_status(struct mtk_eth *eth)
155{
156 u32 status_reg = MTK_REG_MTK_INT_STATUS;
157
158 if (mtk_reg_table[MTK_REG_MTK_INT_STATUS2])
159 status_reg = MTK_REG_MTK_INT_STATUS2;
160
161 return mtk_reg_r32(eth, status_reg);
162}
163
164static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
165{
166 u32 val;
167
168 if (eth->soc->dma_type & MTK_PDMA) {
169 val = mtk_reg_r32(eth, MTK_REG_MTK_INT_ENABLE);
170 mtk_reg_w32(eth, val & ~mask, MTK_REG_MTK_INT_ENABLE);
171 /* flush write */
172 mtk_reg_r32(eth, MTK_REG_MTK_INT_ENABLE);
173 }
174 if (eth->soc->dma_type & MTK_QDMA) {
175 val = mtk_r32(eth, MTK_QMTK_INT_ENABLE);
176 mtk_w32(eth, val & ~mask, MTK_QMTK_INT_ENABLE);
177 /* flush write */
178 mtk_r32(eth, MTK_QMTK_INT_ENABLE);
179 }
180}
181
182static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
183{
184 u32 val;
185
186 if (eth->soc->dma_type & MTK_PDMA) {
187 val = mtk_reg_r32(eth, MTK_REG_MTK_INT_ENABLE);
188 mtk_reg_w32(eth, val | mask, MTK_REG_MTK_INT_ENABLE);
189 /* flush write */
190 mtk_reg_r32(eth, MTK_REG_MTK_INT_ENABLE);
191 }
192 if (eth->soc->dma_type & MTK_QDMA) {
193 val = mtk_r32(eth, MTK_QMTK_INT_ENABLE);
194 mtk_w32(eth, val | mask, MTK_QMTK_INT_ENABLE);
195 /* flush write */
196 mtk_r32(eth, MTK_QMTK_INT_ENABLE);
197 }
198}
199
200static inline u32 mtk_irq_enabled(struct mtk_eth *eth)
201{
202 u32 enabled = 0;
203
204 if (eth->soc->dma_type & MTK_PDMA)
205 enabled |= mtk_reg_r32(eth, MTK_REG_MTK_INT_ENABLE);
206 if (eth->soc->dma_type & MTK_QDMA)
207 enabled |= mtk_r32(eth, MTK_QMTK_INT_ENABLE);
208
209 return enabled;
210}
211
212static inline void mtk_hw_set_macaddr(struct mtk_mac *mac,
213 unsigned char *macaddr)
214{
215 unsigned long flags;
216
217 spin_lock_irqsave(&mac->hw->page_lock, flags);
218 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], MTK_GDMA1_MAC_ADRH);
219 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
220 (macaddr[4] << 8) | macaddr[5],
221 MTK_GDMA1_MAC_ADRL);
222 spin_unlock_irqrestore(&mac->hw->page_lock, flags);
223}
224
225static int mtk_set_mac_address(struct net_device *dev, void *p)
226{
227 int ret = eth_mac_addr(dev, p);
228 struct mtk_mac *mac = netdev_priv(dev);
229 struct mtk_eth *eth = mac->hw;
230
231 if (ret)
232 return ret;
233
234 if (eth->soc->set_mac)
235 eth->soc->set_mac(mac, dev->dev_addr);
236 else
237 mtk_hw_set_macaddr(mac, p);
238
239 return 0;
240}
241
242static inline int mtk_max_frag_size(int mtu)
243{
244 /* make sure buf_size will be at least MAX_RX_LENGTH */
245 if (mtu + MTK_RX_ETH_HLEN < MAX_RX_LENGTH)
246 mtu = MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
247
248 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
249 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
250}
251
252static inline int mtk_max_buf_size(int frag_size)
253{
254 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
255 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
256
257 WARN_ON(buf_size < MAX_RX_LENGTH);
258
259 return buf_size;
260}
261
262static inline void mtk_get_rxd(struct mtk_rx_dma *rxd,
263 struct mtk_rx_dma *dma_rxd)
264{
265 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
266 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
267 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
268 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
269}
270
271static inline void mtk_set_txd_pdma(struct mtk_tx_dma *txd,
272 struct mtk_tx_dma *dma_txd)
273{
274 WRITE_ONCE(dma_txd->txd1, txd->txd1);
275 WRITE_ONCE(dma_txd->txd3, txd->txd3);
276 WRITE_ONCE(dma_txd->txd4, txd->txd4);
277 /* clean dma done flag last */
278 WRITE_ONCE(dma_txd->txd2, txd->txd2);
279}
280
281static void mtk_clean_rx(struct mtk_eth *eth, struct mtk_rx_ring *ring)
282{
283 int i;
284
285 if (ring->rx_data && ring->rx_dma) {
286 for (i = 0; i < ring->rx_ring_size; i++) {
287 if (!ring->rx_data[i])
288 continue;
289 if (!ring->rx_dma[i].rxd1)
290 continue;
291 dma_unmap_single(eth->dev,
292 ring->rx_dma[i].rxd1,
293 ring->rx_buf_size,
294 DMA_FROM_DEVICE);
295 skb_free_frag(ring->rx_data[i]);
296 }
297 kfree(ring->rx_data);
298 ring->rx_data = NULL;
299 }
300
301 if (ring->rx_dma) {
302 dma_free_coherent(eth->dev,
303 ring->rx_ring_size * sizeof(*ring->rx_dma),
304 ring->rx_dma,
305 ring->rx_phys);
306 ring->rx_dma = NULL;
307 }
308}
309
310static int mtk_dma_rx_alloc(struct mtk_eth *eth, struct mtk_rx_ring *ring)
311{
312 int i, pad = 0;
313
314 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
315 ring->rx_buf_size = mtk_max_buf_size(ring->frag_size);
316 ring->rx_ring_size = eth->soc->dma_ring_size;
317 ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
318 GFP_KERNEL);
319 if (!ring->rx_data)
320 goto no_rx_mem;
321
322 for (i = 0; i < ring->rx_ring_size; i++) {
323 ring->rx_data[i] = netdev_alloc_frag(ring->frag_size);
324 if (!ring->rx_data[i])
325 goto no_rx_mem;
326 }
327
328 ring->rx_dma =
329 dma_alloc_coherent(eth->dev,
330 ring->rx_ring_size * sizeof(*ring->rx_dma),
331 &ring->rx_phys, GFP_ATOMIC | __GFP_ZERO);
332 if (!ring->rx_dma)
333 goto no_rx_mem;
334
335 if (!eth->soc->rx_2b_offset)
336 pad = NET_IP_ALIGN;
337
338 for (i = 0; i < ring->rx_ring_size; i++) {
339 dma_addr_t dma_addr = dma_map_single(eth->dev,
340 ring->rx_data[i] + NET_SKB_PAD + pad,
341 ring->rx_buf_size,
342 DMA_FROM_DEVICE);
343 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
344 goto no_rx_mem;
345 ring->rx_dma[i].rxd1 = (unsigned int)dma_addr;
346
347 if (eth->soc->rx_sg_dma)
348 ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
349 else
350 ring->rx_dma[i].rxd2 = RX_DMA_LSO;
351 }
352 ring->rx_calc_idx = ring->rx_ring_size - 1;
353 /* make sure that all changes to the dma ring are flushed before we
354 * continue
355 */
356 wmb();
357
358 return 0;
359
360no_rx_mem:
361 return -ENOMEM;
362}
363
364static void mtk_txd_unmap(struct device *dev, struct mtk_tx_buf *tx_buf)
365{
366 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
367 dma_unmap_single(dev,
368 dma_unmap_addr(tx_buf, dma_addr0),
369 dma_unmap_len(tx_buf, dma_len0),
370 DMA_TO_DEVICE);
371 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
372 dma_unmap_page(dev,
373 dma_unmap_addr(tx_buf, dma_addr0),
374 dma_unmap_len(tx_buf, dma_len0),
375 DMA_TO_DEVICE);
376 }
377 if (tx_buf->flags & MTK_TX_FLAGS_PAGE1)
378 dma_unmap_page(dev,
379 dma_unmap_addr(tx_buf, dma_addr1),
380 dma_unmap_len(tx_buf, dma_len1),
381 DMA_TO_DEVICE);
382
383 tx_buf->flags = 0;
384 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *)DMA_DUMMY_DESC))
385 dev_kfree_skb_any(tx_buf->skb);
386 tx_buf->skb = NULL;
387}
388
389static void mtk_pdma_tx_clean(struct mtk_eth *eth)
390{
391 struct mtk_tx_ring *ring = &eth->tx_ring;
392 int i;
393
394 if (ring->tx_buf) {
395 for (i = 0; i < ring->tx_ring_size; i++)
396 mtk_txd_unmap(eth->dev, &ring->tx_buf[i]);
397 kfree(ring->tx_buf);
398 ring->tx_buf = NULL;
399 }
400
401 if (ring->tx_dma) {
402 dma_free_coherent(eth->dev,
403 ring->tx_ring_size * sizeof(*ring->tx_dma),
404 ring->tx_dma,
405 ring->tx_phys);
406 ring->tx_dma = NULL;
407 }
408}
409
410static void mtk_qdma_tx_clean(struct mtk_eth *eth)
411{
412 struct mtk_tx_ring *ring = &eth->tx_ring;
413 int i;
414
415 if (ring->tx_buf) {
416 for (i = 0; i < ring->tx_ring_size; i++)
417 mtk_txd_unmap(eth->dev, &ring->tx_buf[i]);
418 kfree(ring->tx_buf);
419 ring->tx_buf = NULL;
420 }
421
422 if (ring->tx_dma) {
423 dma_free_coherent(eth->dev,
424 ring->tx_ring_size * sizeof(*ring->tx_dma),
425 ring->tx_dma,
426 ring->tx_phys);
427 ring->tx_dma = NULL;
428 }
429}
430
431void mtk_stats_update_mac(struct mtk_mac *mac)
432{
433 struct mtk_hw_stats *hw_stats = mac->hw_stats;
434 unsigned int base = mtk_reg_table[MTK_REG_MTK_COUNTER_BASE];
435 u64 stats;
436
437 base += hw_stats->reg_offset;
438
439 u64_stats_update_begin(&hw_stats->syncp);
440
441 if (mac->hw->soc->new_stats) {
442 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
443 stats = mtk_r32(mac->hw, base + 0x04);
444 if (stats)
445 hw_stats->rx_bytes += (stats << 32);
446 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
447 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
448 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
449 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
450 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
451 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
452 hw_stats->rx_flow_control_packets +=
453 mtk_r32(mac->hw, base + 0x24);
454 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
455 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
456 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
457 stats = mtk_r32(mac->hw, base + 0x34);
458 if (stats)
459 hw_stats->tx_bytes += (stats << 32);
460 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
461 } else {
462 hw_stats->tx_bytes += mtk_r32(mac->hw, base);
463 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x04);
464 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x08);
465 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x0c);
466 hw_stats->rx_bytes += mtk_r32(mac->hw, base + 0x20);
467 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x24);
468 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x28);
469 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x2c);
470 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x30);
471 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x34);
472 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x38);
473 hw_stats->rx_flow_control_packets +=
474 mtk_r32(mac->hw, base + 0x3c);
475 }
476
477 u64_stats_update_end(&hw_stats->syncp);
478}
479
480static void mtk_get_stats64(struct net_device *dev,
481 struct rtnl_link_stats64 *storage)
482{
483 struct mtk_mac *mac = netdev_priv(dev);
484 struct mtk_hw_stats *hw_stats = mac->hw_stats;
485 unsigned int base = mtk_reg_table[MTK_REG_MTK_COUNTER_BASE];
486 unsigned int start;
487
488 if (!base) {
489 netdev_stats_to_stats64(storage, &dev->stats);
490 return;
491 }
492
493 if (netif_running(dev) && netif_device_present(dev)) {
494 if (spin_trylock(&hw_stats->stats_lock)) {
495 mtk_stats_update_mac(mac);
496 spin_unlock(&hw_stats->stats_lock);
497 }
498 }
499
500 do {
501 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
502 storage->rx_packets = hw_stats->rx_packets;
503 storage->tx_packets = hw_stats->tx_packets;
504 storage->rx_bytes = hw_stats->rx_bytes;
505 storage->tx_bytes = hw_stats->tx_bytes;
506 storage->collisions = hw_stats->tx_collisions;
507 storage->rx_length_errors = hw_stats->rx_short_errors +
508 hw_stats->rx_long_errors;
509 storage->rx_over_errors = hw_stats->rx_overflow;
510 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
511 storage->rx_errors = hw_stats->rx_checksum_errors;
512 storage->tx_aborted_errors = hw_stats->tx_skip;
513 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
514
515 storage->tx_errors = dev->stats.tx_errors;
516 storage->rx_dropped = dev->stats.rx_dropped;
517 storage->tx_dropped = dev->stats.tx_dropped;
518}
519
520static int mtk_vlan_rx_add_vid(struct net_device *dev,
521 __be16 proto, u16 vid)
522{
523 struct mtk_mac *mac = netdev_priv(dev);
524 struct mtk_eth *eth = mac->hw;
525 u32 idx = (vid & 0xf);
526 u32 vlan_cfg;
527
528 if (!((mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE]) &&
529 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
530 return 0;
531
532 if (test_bit(idx, &eth->vlan_map)) {
533 netdev_warn(dev, "disable tx vlan offload\n");
534 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
535 netdev_update_features(dev);
536 } else {
537 vlan_cfg = mtk_r32(eth,
538 mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE] +
539 ((idx >> 1) << 2));
540 if (idx & 0x1) {
541 vlan_cfg &= 0xffff;
542 vlan_cfg |= (vid << 16);
543 } else {
544 vlan_cfg &= 0xffff0000;
545 vlan_cfg |= vid;
546 }
547 mtk_w32(eth,
548 vlan_cfg, mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE] +
549 ((idx >> 1) << 2));
550 set_bit(idx, &eth->vlan_map);
551 }
552
553 return 0;
554}
555
556static int mtk_vlan_rx_kill_vid(struct net_device *dev,
557 __be16 proto, u16 vid)
558{
559 struct mtk_mac *mac = netdev_priv(dev);
560 struct mtk_eth *eth = mac->hw;
561 u32 idx = (vid & 0xf);
562
563 if (!((mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE]) &&
564 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
565 return 0;
566
567 clear_bit(idx, &eth->vlan_map);
568
569 return 0;
570}
571
572static inline u32 mtk_pdma_empty_txd(struct mtk_tx_ring *ring)
573{
574 barrier();
575 return (u32)(ring->tx_ring_size -
576 ((ring->tx_next_idx - ring->tx_free_idx) &
577 (ring->tx_ring_size - 1)));
578}
579
580static int mtk_skb_padto(struct sk_buff *skb, struct mtk_eth *eth)
581{
582 unsigned int len;
583 int ret;
584
585 if (unlikely(skb->len >= VLAN_ETH_ZLEN))
586 return 0;
587
588 if (eth->soc->padding_64b && !eth->soc->padding_bug)
589 return 0;
590
591 if (skb_vlan_tag_present(skb))
592 len = ETH_ZLEN;
593 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
594 len = VLAN_ETH_ZLEN;
595 else if (!eth->soc->padding_64b)
596 len = ETH_ZLEN;
597 else
598 return 0;
599
600 if (skb->len >= len)
601 return 0;
602
603 ret = skb_pad(skb, len - skb->len);
604 if (ret < 0)
605 return ret;
606 skb->len = len;
607 skb_set_tail_pointer(skb, len);
608
609 return ret;
610}
611
612static int mtk_pdma_tx_map(struct sk_buff *skb, struct net_device *dev,
613 int tx_num, struct mtk_tx_ring *ring, bool gso)
614{
615 struct mtk_mac *mac = netdev_priv(dev);
616 struct mtk_eth *eth = mac->hw;
617 struct skb_frag_struct *frag;
618 struct mtk_tx_dma txd, *ptxd;
619 struct mtk_tx_buf *tx_buf;
620 int i, j, k, frag_size, frag_map_size, offset;
621 dma_addr_t mapped_addr;
622 unsigned int nr_frags;
623 u32 def_txd4;
624
625 if (mtk_skb_padto(skb, eth)) {
626 netif_warn(eth, tx_err, dev, "tx padding failed!\n");
627 return -1;
628 }
629
630 tx_buf = &ring->tx_buf[ring->tx_next_idx];
631 memset(tx_buf, 0, sizeof(*tx_buf));
632 memset(&txd, 0, sizeof(txd));
633 nr_frags = skb_shinfo(skb)->nr_frags;
634
635 /* init tx descriptor */
636 def_txd4 = eth->soc->txd4;
637 txd.txd4 = def_txd4;
638
639 if (eth->soc->mac_count > 1)
640 txd.txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT;
641
642 if (gso)
643 txd.txd4 |= TX_DMA_TSO;
644
645 /* TX Checksum offload */
646 if (skb->ip_summed == CHECKSUM_PARTIAL)
647 txd.txd4 |= TX_DMA_CHKSUM;
648
649 /* VLAN header offload */
650 if (skb_vlan_tag_present(skb)) {
651 u16 tag = skb_vlan_tag_get(skb);
652
653 txd.txd4 |= TX_DMA_INS_VLAN |
654 ((tag >> VLAN_PRIO_SHIFT) << 4) |
655 (tag & 0xF);
656 }
657
658 mapped_addr = dma_map_single(&dev->dev, skb->data,
659 skb_headlen(skb), DMA_TO_DEVICE);
660 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
661 return -1;
662
663 txd.txd1 = mapped_addr;
664 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
665
666 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
667 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
668 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
669
670 /* TX SG offload */
671 j = ring->tx_next_idx;
672 k = 0;
673 for (i = 0; i < nr_frags; i++) {
674 offset = 0;
675 frag = &skb_shinfo(skb)->frags[i];
676 frag_size = skb_frag_size(frag);
677
678 while (frag_size > 0) {
679 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
680 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
681 frag_map_size,
682 DMA_TO_DEVICE);
683 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
684 goto err_dma;
685
686 if (k & 0x1) {
687 j = NEXT_TX_DESP_IDX(j);
688 txd.txd1 = mapped_addr;
689 txd.txd2 = TX_DMA_PLEN0(frag_map_size);
690 txd.txd4 = def_txd4;
691
692 tx_buf = &ring->tx_buf[j];
693 memset(tx_buf, 0, sizeof(*tx_buf));
694
695 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
696 dma_unmap_addr_set(tx_buf, dma_addr0,
697 mapped_addr);
698 dma_unmap_len_set(tx_buf, dma_len0,
699 frag_map_size);
700 } else {
701 txd.txd3 = mapped_addr;
702 txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
703
704 tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
705 tx_buf->flags |= MTK_TX_FLAGS_PAGE1;
706 dma_unmap_addr_set(tx_buf, dma_addr1,
707 mapped_addr);
708 dma_unmap_len_set(tx_buf, dma_len1,
709 frag_map_size);
710
711 if (!((i == (nr_frags - 1)) &&
712 (frag_map_size == frag_size))) {
713 mtk_set_txd_pdma(&txd,
714 &ring->tx_dma[j]);
715 memset(&txd, 0, sizeof(txd));
716 }
717 }
718 frag_size -= frag_map_size;
719 offset += frag_map_size;
720 k++;
721 }
722 }
723
724 /* set last segment */
725 if (k & 0x1)
726 txd.txd2 |= TX_DMA_LS1;
727 else
728 txd.txd2 |= TX_DMA_LS0;
729 mtk_set_txd_pdma(&txd, &ring->tx_dma[j]);
730
731 /* store skb to cleanup */
732 tx_buf->skb = skb;
733
734 netdev_sent_queue(dev, skb->len);
735 skb_tx_timestamp(skb);
736
737 ring->tx_next_idx = NEXT_TX_DESP_IDX(j);
738 /* make sure that all changes to the dma ring are flushed before we
739 * continue
740 */
741 wmb();
742 atomic_set(&ring->tx_free_count, mtk_pdma_empty_txd(ring));
743
744 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
745 mtk_reg_w32(eth, ring->tx_next_idx, MTK_REG_TX_CTX_IDX0);
746
747 return 0;
748
749err_dma:
750 j = ring->tx_next_idx;
751 for (i = 0; i < tx_num; i++) {
752 ptxd = &ring->tx_dma[j];
753 tx_buf = &ring->tx_buf[j];
754
755 /* unmap dma */
756 mtk_txd_unmap(&dev->dev, tx_buf);
757
758 ptxd->txd2 = TX_DMA_DESP2_DEF;
759 j = NEXT_TX_DESP_IDX(j);
760 }
761 /* make sure that all changes to the dma ring are flushed before we
762 * continue
763 */
764 wmb();
765 return -1;
766}
767
768/* the qdma core needs scratch memory to be setup */
769static int mtk_init_fq_dma(struct mtk_eth *eth)
770{
771 dma_addr_t dma_addr, phy_ring_head, phy_ring_tail;
772 int cnt = eth->soc->dma_ring_size;
773 int i;
774
775 eth->scratch_ring = dma_alloc_coherent(eth->dev,
776 cnt * sizeof(struct mtk_tx_dma),
777 &phy_ring_head,
778 GFP_ATOMIC | __GFP_ZERO);
779 if (unlikely(!eth->scratch_ring))
780 return -ENOMEM;
781
782 eth->scratch_head = kcalloc(cnt, QDMA_PAGE_SIZE,
783 GFP_KERNEL);
784 dma_addr = dma_map_single(eth->dev,
785 eth->scratch_head, cnt * QDMA_PAGE_SIZE,
786 DMA_FROM_DEVICE);
787 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
788 return -ENOMEM;
789
790 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
791 phy_ring_tail = phy_ring_head + (sizeof(struct mtk_tx_dma) * (cnt - 1));
792
793 for (i = 0; i < cnt; i++) {
794 eth->scratch_ring[i].txd1 = (dma_addr + (i * QDMA_PAGE_SIZE));
795 if (i < cnt - 1)
796 eth->scratch_ring[i].txd2 = (phy_ring_head +
797 ((i + 1) * sizeof(struct mtk_tx_dma)));
798 eth->scratch_ring[i].txd3 = TX_QDMA_SDL(QDMA_PAGE_SIZE);
799 }
800
801 mtk_w32(eth, phy_ring_head, MTK_QDMA_FQ_HEAD);
802 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
803 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
804 mtk_w32(eth, QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
805
806 return 0;
807}
808
809static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
810{
811 void *ret = ring->tx_dma;
812
813 return ret + (desc - ring->tx_phys);
814}
815
816static struct mtk_tx_dma *mtk_tx_next_qdma(struct mtk_tx_ring *ring,
817 struct mtk_tx_dma *txd)
818{
819 return mtk_qdma_phys_to_virt(ring, txd->txd2);
820}
821
822static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
823 struct mtk_tx_dma *txd)
824{
825 int idx = txd - ring->tx_dma;
826
827 return &ring->tx_buf[idx];
828}
829
830static int mtk_qdma_tx_map(struct sk_buff *skb, struct net_device *dev,
831 int tx_num, struct mtk_tx_ring *ring, bool gso)
832{
833 struct mtk_mac *mac = netdev_priv(dev);
834 struct mtk_eth *eth = mac->hw;
835 struct mtk_tx_dma *itxd, *txd;
836 struct mtk_tx_buf *tx_buf;
837 dma_addr_t mapped_addr;
838 unsigned int nr_frags;
839 int i, n_desc = 1;
840 u32 txd4 = eth->soc->txd4;
841
842 itxd = ring->tx_next_free;
843 if (itxd == ring->tx_last_free)
844 return -ENOMEM;
845
846 if (eth->soc->mac_count > 1)
847 txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT;
848
849 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
850 memset(tx_buf, 0, sizeof(*tx_buf));
851
852 if (gso)
853 txd4 |= TX_DMA_TSO;
854
855 /* TX Checksum offload */
856 if (skb->ip_summed == CHECKSUM_PARTIAL)
857 txd4 |= TX_DMA_CHKSUM;
858
859 /* VLAN header offload */
860 if (skb_vlan_tag_present(skb))
861 txd4 |= TX_DMA_INS_VLAN_MT7621 | skb_vlan_tag_get(skb);
862
863 mapped_addr = dma_map_single(&dev->dev, skb->data,
864 skb_headlen(skb), DMA_TO_DEVICE);
865 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
866 return -ENOMEM;
867
868 WRITE_ONCE(itxd->txd1, mapped_addr);
869 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
870 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
871 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
872
873 /* TX SG offload */
874 txd = itxd;
875 nr_frags = skb_shinfo(skb)->nr_frags;
876 for (i = 0; i < nr_frags; i++) {
877 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
878 unsigned int offset = 0;
879 int frag_size = skb_frag_size(frag);
880
881 while (frag_size) {
882 bool last_frag = false;
883 unsigned int frag_map_size;
884
885 txd = mtk_tx_next_qdma(ring, txd);
886 if (txd == ring->tx_last_free)
887 goto err_dma;
888
889 n_desc++;
890 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
891 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
892 frag_map_size,
893 DMA_TO_DEVICE);
894 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
895 goto err_dma;
896
897 if (i == nr_frags - 1 &&
898 (frag_size - frag_map_size) == 0)
899 last_frag = true;
900
901 WRITE_ONCE(txd->txd1, mapped_addr);
902 WRITE_ONCE(txd->txd3, (QDMA_TX_SWC |
903 TX_DMA_PLEN0(frag_map_size) |
904 last_frag * TX_DMA_LS0) |
905 mac->id);
906 WRITE_ONCE(txd->txd4, 0);
907
908 tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
909 tx_buf = mtk_desc_to_tx_buf(ring, txd);
910 memset(tx_buf, 0, sizeof(*tx_buf));
911
912 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
913 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
914 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
915 frag_size -= frag_map_size;
916 offset += frag_map_size;
917 }
918 }
919
920 /* store skb to cleanup */
921 tx_buf->skb = skb;
922
923 WRITE_ONCE(itxd->txd4, txd4);
924 WRITE_ONCE(itxd->txd3, (QDMA_TX_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
925 (!nr_frags * TX_DMA_LS0)));
926
927 netdev_sent_queue(dev, skb->len);
928 skb_tx_timestamp(skb);
929
930 ring->tx_next_free = mtk_tx_next_qdma(ring, txd);
931 atomic_sub(n_desc, &ring->tx_free_count);
932
933 /* make sure that all changes to the dma ring are flushed before we
934 * continue
935 */
936 wmb();
937
938 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
939 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
940
941 return 0;
942
943err_dma:
944 do {
945 tx_buf = mtk_desc_to_tx_buf(ring, txd);
946
947 /* unmap dma */
948 mtk_txd_unmap(&dev->dev, tx_buf);
949
950 itxd->txd3 = TX_DMA_DESP2_DEF;
951 itxd = mtk_tx_next_qdma(ring, itxd);
952 } while (itxd != txd);
953
954 return -ENOMEM;
955}
956
957static inline int mtk_cal_txd_req(struct sk_buff *skb)
958{
959 int i, nfrags;
960 struct skb_frag_struct *frag;
961
962 nfrags = 1;
963 if (skb_is_gso(skb)) {
964 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
965 frag = &skb_shinfo(skb)->frags[i];
966 nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
967 }
968 } else {
969 nfrags += skb_shinfo(skb)->nr_frags;
970 }
971
972 return DIV_ROUND_UP(nfrags, 2);
973}
974
975static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
976{
977 struct mtk_mac *mac = netdev_priv(dev);
978 struct mtk_eth *eth = mac->hw;
979 struct mtk_tx_ring *ring = &eth->tx_ring;
980 struct net_device_stats *stats = &dev->stats;
981 int tx_num;
982 int len = skb->len;
983 bool gso = false;
984
985 tx_num = mtk_cal_txd_req(skb);
986 if (unlikely(atomic_read(&ring->tx_free_count) <= tx_num)) {
987 netif_stop_queue(dev);
988 netif_err(eth, tx_queued, dev,
989 "Tx Ring full when queue awake!\n");
990 return NETDEV_TX_BUSY;
991 }
992
993 /* TSO: fill MSS info in tcp checksum field */
994 if (skb_is_gso(skb)) {
995 if (skb_cow_head(skb, 0)) {
996 netif_warn(eth, tx_err, dev,
997 "GSO expand head fail.\n");
998 goto drop;
999 }
1000
1001 if (skb_shinfo(skb)->gso_type &
1002 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1003 gso = true;
1004 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
1005 }
1006 }
1007
1008 if (ring->tx_map(skb, dev, tx_num, ring, gso) < 0)
1009 goto drop;
1010
1011 stats->tx_packets++;
1012 stats->tx_bytes += len;
1013
1014 if (unlikely(atomic_read(&ring->tx_free_count) <= ring->tx_thresh)) {
1015 netif_stop_queue(dev);
1016 smp_mb();
1017 if (unlikely(atomic_read(&ring->tx_free_count) >
1018 ring->tx_thresh))
1019 netif_wake_queue(dev);
1020 }
1021
1022 return NETDEV_TX_OK;
1023
1024drop:
1025 stats->tx_dropped++;
1026 dev_kfree_skb(skb);
1027 return NETDEV_TX_OK;
1028}
1029
1030static int mtk_poll_rx(struct napi_struct *napi, int budget,
1031 struct mtk_eth *eth, u32 rx_intr)
1032{
1033 struct mtk_soc_data *soc = eth->soc;
1034 struct mtk_rx_ring *ring = &eth->rx_ring[0];
1035 int idx = ring->rx_calc_idx;
1036 u32 checksum_bit;
1037 struct sk_buff *skb;
1038 u8 *data, *new_data;
1039 struct mtk_rx_dma *rxd, trxd;
1040 int done = 0, pad;
1041
1042 if (eth->soc->hw_features & NETIF_F_RXCSUM)
1043 checksum_bit = soc->checksum_bit;
1044 else
1045 checksum_bit = 0;
1046
1047 if (eth->soc->rx_2b_offset)
1048 pad = 0;
1049 else
1050 pad = NET_IP_ALIGN;
1051
1052 while (done < budget) {
1053 struct net_device *netdev;
1054 unsigned int pktlen;
1055 dma_addr_t dma_addr;
1056 int mac = 0;
1057
1058 idx = NEXT_RX_DESP_IDX(idx);
1059 rxd = &ring->rx_dma[idx];
1060 data = ring->rx_data[idx];
1061
1062 mtk_get_rxd(&trxd, rxd);
1063 if (!(trxd.rxd2 & RX_DMA_DONE))
1064 break;
1065
1066 /* find out which mac the packet come from. values start at 1 */
1067 if (eth->soc->mac_count > 1) {
1068 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
1069 RX_DMA_FPORT_MASK;
1070 mac--;
1071 if (mac < 0 || mac >= eth->soc->mac_count)
1072 goto release_desc;
1073 }
1074
1075 netdev = eth->netdev[mac];
1076
1077 /* alloc new buffer */
1078 new_data = napi_alloc_frag(ring->frag_size);
1079 if (unlikely(!new_data || !netdev)) {
1080 netdev->stats.rx_dropped++;
1081 goto release_desc;
1082 }
1083 dma_addr = dma_map_single(&netdev->dev,
1084 new_data + NET_SKB_PAD + pad,
1085 ring->rx_buf_size,
1086 DMA_FROM_DEVICE);
1087 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
1088 skb_free_frag(new_data);
1089 goto release_desc;
1090 }
1091
1092 /* receive data */
1093 skb = build_skb(data, ring->frag_size);
1094 if (unlikely(!skb)) {
1095 put_page(virt_to_head_page(new_data));
1096 goto release_desc;
1097 }
1098 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
1099
1100 dma_unmap_single(&netdev->dev, trxd.rxd1,
1101 ring->rx_buf_size, DMA_FROM_DEVICE);
1102 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1103 skb->dev = netdev;
1104 skb_put(skb, pktlen);
1105 if (trxd.rxd4 & checksum_bit)
1106 skb->ip_summed = CHECKSUM_UNNECESSARY;
1107 else
1108 skb_checksum_none_assert(skb);
1109 skb->protocol = eth_type_trans(skb, netdev);
1110
1111 netdev->stats.rx_packets++;
1112 netdev->stats.rx_bytes += pktlen;
1113
1114 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
1115 RX_DMA_VID(trxd.rxd3))
1116 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1117 RX_DMA_VID(trxd.rxd3));
1118 napi_gro_receive(napi, skb);
1119
1120 ring->rx_data[idx] = new_data;
1121 rxd->rxd1 = (unsigned int)dma_addr;
1122
1123release_desc:
1124 if (eth->soc->rx_sg_dma)
1125 rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
1126 else
1127 rxd->rxd2 = RX_DMA_LSO;
1128
1129 ring->rx_calc_idx = idx;
1130 /* make sure that all changes to the dma ring are flushed before
1131 * we continue
1132 */
1133 wmb();
1134 if (eth->soc->dma_type == MTK_QDMA)
1135 mtk_w32(eth, ring->rx_calc_idx, MTK_QRX_CRX_IDX0);
1136 else
1137 mtk_reg_w32(eth, ring->rx_calc_idx,
1138 MTK_REG_RX_CALC_IDX0);
1139 done++;
1140 }
1141
1142 if (done < budget)
1143 mtk_irq_ack(eth, rx_intr);
1144
1145 return done;
1146}
1147
1148static int mtk_pdma_tx_poll(struct mtk_eth *eth, int budget, bool *tx_again)
1149{
1150 struct sk_buff *skb;
1151 struct mtk_tx_buf *tx_buf;
1152 int done = 0;
1153 u32 idx, hwidx;
1154 struct mtk_tx_ring *ring = &eth->tx_ring;
1155 unsigned int bytes = 0;
1156
1157 idx = ring->tx_free_idx;
1158 hwidx = mtk_reg_r32(eth, MTK_REG_TX_DTX_IDX0);
1159
1160 while ((idx != hwidx) && budget) {
1161 tx_buf = &ring->tx_buf[idx];
1162 skb = tx_buf->skb;
1163
1164 if (!skb)
1165 break;
1166
1167 if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
1168 bytes += skb->len;
1169 done++;
1170 budget--;
1171 }
1172 mtk_txd_unmap(eth->dev, tx_buf);
1173 idx = NEXT_TX_DESP_IDX(idx);
1174 }
1175 ring->tx_free_idx = idx;
1176 atomic_set(&ring->tx_free_count, mtk_pdma_empty_txd(ring));
1177
1178 /* read hw index again make sure no new tx packet */
1179 if (idx != hwidx || idx != mtk_reg_r32(eth, MTK_REG_TX_DTX_IDX0))
1180 *tx_again = 1;
1181
1182 if (done)
1183 netdev_completed_queue(*eth->netdev, done, bytes);
1184
1185 return done;
1186}
1187
1188static int mtk_qdma_tx_poll(struct mtk_eth *eth, int budget, bool *tx_again)
1189{
1190 struct mtk_tx_ring *ring = &eth->tx_ring;
1191 struct mtk_tx_dma *desc;
1192 struct sk_buff *skb;
1193 struct mtk_tx_buf *tx_buf;
1194 int total = 0, done[MTK_MAX_DEVS];
1195 unsigned int bytes[MTK_MAX_DEVS];
1196 u32 cpu, dma;
1197 int i;
1198
1199 memset(done, 0, sizeof(done));
1200 memset(bytes, 0, sizeof(bytes));
1201
1202 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
1203 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
1204
1205 desc = mtk_qdma_phys_to_virt(ring, cpu);
1206
1207 while ((cpu != dma) && budget) {
1208 u32 next_cpu = desc->txd2;
1209 int mac;
1210
1211 desc = mtk_tx_next_qdma(ring, desc);
1212 if ((desc->txd3 & QDMA_TX_OWNER_CPU) == 0)
1213 break;
1214
1215 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
1216 TX_DMA_FPORT_MASK;
1217 mac--;
1218
1219 tx_buf = mtk_desc_to_tx_buf(ring, desc);
1220 skb = tx_buf->skb;
1221 if (!skb)
1222 break;
1223
1224 if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
1225 bytes[mac] += skb->len;
1226 done[mac]++;
1227 budget--;
1228 }
1229 mtk_txd_unmap(eth->dev, tx_buf);
1230
1231 ring->tx_last_free->txd2 = next_cpu;
1232 ring->tx_last_free = desc;
1233 atomic_inc(&ring->tx_free_count);
1234
1235 cpu = next_cpu;
1236 }
1237
1238 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1239
1240 /* read hw index again make sure no new tx packet */
1241 if (cpu != dma || cpu != mtk_r32(eth, MTK_QTX_DRX_PTR))
1242 *tx_again = true;
1243
1244 for (i = 0; i < eth->soc->mac_count; i++) {
1245 if (!done[i])
1246 continue;
1247 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1248 total += done[i];
1249 }
1250
1251 return total;
1252}
1253
1254static int mtk_poll_tx(struct mtk_eth *eth, int budget, u32 tx_intr,
1255 bool *tx_again)
1256{
1257 struct mtk_tx_ring *ring = &eth->tx_ring;
1258 struct net_device *netdev = eth->netdev[0];
1259 int done;
1260
1261 done = eth->tx_ring.tx_poll(eth, budget, tx_again);
1262 if (!*tx_again)
1263 mtk_irq_ack(eth, tx_intr);
1264
1265 if (!done)
1266 return 0;
1267
1268 smp_mb();
1269 if (unlikely(!netif_queue_stopped(netdev)))
1270 return done;
1271
1272 if (atomic_read(&ring->tx_free_count) > ring->tx_thresh)
1273 netif_wake_queue(netdev);
1274
1275 return done;
1276}
1277
1278static void mtk_stats_update(struct mtk_eth *eth)
1279{
1280 int i;
1281
1282 for (i = 0; i < eth->soc->mac_count; i++) {
1283 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
1284 continue;
1285 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
1286 mtk_stats_update_mac(eth->mac[i]);
1287 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
1288 }
1289 }
1290}
1291
1292static int mtk_poll(struct napi_struct *napi, int budget)
1293{
1294 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1295 u32 status, mtk_status, mask, tx_intr, rx_intr, status_intr;
1296 int tx_done, rx_done;
1297 bool tx_again = false;
1298
1299 status = mtk_irq_pending(eth);
1300 mtk_status = mtk_irq_pending_status(eth);
1301 tx_intr = eth->soc->tx_int;
1302 rx_intr = eth->soc->rx_int;
1303 status_intr = eth->soc->status_int;
1304 tx_done = 0;
1305 rx_done = 0;
1306 tx_again = 0;
1307
1308 if (status & tx_intr)
1309 tx_done = mtk_poll_tx(eth, budget, tx_intr, &tx_again);
1310
1311 if (status & rx_intr)
1312 rx_done = mtk_poll_rx(napi, budget, eth, rx_intr);
1313
1314 if (unlikely(mtk_status & status_intr)) {
1315 mtk_stats_update(eth);
1316 mtk_irq_ack_status(eth, status_intr);
1317 }
1318
1319 if (unlikely(netif_msg_intr(eth))) {
1320 mask = mtk_irq_enabled(eth);
1321 netdev_info(eth->netdev[0],
1322 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1323 tx_done, rx_done, status, mask);
1324 }
1325
1326 if (tx_again || rx_done == budget)
1327 return budget;
1328
1329 status = mtk_irq_pending(eth);
1330 if (status & (tx_intr | rx_intr))
1331 return budget;
1332
1333 napi_complete(napi);
1334 mtk_irq_enable(eth, tx_intr | rx_intr);
1335
1336 return rx_done;
1337}
1338
1339static int mtk_pdma_tx_alloc(struct mtk_eth *eth)
1340{
1341 int i;
1342 struct mtk_tx_ring *ring = &eth->tx_ring;
1343
1344 ring->tx_ring_size = eth->soc->dma_ring_size;
1345 ring->tx_free_idx = 0;
1346 ring->tx_next_idx = 0;
1347 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
1348 MAX_SKB_FRAGS);
1349
1350 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
1351 GFP_KERNEL);
1352 if (!ring->tx_buf)
1353 goto no_tx_mem;
1354
1355 ring->tx_dma =
1356 dma_alloc_coherent(eth->dev,
1357 ring->tx_ring_size * sizeof(*ring->tx_dma),
1358 &ring->tx_phys, GFP_ATOMIC | __GFP_ZERO);
1359 if (!ring->tx_dma)
1360 goto no_tx_mem;
1361
1362 for (i = 0; i < ring->tx_ring_size; i++) {
1363 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
1364 ring->tx_dma[i].txd4 = eth->soc->txd4;
1365 }
1366
1367 atomic_set(&ring->tx_free_count, mtk_pdma_empty_txd(ring));
1368 ring->tx_map = mtk_pdma_tx_map;
1369 ring->tx_poll = mtk_pdma_tx_poll;
1370 ring->tx_clean = mtk_pdma_tx_clean;
1371
1372 /* make sure that all changes to the dma ring are flushed before we
1373 * continue
1374 */
1375 wmb();
1376
1377 mtk_reg_w32(eth, ring->tx_phys, MTK_REG_TX_BASE_PTR0);
1378 mtk_reg_w32(eth, ring->tx_ring_size, MTK_REG_TX_MAX_CNT0);
1379 mtk_reg_w32(eth, 0, MTK_REG_TX_CTX_IDX0);
1380 mtk_reg_w32(eth, MTK_PST_DTX_IDX0, MTK_REG_PDMA_RST_CFG);
1381
1382 return 0;
1383
1384no_tx_mem:
1385 return -ENOMEM;
1386}
1387
1388static int mtk_qdma_tx_alloc_tx(struct mtk_eth *eth)
1389{
1390 struct mtk_tx_ring *ring = &eth->tx_ring;
1391 int i, sz = sizeof(*ring->tx_dma);
1392
1393 ring->tx_ring_size = eth->soc->dma_ring_size;
1394 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
1395 GFP_KERNEL);
1396 if (!ring->tx_buf)
1397 goto no_tx_mem;
1398
1399 ring->tx_dma = dma_alloc_coherent(eth->dev, ring->tx_ring_size * sz,
1400 &ring->tx_phys,
1401 GFP_ATOMIC | __GFP_ZERO);
1402 if (!ring->tx_dma)
1403 goto no_tx_mem;
1404
1405 for (i = 0; i < ring->tx_ring_size; i++) {
1406 int next = (i + 1) % ring->tx_ring_size;
1407 u32 next_ptr = ring->tx_phys + next * sz;
1408
1409 ring->tx_dma[i].txd2 = next_ptr;
1410 ring->tx_dma[i].txd3 = TX_DMA_DESP2_DEF;
1411 }
1412
1413 atomic_set(&ring->tx_free_count, ring->tx_ring_size - 2);
1414 ring->tx_next_free = &ring->tx_dma[0];
1415 ring->tx_last_free = &ring->tx_dma[ring->tx_ring_size - 2];
1416 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
1417 MAX_SKB_FRAGS);
1418
1419 ring->tx_map = mtk_qdma_tx_map;
1420 ring->tx_poll = mtk_qdma_tx_poll;
1421 ring->tx_clean = mtk_qdma_tx_clean;
1422
1423 /* make sure that all changes to the dma ring are flushed before we
1424 * continue
1425 */
1426 wmb();
1427
1428 mtk_w32(eth, ring->tx_phys, MTK_QTX_CTX_PTR);
1429 mtk_w32(eth, ring->tx_phys, MTK_QTX_DTX_PTR);
1430 mtk_w32(eth,
1431 ring->tx_phys + ((ring->tx_ring_size - 1) * sz),
1432 MTK_QTX_CRX_PTR);
1433 mtk_w32(eth,
1434 ring->tx_phys + ((ring->tx_ring_size - 1) * sz),
1435 MTK_QTX_DRX_PTR);
1436
1437 return 0;
1438
1439no_tx_mem:
1440 return -ENOMEM;
1441}
1442
1443static int mtk_qdma_init(struct mtk_eth *eth, int ring)
1444{
1445 int err;
1446
1447 err = mtk_init_fq_dma(eth);
1448 if (err)
1449 return err;
1450
1451 err = mtk_qdma_tx_alloc_tx(eth);
1452 if (err)
1453 return err;
1454
1455 err = mtk_dma_rx_alloc(eth, &eth->rx_ring[ring]);
1456 if (err)
1457 return err;
1458
1459 mtk_w32(eth, eth->rx_ring[ring].rx_phys, MTK_QRX_BASE_PTR0);
1460 mtk_w32(eth, eth->rx_ring[ring].rx_ring_size, MTK_QRX_MAX_CNT0);
1461 mtk_w32(eth, eth->rx_ring[ring].rx_calc_idx, MTK_QRX_CRX_IDX0);
1462 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX);
1463 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1464
1465 /* Enable random early drop and set drop threshold automatically */
1466 mtk_w32(eth, 0x174444, MTK_QDMA_FC_THRES);
1467 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1468
1469 return 0;
1470}
1471
1472static int mtk_pdma_qdma_init(struct mtk_eth *eth)
1473{
1474 int err = mtk_qdma_init(eth, 1);
1475
1476 if (err)
1477 return err;
1478
1479 err = mtk_dma_rx_alloc(eth, &eth->rx_ring[0]);
1480 if (err)
1481 return err;
1482
1483 mtk_reg_w32(eth, eth->rx_ring[0].rx_phys, MTK_REG_RX_BASE_PTR0);
1484 mtk_reg_w32(eth, eth->rx_ring[0].rx_ring_size, MTK_REG_RX_MAX_CNT0);
1485 mtk_reg_w32(eth, eth->rx_ring[0].rx_calc_idx, MTK_REG_RX_CALC_IDX0);
1486 mtk_reg_w32(eth, MTK_PST_DRX_IDX0, MTK_REG_PDMA_RST_CFG);
1487
1488 return 0;
1489}
1490
1491static int mtk_pdma_init(struct mtk_eth *eth)
1492{
1493 struct mtk_rx_ring *ring = &eth->rx_ring[0];
1494 int err;
1495
1496 err = mtk_pdma_tx_alloc(eth);
1497 if (err)
1498 return err;
1499
1500 err = mtk_dma_rx_alloc(eth, ring);
1501 if (err)
1502 return err;
1503
1504 mtk_reg_w32(eth, ring->rx_phys, MTK_REG_RX_BASE_PTR0);
1505 mtk_reg_w32(eth, ring->rx_ring_size, MTK_REG_RX_MAX_CNT0);
1506 mtk_reg_w32(eth, ring->rx_calc_idx, MTK_REG_RX_CALC_IDX0);
1507 mtk_reg_w32(eth, MTK_PST_DRX_IDX0, MTK_REG_PDMA_RST_CFG);
1508
1509 return 0;
1510}
1511
1512static void mtk_dma_free(struct mtk_eth *eth)
1513{
1514 int i;
1515
1516 for (i = 0; i < eth->soc->mac_count; i++)
1517 if (eth->netdev[i])
1518 netdev_reset_queue(eth->netdev[i]);
1519 eth->tx_ring.tx_clean(eth);
1520 mtk_clean_rx(eth, &eth->rx_ring[0]);
1521 mtk_clean_rx(eth, &eth->rx_ring[1]);
1522 kfree(eth->scratch_head);
1523}
1524
1525static void mtk_tx_timeout(struct net_device *dev)
1526{
1527 struct mtk_mac *mac = netdev_priv(dev);
1528 struct mtk_eth *eth = mac->hw;
1529 struct mtk_tx_ring *ring = &eth->tx_ring;
1530
1531 eth->netdev[mac->id]->stats.tx_errors++;
1532 netif_err(eth, tx_err, dev,
1533 "transmit timed out\n");
1534 if (eth->soc->dma_type & MTK_PDMA) {
1535 netif_info(eth, drv, dev, "pdma_cfg:%08x\n",
1536 mtk_reg_r32(eth, MTK_REG_PDMA_GLO_CFG));
1537 netif_info(eth, drv, dev,
1538 "tx_ring=%d, base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1539 0, mtk_reg_r32(eth, MTK_REG_TX_BASE_PTR0),
1540 mtk_reg_r32(eth, MTK_REG_TX_MAX_CNT0),
1541 mtk_reg_r32(eth, MTK_REG_TX_CTX_IDX0),
1542 mtk_reg_r32(eth, MTK_REG_TX_DTX_IDX0),
1543 ring->tx_free_idx,
1544 ring->tx_next_idx);
1545 }
1546 if (eth->soc->dma_type & MTK_QDMA) {
1547 netif_info(eth, drv, dev, "qdma_cfg:%08x\n",
1548 mtk_r32(eth, MTK_QDMA_GLO_CFG));
1549 netif_info(eth, drv, dev,
1550 "tx_ring=%d, ctx=%08x, dtx=%08x, crx=%08x, drx=%08x, free=%hu\n",
1551 0, mtk_r32(eth, MTK_QTX_CTX_PTR),
1552 mtk_r32(eth, MTK_QTX_DTX_PTR),
1553 mtk_r32(eth, MTK_QTX_CRX_PTR),
1554 mtk_r32(eth, MTK_QTX_DRX_PTR),
1555 atomic_read(&ring->tx_free_count));
1556 }
1557 netif_info(eth, drv, dev,
1558 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1559 0, mtk_reg_r32(eth, MTK_REG_RX_BASE_PTR0),
1560 mtk_reg_r32(eth, MTK_REG_RX_MAX_CNT0),
1561 mtk_reg_r32(eth, MTK_REG_RX_CALC_IDX0),
1562 mtk_reg_r32(eth, MTK_REG_RX_DRX_IDX0));
1563
1564 schedule_work(&mac->pending_work);
1565}
1566
1567static irqreturn_t mtk_handle_irq(int irq, void *_eth)
1568{
1569 struct mtk_eth *eth = _eth;
1570 u32 status, int_mask;
1571
1572 status = mtk_irq_pending(eth);
1573 if (unlikely(!status))
1574 return IRQ_NONE;
1575
1576 int_mask = (eth->soc->rx_int | eth->soc->tx_int);
1577 if (likely(status & int_mask)) {
1578 if (likely(napi_schedule_prep(&eth->rx_napi)))
1579 __napi_schedule(&eth->rx_napi);
1580 } else {
1581 mtk_irq_ack(eth, status);
1582 }
1583 mtk_irq_disable(eth, int_mask);
1584
1585 return IRQ_HANDLED;
1586}
1587
1588#ifdef CONFIG_NET_POLL_CONTROLLER
1589static void mtk_poll_controller(struct net_device *dev)
1590{
1591 struct mtk_mac *mac = netdev_priv(dev);
1592 struct mtk_eth *eth = mac->hw;
1593 u32 int_mask = eth->soc->tx_int | eth->soc->rx_int;
1594
1595 mtk_irq_disable(eth, int_mask);
1596 mtk_handle_irq(dev->irq, dev);
1597 mtk_irq_enable(eth, int_mask);
1598}
1599#endif
1600
1601int mtk_set_clock_cycle(struct mtk_eth *eth)
1602{
1603 unsigned long sysclk = eth->sysclk;
1604
1605 sysclk /= MTK_US_CYC_CNT_DIVISOR;
1606 sysclk <<= MTK_US_CYC_CNT_SHIFT;
1607
1608 mtk_w32(eth, (mtk_r32(eth, MTK_GLO_CFG) &
1609 ~(MTK_US_CYC_CNT_MASK << MTK_US_CYC_CNT_SHIFT)) |
1610 sysclk,
1611 MTK_GLO_CFG);
1612 return 0;
1613}
1614
1615void mtk_fwd_config(struct mtk_eth *eth)
1616{
1617 u32 fwd_cfg;
1618
1619 fwd_cfg = mtk_r32(eth, MTK_GDMA1_FWD_CFG);
1620
1621 /* disable jumbo frame */
1622 if (eth->soc->jumbo_frame)
1623 fwd_cfg &= ~MTK_GDM1_JMB_EN;
1624
1625 /* set unicast/multicast/broadcast frame to cpu */
1626 fwd_cfg &= ~0xffff;
1627
1628 mtk_w32(eth, fwd_cfg, MTK_GDMA1_FWD_CFG);
1629}
1630
1631void mtk_csum_config(struct mtk_eth *eth)
1632{
1633 if (eth->soc->hw_features & NETIF_F_RXCSUM)
1634 mtk_w32(eth, mtk_r32(eth, MTK_GDMA1_FWD_CFG) |
1635 (MTK_GDM1_ICS_EN | MTK_GDM1_TCS_EN | MTK_GDM1_UCS_EN),
1636 MTK_GDMA1_FWD_CFG);
1637 else
1638 mtk_w32(eth, mtk_r32(eth, MTK_GDMA1_FWD_CFG) &
1639 ~(MTK_GDM1_ICS_EN | MTK_GDM1_TCS_EN | MTK_GDM1_UCS_EN),
1640 MTK_GDMA1_FWD_CFG);
1641 if (eth->soc->hw_features & NETIF_F_IP_CSUM)
1642 mtk_w32(eth, mtk_r32(eth, MTK_CDMA_CSG_CFG) |
1643 (MTK_ICS_GEN_EN | MTK_TCS_GEN_EN | MTK_UCS_GEN_EN),
1644 MTK_CDMA_CSG_CFG);
1645 else
1646 mtk_w32(eth, mtk_r32(eth, MTK_CDMA_CSG_CFG) &
1647 ~(MTK_ICS_GEN_EN | MTK_TCS_GEN_EN | MTK_UCS_GEN_EN),
1648 MTK_CDMA_CSG_CFG);
1649}
1650
1651static int mtk_start_dma(struct mtk_eth *eth)
1652{
1653 unsigned long flags;
1654 u32 val;
1655 int err;
1656
1657 if (eth->soc->dma_type == MTK_PDMA)
1658 err = mtk_pdma_init(eth);
1659 else if (eth->soc->dma_type == MTK_QDMA)
1660 err = mtk_qdma_init(eth, 0);
1661 else
1662 err = mtk_pdma_qdma_init(eth);
1663 if (err) {
1664 mtk_dma_free(eth);
1665 return err;
1666 }
1667
1668 spin_lock_irqsave(&eth->page_lock, flags);
1669
1670 val = MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN;
1671 if (eth->soc->rx_2b_offset)
1672 val |= MTK_RX_2B_OFFSET;
1673 val |= eth->soc->pdma_glo_cfg;
1674
1675 if (eth->soc->dma_type & MTK_PDMA)
1676 mtk_reg_w32(eth, val, MTK_REG_PDMA_GLO_CFG);
1677
1678 if (eth->soc->dma_type & MTK_QDMA)
1679 mtk_w32(eth, val, MTK_QDMA_GLO_CFG);
1680
1681 spin_unlock_irqrestore(&eth->page_lock, flags);
1682
1683 return 0;
1684}
1685
1686static int mtk_open(struct net_device *dev)
1687{
1688 struct mtk_mac *mac = netdev_priv(dev);
1689 struct mtk_eth *eth = mac->hw;
1690
1691 dma_coerce_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
1692
1693 if (!atomic_read(&eth->dma_refcnt)) {
1694 int err = mtk_start_dma(eth);
1695
1696 if (err)
1697 return err;
1698
1699 napi_enable(&eth->rx_napi);
1700 mtk_irq_enable(eth, eth->soc->tx_int | eth->soc->rx_int);
1701 }
1702 atomic_inc(&eth->dma_refcnt);
1703
1704 if (eth->phy)
1705 eth->phy->start(mac);
1706
1707 if (eth->soc->has_carrier && eth->soc->has_carrier(eth))
1708 netif_carrier_on(dev);
1709
1710 netif_start_queue(dev);
1711 eth->soc->fwd_config(eth);
1712
1713 return 0;
1714}
1715
1716static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1717{
1718 unsigned long flags;
1719 u32 val;
1720 int i;
1721
1722 /* stop the dma enfine */
1723 spin_lock_irqsave(&eth->page_lock, flags);
1724 val = mtk_r32(eth, glo_cfg);
1725 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1726 glo_cfg);
1727 spin_unlock_irqrestore(&eth->page_lock, flags);
1728
1729 /* wait for dma stop */
1730 for (i = 0; i < 10; i++) {
1731 val = mtk_r32(eth, glo_cfg);
1732 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1733 msleep(20);
1734 continue;
1735 }
1736 break;
1737 }
1738}
1739
1740static int mtk_stop(struct net_device *dev)
1741{
1742 struct mtk_mac *mac = netdev_priv(dev);
1743 struct mtk_eth *eth = mac->hw;
1744
1745 netif_tx_disable(dev);
1746 if (eth->phy)
1747 eth->phy->stop(mac);
1748
1749 if (!atomic_dec_and_test(&eth->dma_refcnt))
1750 return 0;
1751
1752 mtk_irq_disable(eth, eth->soc->tx_int | eth->soc->rx_int);
1753 napi_disable(&eth->rx_napi);
1754
1755 if (eth->soc->dma_type & MTK_PDMA)
1756 mtk_stop_dma(eth, mtk_reg_table[MTK_REG_PDMA_GLO_CFG]);
1757
1758 if (eth->soc->dma_type & MTK_QDMA)
1759 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1760
1761 mtk_dma_free(eth);
1762
1763 return 0;
1764}
1765
1766static int __init mtk_init_hw(struct mtk_eth *eth)
1767{
1768 int i, err;
1769
1770 eth->soc->reset_fe(eth);
1771
1772 if (eth->soc->switch_init)
1773 if (eth->soc->switch_init(eth)) {
1774 dev_err(eth->dev, "failed to initialize switch core\n");
1775 return -ENODEV;
1776 }
1777
1778 err = devm_request_irq(eth->dev, eth->irq, mtk_handle_irq, 0,
1779 dev_name(eth->dev), eth);
1780 if (err)
1781 return err;
1782
1783 err = mtk_mdio_init(eth);
1784 if (err)
1785 return err;
1786
1787 /* disable delay and normal interrupt */
1788 mtk_reg_w32(eth, 0, MTK_REG_DLY_INT_CFG);
1789 if (eth->soc->dma_type & MTK_QDMA)
1790 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1791 mtk_irq_disable(eth, eth->soc->tx_int | eth->soc->rx_int);
1792
1793 /* frame engine will push VLAN tag regarding to VIDX field in Tx desc */
1794 if (mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE])
1795 for (i = 0; i < 16; i += 2)
1796 mtk_w32(eth, ((i + 1) << 16) + i,
1797 mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE] +
1798 (i * 2));
1799
1800 if (eth->soc->fwd_config(eth))
1801 dev_err(eth->dev, "unable to get clock\n");
1802
1803 if (mtk_reg_table[MTK_REG_MTK_RST_GL]) {
1804 mtk_reg_w32(eth, 1, MTK_REG_MTK_RST_GL);
1805 mtk_reg_w32(eth, 0, MTK_REG_MTK_RST_GL);
1806 }
1807
1808 return 0;
1809}
1810
1811static int __init mtk_init(struct net_device *dev)
1812{
1813 struct mtk_mac *mac = netdev_priv(dev);
1814 struct mtk_eth *eth = mac->hw;
1815 struct device_node *port;
1816 const char *mac_addr;
1817 int err;
1818
1819 mac_addr = of_get_mac_address(mac->of_node);
1820 if (mac_addr)
1821 ether_addr_copy(dev->dev_addr, mac_addr);
1822
1823 /* If the mac address is invalid, use random mac address */
1824 if (!is_valid_ether_addr(dev->dev_addr)) {
1825 eth_hw_addr_random(dev);
1826 dev_err(eth->dev, "generated random MAC address %pM\n",
1827 dev->dev_addr);
1828 }
1829 mac->hw->soc->set_mac(mac, dev->dev_addr);
1830
1831 if (eth->soc->port_init)
1832 for_each_child_of_node(mac->of_node, port)
1833 if (of_device_is_compatible(port,
1834 "mediatek,eth-port") &&
1835 of_device_is_available(port))
1836 eth->soc->port_init(eth, mac, port);
1837
1838 if (eth->phy) {
1839 err = eth->phy->connect(mac);
1840 if (err)
1841 return err;
1842 }
1843
1844 return 0;
1845}
1846
1847static void mtk_uninit(struct net_device *dev)
1848{
1849 struct mtk_mac *mac = netdev_priv(dev);
1850 struct mtk_eth *eth = mac->hw;
1851
1852 if (eth->phy)
1853 eth->phy->disconnect(mac);
1854 mtk_mdio_cleanup(eth);
1855
1856 mtk_irq_disable(eth, ~0);
1857 free_irq(dev->irq, dev);
1858}
1859
1860static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1861{
1862 struct mtk_mac *mac = netdev_priv(dev);
1863
1864 if (!mac->phy_dev)
1865 return -ENODEV;
1866
1867 switch (cmd) {
1868 case SIOCGMIIPHY:
1869 case SIOCGMIIREG:
1870 case SIOCSMIIREG:
1871 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1872 default:
1873 break;
1874 }
1875
1876 return -EOPNOTSUPP;
1877}
1878
1879static int mtk_change_mtu(struct net_device *dev, int new_mtu)
1880{
1881 struct mtk_mac *mac = netdev_priv(dev);
1882 struct mtk_eth *eth = mac->hw;
1883 int frag_size, old_mtu;
1884 u32 fwd_cfg;
1885
1886 if (!eth->soc->jumbo_frame)
1887 return eth_change_mtu(dev, new_mtu);
1888
1889 frag_size = mtk_max_frag_size(new_mtu);
1890 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1891 return -EINVAL;
1892
1893 old_mtu = dev->mtu;
1894 dev->mtu = new_mtu;
1895
1896 /* return early if the buffer sizes will not change */
1897 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1898 return 0;
1899 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1900 return 0;
1901
1902 if (new_mtu <= ETH_DATA_LEN)
1903 eth->rx_ring[0].frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1904 else
1905 eth->rx_ring[0].frag_size = PAGE_SIZE;
1906 eth->rx_ring[0].rx_buf_size =
1907 mtk_max_buf_size(eth->rx_ring[0].frag_size);
1908
1909 if (!netif_running(dev))
1910 return 0;
1911
1912 mtk_stop(dev);
1913 fwd_cfg = mtk_r32(eth, MTK_GDMA1_FWD_CFG);
1914 if (new_mtu <= ETH_DATA_LEN) {
1915 fwd_cfg &= ~MTK_GDM1_JMB_EN;
1916 } else {
1917 fwd_cfg &= ~(MTK_GDM1_JMB_LEN_MASK << MTK_GDM1_JMB_LEN_SHIFT);
1918 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1919 MTK_GDM1_JMB_LEN_SHIFT) | MTK_GDM1_JMB_EN;
1920 }
1921 mtk_w32(eth, fwd_cfg, MTK_GDMA1_FWD_CFG);
1922
1923 return mtk_open(dev);
1924}
1925
1926static void mtk_pending_work(struct work_struct *work)
1927{
1928 struct mtk_mac *mac = container_of(work, struct mtk_mac, pending_work);
1929 struct mtk_eth *eth = mac->hw;
1930 struct net_device *dev = eth->netdev[mac->id];
1931 int err;
1932
1933 rtnl_lock();
1934 mtk_stop(dev);
1935
1936 err = mtk_open(dev);
1937 if (err) {
1938 netif_alert(eth, ifup, dev,
1939 "Driver up/down cycle failed, closing device.\n");
1940 dev_close(dev);
1941 }
1942 rtnl_unlock();
1943}
1944
1945static int mtk_cleanup(struct mtk_eth *eth)
1946{
1947 int i;
1948
1949 for (i = 0; i < eth->soc->mac_count; i++) {
1950 struct mtk_mac *mac = netdev_priv(eth->netdev[i]);
1951
1952 if (!eth->netdev[i])
1953 continue;
1954
1955 unregister_netdev(eth->netdev[i]);
1956 free_netdev(eth->netdev[i]);
1957 cancel_work_sync(&mac->pending_work);
1958 }
1959
1960 return 0;
1961}
1962
1963static const struct net_device_ops mtk_netdev_ops = {
1964 .ndo_init = mtk_init,
1965 .ndo_uninit = mtk_uninit,
1966 .ndo_open = mtk_open,
1967 .ndo_stop = mtk_stop,
1968 .ndo_start_xmit = mtk_start_xmit,
1969 .ndo_set_mac_address = mtk_set_mac_address,
1970 .ndo_validate_addr = eth_validate_addr,
1971 .ndo_do_ioctl = mtk_do_ioctl,
1972 .ndo_change_mtu = mtk_change_mtu,
1973 .ndo_tx_timeout = mtk_tx_timeout,
1974 .ndo_get_stats64 = mtk_get_stats64,
1975 .ndo_vlan_rx_add_vid = mtk_vlan_rx_add_vid,
1976 .ndo_vlan_rx_kill_vid = mtk_vlan_rx_kill_vid,
1977#ifdef CONFIG_NET_POLL_CONTROLLER
1978 .ndo_poll_controller = mtk_poll_controller,
1979#endif
1980};
1981
1982static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1983{
1984 struct mtk_mac *mac;
1985 const __be32 *_id = of_get_property(np, "reg", NULL);
1986 int id, err;
1987
1988 if (!_id) {
1989 dev_err(eth->dev, "missing mac id\n");
1990 return -EINVAL;
1991 }
1992 id = be32_to_cpup(_id);
1993 if (id >= eth->soc->mac_count || eth->netdev[id]) {
1994 dev_err(eth->dev, "%d is not a valid mac id\n", id);
1995 return -EINVAL;
1996 }
1997
1998 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
1999 if (!eth->netdev[id]) {
2000 dev_err(eth->dev, "alloc_etherdev failed\n");
2001 return -ENOMEM;
2002 }
2003 mac = netdev_priv(eth->netdev[id]);
2004 eth->mac[id] = mac;
2005 mac->id = id;
2006 mac->hw = eth;
2007 mac->of_node = np;
2008 INIT_WORK(&mac->pending_work, mtk_pending_work);
2009
2010 if (mtk_reg_table[MTK_REG_MTK_COUNTER_BASE]) {
2011 mac->hw_stats = devm_kzalloc(eth->dev,
2012 sizeof(*mac->hw_stats),
2013 GFP_KERNEL);
2014 if (!mac->hw_stats) {
2015 err = -ENOMEM;
2016 goto free_netdev;
2017 }
2018 spin_lock_init(&mac->hw_stats->stats_lock);
2019 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2020 }
2021
2022 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
2023 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2024 eth->netdev[id]->base_addr = (unsigned long)eth->base;
2025
2026 if (eth->soc->init_data)
2027 eth->soc->init_data(eth->soc, eth->netdev[id]);
2028
2029 eth->netdev[id]->vlan_features = eth->soc->hw_features &
2030 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2031 eth->netdev[id]->features |= eth->soc->hw_features;
2032
2033 if (mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE])
2034 eth->netdev[id]->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2035
2036 mtk_set_ethtool_ops(eth->netdev[id]);
2037
2038 err = register_netdev(eth->netdev[id]);
2039 if (err) {
2040 dev_err(eth->dev, "error bringing up device\n");
2041 err = -ENOMEM;
2042 goto free_netdev;
2043 }
2044 eth->netdev[id]->irq = eth->irq;
2045 netif_info(eth, probe, eth->netdev[id],
2046 "mediatek frame engine at 0x%08lx, irq %d\n",
2047 eth->netdev[id]->base_addr, eth->netdev[id]->irq);
2048
2049 return 0;
2050
2051free_netdev:
2052 free_netdev(eth->netdev[id]);
2053 return err;
2054}
2055
2056static int mtk_probe(struct platform_device *pdev)
2057{
2058 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2059 const struct of_device_id *match;
2060 struct device_node *mac_np;
2061 struct mtk_soc_data *soc;
2062 struct mtk_eth *eth;
2063 struct clk *sysclk;
2064 int err;
2065
2066 device_reset(&pdev->dev);
2067
2068 match = of_match_device(of_mtk_match, &pdev->dev);
2069 soc = (struct mtk_soc_data *)match->data;
2070
2071 if (soc->reg_table)
2072 mtk_reg_table = soc->reg_table;
2073
2074 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2075 if (!eth)
2076 return -ENOMEM;
2077
2078 eth->base = devm_ioremap_resource(&pdev->dev, res);
2079 if (IS_ERR(eth->base))
2080 return PTR_ERR(eth->base);
2081
2082 spin_lock_init(&eth->page_lock);
2083
2084 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2085 "mediatek,ethsys");
2086 if (IS_ERR(eth->ethsys))
2087 return PTR_ERR(eth->ethsys);
2088
2089 eth->irq = platform_get_irq(pdev, 0);
2090 if (eth->irq < 0) {
2091 dev_err(&pdev->dev, "no IRQ resource found\n");
2092 return -ENXIO;
2093 }
2094
2095 sysclk = devm_clk_get(&pdev->dev, NULL);
2096 if (IS_ERR(sysclk)) {
2097 dev_err(&pdev->dev,
2098 "the clock is not defined in the devicetree\n");
2099 return -ENXIO;
2100 }
2101 eth->sysclk = clk_get_rate(sysclk);
2102
2103 eth->switch_np = of_parse_phandle(pdev->dev.of_node,
2104 "mediatek,switch", 0);
2105 if (soc->has_switch && !eth->switch_np) {
2106 dev_err(&pdev->dev, "failed to read switch phandle\n");
2107 return -ENODEV;
2108 }
2109
2110 eth->dev = &pdev->dev;
2111 eth->soc = soc;
2112 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
2113
2114 err = mtk_init_hw(eth);
2115 if (err)
2116 return err;
2117
2118 if (eth->soc->mac_count > 1) {
2119 for_each_child_of_node(pdev->dev.of_node, mac_np) {
2120 if (!of_device_is_compatible(mac_np,
2121 "mediatek,eth-mac"))
2122 continue;
2123
2124 if (!of_device_is_available(mac_np))
2125 continue;
2126
2127 err = mtk_add_mac(eth, mac_np);
2128 if (err)
2129 goto err_free_dev;
2130 }
2131
2132 init_dummy_netdev(&eth->dummy_dev);
2133 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_poll,
2134 soc->napi_weight);
2135 } else {
2136 err = mtk_add_mac(eth, pdev->dev.of_node);
2137 if (err)
2138 goto err_free_dev;
2139 netif_napi_add(eth->netdev[0], &eth->rx_napi, mtk_poll,
2140 soc->napi_weight);
2141 }
2142
2143 platform_set_drvdata(pdev, eth);
2144
2145 return 0;
2146
2147err_free_dev:
2148 mtk_cleanup(eth);
2149 return err;
2150}
2151
2152static int mtk_remove(struct platform_device *pdev)
2153{
2154 struct mtk_eth *eth = platform_get_drvdata(pdev);
2155
2156 netif_napi_del(&eth->rx_napi);
2157 mtk_cleanup(eth);
2158 platform_set_drvdata(pdev, NULL);
2159
2160 return 0;
2161}
2162
2163static struct platform_driver mtk_driver = {
2164 .probe = mtk_probe,
2165 .remove = mtk_remove,
2166 .driver = {
2167 .name = "mtk_soc_eth",
2168 .of_match_table = of_mtk_match,
2169 },
2170};
2171
2172module_platform_driver(mtk_driver);
2173
2174MODULE_LICENSE("GPL");
2175MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2176MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
diff --git a/drivers/staging/mt7621-eth/mtk_eth_soc.h b/drivers/staging/mt7621-eth/mtk_eth_soc.h
deleted file mode 100644
index e6ed80433f49..000000000000
--- a/drivers/staging/mt7621-eth/mtk_eth_soc.h
+++ /dev/null
@@ -1,716 +0,0 @@
1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#ifndef MTK_ETH_H
16#define MTK_ETH_H
17
18#include <linux/mii.h>
19#include <linux/interrupt.h>
20#include <linux/netdevice.h>
21#include <linux/dma-mapping.h>
22#include <linux/phy.h>
23#include <linux/ethtool.h>
24#include <linux/version.h>
25#include <linux/atomic.h>
26
27/* these registers have different offsets depending on the SoC. we use a lookup
28 * table for these
29 */
30enum mtk_reg {
31 MTK_REG_PDMA_GLO_CFG = 0,
32 MTK_REG_PDMA_RST_CFG,
33 MTK_REG_DLY_INT_CFG,
34 MTK_REG_TX_BASE_PTR0,
35 MTK_REG_TX_MAX_CNT0,
36 MTK_REG_TX_CTX_IDX0,
37 MTK_REG_TX_DTX_IDX0,
38 MTK_REG_RX_BASE_PTR0,
39 MTK_REG_RX_MAX_CNT0,
40 MTK_REG_RX_CALC_IDX0,
41 MTK_REG_RX_DRX_IDX0,
42 MTK_REG_MTK_INT_ENABLE,
43 MTK_REG_MTK_INT_STATUS,
44 MTK_REG_MTK_DMA_VID_BASE,
45 MTK_REG_MTK_COUNTER_BASE,
46 MTK_REG_MTK_RST_GL,
47 MTK_REG_MTK_INT_STATUS2,
48 MTK_REG_COUNT
49};
50
51/* delayed interrupt bits */
52#define MTK_DELAY_EN_INT 0x80
53#define MTK_DELAY_MAX_INT 0x04
54#define MTK_DELAY_MAX_TOUT 0x04
55#define MTK_DELAY_TIME 20
56#define MTK_DELAY_CHAN (((MTK_DELAY_EN_INT | MTK_DELAY_MAX_INT) << 8) \
57 | MTK_DELAY_MAX_TOUT)
58#define MTK_DELAY_INIT ((MTK_DELAY_CHAN << 16) | MTK_DELAY_CHAN)
59#define MTK_PSE_FQFC_CFG_INIT 0x80504000
60#define MTK_PSE_FQFC_CFG_256Q 0xff908000
61
62/* interrupt bits */
63#define MTK_CNT_PPE_AF BIT(31)
64#define MTK_CNT_GDM_AF BIT(29)
65#define MTK_PSE_P2_FC BIT(26)
66#define MTK_PSE_BUF_DROP BIT(24)
67#define MTK_GDM_OTHER_DROP BIT(23)
68#define MTK_PSE_P1_FC BIT(22)
69#define MTK_PSE_P0_FC BIT(21)
70#define MTK_PSE_FQ_EMPTY BIT(20)
71#define MTK_GE1_STA_CHG BIT(18)
72#define MTK_TX_COHERENT BIT(17)
73#define MTK_RX_COHERENT BIT(16)
74#define MTK_TX_DONE_INT3 BIT(11)
75#define MTK_TX_DONE_INT2 BIT(10)
76#define MTK_TX_DONE_INT1 BIT(9)
77#define MTK_TX_DONE_INT0 BIT(8)
78#define MTK_RX_DONE_INT0 BIT(2)
79#define MTK_TX_DLY_INT BIT(1)
80#define MTK_RX_DLY_INT BIT(0)
81
82#define MTK_RX_DONE_INT MTK_RX_DONE_INT0
83#define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
84 MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
85
86#define RT5350_RX_DLY_INT BIT(30)
87#define RT5350_TX_DLY_INT BIT(28)
88#define RT5350_RX_DONE_INT1 BIT(17)
89#define RT5350_RX_DONE_INT0 BIT(16)
90#define RT5350_TX_DONE_INT3 BIT(3)
91#define RT5350_TX_DONE_INT2 BIT(2)
92#define RT5350_TX_DONE_INT1 BIT(1)
93#define RT5350_TX_DONE_INT0 BIT(0)
94
95#define RT5350_RX_DONE_INT (RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1)
96#define RT5350_TX_DONE_INT (RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \
97 RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3)
98
99/* registers */
100#define MTK_GDMA_OFFSET 0x0020
101#define MTK_PSE_OFFSET 0x0040
102#define MTK_GDMA2_OFFSET 0x0060
103#define MTK_CDMA_OFFSET 0x0080
104#define MTK_DMA_VID0 0x00a8
105#define MTK_PDMA_OFFSET 0x0100
106#define MTK_PPE_OFFSET 0x0200
107#define MTK_CMTABLE_OFFSET 0x0400
108#define MTK_POLICYTABLE_OFFSET 0x1000
109
110#define MT7621_GDMA_OFFSET 0x0500
111#define MT7620_GDMA_OFFSET 0x0600
112
113#define RT5350_PDMA_OFFSET 0x0800
114#define RT5350_SDM_OFFSET 0x0c00
115
116#define MTK_MDIO_ACCESS 0x00
117#define MTK_MDIO_CFG 0x04
118#define MTK_GLO_CFG 0x08
119#define MTK_RST_GL 0x0C
120#define MTK_INT_STATUS 0x10
121#define MTK_INT_ENABLE 0x14
122#define MTK_MDIO_CFG2 0x18
123#define MTK_FOC_TS_T 0x1C
124
125#define MTK_GDMA1_FWD_CFG (MTK_GDMA_OFFSET + 0x00)
126#define MTK_GDMA1_SCH_CFG (MTK_GDMA_OFFSET + 0x04)
127#define MTK_GDMA1_SHPR_CFG (MTK_GDMA_OFFSET + 0x08)
128#define MTK_GDMA1_MAC_ADRL (MTK_GDMA_OFFSET + 0x0C)
129#define MTK_GDMA1_MAC_ADRH (MTK_GDMA_OFFSET + 0x10)
130
131#define MTK_GDMA2_FWD_CFG (MTK_GDMA2_OFFSET + 0x00)
132#define MTK_GDMA2_SCH_CFG (MTK_GDMA2_OFFSET + 0x04)
133#define MTK_GDMA2_SHPR_CFG (MTK_GDMA2_OFFSET + 0x08)
134#define MTK_GDMA2_MAC_ADRL (MTK_GDMA2_OFFSET + 0x0C)
135#define MTK_GDMA2_MAC_ADRH (MTK_GDMA2_OFFSET + 0x10)
136
137#define MTK_PSE_FQ_CFG (MTK_PSE_OFFSET + 0x00)
138#define MTK_CDMA_FC_CFG (MTK_PSE_OFFSET + 0x04)
139#define MTK_GDMA1_FC_CFG (MTK_PSE_OFFSET + 0x08)
140#define MTK_GDMA2_FC_CFG (MTK_PSE_OFFSET + 0x0C)
141
142#define MTK_CDMA_CSG_CFG (MTK_CDMA_OFFSET + 0x00)
143#define MTK_CDMA_SCH_CFG (MTK_CDMA_OFFSET + 0x04)
144
145#define MT7621_GDMA_FWD_CFG(x) (MT7621_GDMA_OFFSET + (x * 0x1000))
146
147/* FIXME this might be different for different SOCs */
148#define MT7620_GDMA1_FWD_CFG (MT7621_GDMA_OFFSET + 0x00)
149
150#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
151#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
152#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
153#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
154#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
155#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
156#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
157#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
158#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
159#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
160#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
161#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
162#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
163#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
164#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
165#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
166#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
167#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
168#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
169#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
170#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
171#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
172#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
173#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
174#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
175#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
176#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
177#define RT5350_MTK_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
178#define RT5350_MTK_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
179#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
180
181#define MTK_PDMA_GLO_CFG (MTK_PDMA_OFFSET + 0x00)
182#define MTK_PDMA_RST_CFG (MTK_PDMA_OFFSET + 0x04)
183#define MTK_PDMA_SCH_CFG (MTK_PDMA_OFFSET + 0x08)
184#define MTK_DLY_INT_CFG (MTK_PDMA_OFFSET + 0x0C)
185#define MTK_TX_BASE_PTR0 (MTK_PDMA_OFFSET + 0x10)
186#define MTK_TX_MAX_CNT0 (MTK_PDMA_OFFSET + 0x14)
187#define MTK_TX_CTX_IDX0 (MTK_PDMA_OFFSET + 0x18)
188#define MTK_TX_DTX_IDX0 (MTK_PDMA_OFFSET + 0x1C)
189#define MTK_TX_BASE_PTR1 (MTK_PDMA_OFFSET + 0x20)
190#define MTK_TX_MAX_CNT1 (MTK_PDMA_OFFSET + 0x24)
191#define MTK_TX_CTX_IDX1 (MTK_PDMA_OFFSET + 0x28)
192#define MTK_TX_DTX_IDX1 (MTK_PDMA_OFFSET + 0x2C)
193#define MTK_RX_BASE_PTR0 (MTK_PDMA_OFFSET + 0x30)
194#define MTK_RX_MAX_CNT0 (MTK_PDMA_OFFSET + 0x34)
195#define MTK_RX_CALC_IDX0 (MTK_PDMA_OFFSET + 0x38)
196#define MTK_RX_DRX_IDX0 (MTK_PDMA_OFFSET + 0x3C)
197#define MTK_TX_BASE_PTR2 (MTK_PDMA_OFFSET + 0x40)
198#define MTK_TX_MAX_CNT2 (MTK_PDMA_OFFSET + 0x44)
199#define MTK_TX_CTX_IDX2 (MTK_PDMA_OFFSET + 0x48)
200#define MTK_TX_DTX_IDX2 (MTK_PDMA_OFFSET + 0x4C)
201#define MTK_TX_BASE_PTR3 (MTK_PDMA_OFFSET + 0x50)
202#define MTK_TX_MAX_CNT3 (MTK_PDMA_OFFSET + 0x54)
203#define MTK_TX_CTX_IDX3 (MTK_PDMA_OFFSET + 0x58)
204#define MTK_TX_DTX_IDX3 (MTK_PDMA_OFFSET + 0x5C)
205#define MTK_RX_BASE_PTR1 (MTK_PDMA_OFFSET + 0x60)
206#define MTK_RX_MAX_CNT1 (MTK_PDMA_OFFSET + 0x64)
207#define MTK_RX_CALC_IDX1 (MTK_PDMA_OFFSET + 0x68)
208#define MTK_RX_DRX_IDX1 (MTK_PDMA_OFFSET + 0x6C)
209
210/* Switch DMA configuration */
211#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00)
212#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04)
213#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08)
214#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C)
215#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10)
216#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100)
217#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104)
218#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108)
219#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C)
220#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110)
221
222#define RT5350_SDM_ICS_EN BIT(16)
223#define RT5350_SDM_TCS_EN BIT(17)
224#define RT5350_SDM_UCS_EN BIT(18)
225
226/* QDMA registers */
227#define MTK_QTX_CFG(x) (0x1800 + (x * 0x10))
228#define MTK_QTX_SCH(x) (0x1804 + (x * 0x10))
229#define MTK_QRX_BASE_PTR0 0x1900
230#define MTK_QRX_MAX_CNT0 0x1904
231#define MTK_QRX_CRX_IDX0 0x1908
232#define MTK_QRX_DRX_IDX0 0x190C
233#define MTK_QDMA_GLO_CFG 0x1A04
234#define MTK_QDMA_RST_IDX 0x1A08
235#define MTK_QDMA_DELAY_INT 0x1A0C
236#define MTK_QDMA_FC_THRES 0x1A10
237#define MTK_QMTK_INT_STATUS 0x1A18
238#define MTK_QMTK_INT_ENABLE 0x1A1C
239#define MTK_QDMA_HRED2 0x1A44
240
241#define MTK_QTX_CTX_PTR 0x1B00
242#define MTK_QTX_DTX_PTR 0x1B04
243
244#define MTK_QTX_CRX_PTR 0x1B10
245#define MTK_QTX_DRX_PTR 0x1B14
246
247#define MTK_QDMA_FQ_HEAD 0x1B20
248#define MTK_QDMA_FQ_TAIL 0x1B24
249#define MTK_QDMA_FQ_CNT 0x1B28
250#define MTK_QDMA_FQ_BLEN 0x1B2C
251
252#define QDMA_PAGE_SIZE 2048
253#define QDMA_TX_OWNER_CPU BIT(31)
254#define QDMA_TX_SWC BIT(14)
255#define TX_QDMA_SDL(_x) (((_x) & 0x3fff) << 16)
256#define QDMA_RES_THRES 4
257
258/* MDIO_CFG register bits */
259#define MTK_MDIO_CFG_AUTO_POLL_EN BIT(29)
260#define MTK_MDIO_CFG_GP1_BP_EN BIT(16)
261#define MTK_MDIO_CFG_GP1_FRC_EN BIT(15)
262#define MTK_MDIO_CFG_GP1_SPEED_10 (0 << 13)
263#define MTK_MDIO_CFG_GP1_SPEED_100 (1 << 13)
264#define MTK_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
265#define MTK_MDIO_CFG_GP1_DUPLEX BIT(12)
266#define MTK_MDIO_CFG_GP1_FC_TX BIT(11)
267#define MTK_MDIO_CFG_GP1_FC_RX BIT(10)
268#define MTK_MDIO_CFG_GP1_LNK_DWN BIT(9)
269#define MTK_MDIO_CFG_GP1_AN_FAIL BIT(8)
270#define MTK_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
271#define MTK_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
272#define MTK_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
273#define MTK_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
274#define MTK_MDIO_CFG_TURBO_MII_FREQ BIT(5)
275#define MTK_MDIO_CFG_TURBO_MII_MODE BIT(4)
276#define MTK_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
277#define MTK_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
278#define MTK_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
279#define MTK_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
280#define MTK_MDIO_CFG_TX_CLK_SKEW_0 0
281#define MTK_MDIO_CFG_TX_CLK_SKEW_200 1
282#define MTK_MDIO_CFG_TX_CLK_SKEW_400 2
283#define MTK_MDIO_CFG_TX_CLK_SKEW_INV 3
284
285/* uni-cast port */
286#define MTK_GDM1_JMB_LEN_MASK 0xf
287#define MTK_GDM1_JMB_LEN_SHIFT 28
288#define MTK_GDM1_ICS_EN BIT(22)
289#define MTK_GDM1_TCS_EN BIT(21)
290#define MTK_GDM1_UCS_EN BIT(20)
291#define MTK_GDM1_JMB_EN BIT(19)
292#define MTK_GDM1_STRPCRC BIT(16)
293#define MTK_GDM1_UFRC_P_CPU (0 << 12)
294#define MTK_GDM1_UFRC_P_GDMA1 (1 << 12)
295#define MTK_GDM1_UFRC_P_PPE (6 << 12)
296
297/* checksums */
298#define MTK_ICS_GEN_EN BIT(2)
299#define MTK_UCS_GEN_EN BIT(1)
300#define MTK_TCS_GEN_EN BIT(0)
301
302/* dma mode */
303#define MTK_PDMA BIT(0)
304#define MTK_QDMA BIT(1)
305#define MTK_PDMA_RX_QDMA_TX (MTK_PDMA | MTK_QDMA)
306
307/* dma ring */
308#define MTK_PST_DRX_IDX0 BIT(16)
309#define MTK_PST_DTX_IDX3 BIT(3)
310#define MTK_PST_DTX_IDX2 BIT(2)
311#define MTK_PST_DTX_IDX1 BIT(1)
312#define MTK_PST_DTX_IDX0 BIT(0)
313
314#define MTK_RX_2B_OFFSET BIT(31)
315#define MTK_TX_WB_DDONE BIT(6)
316#define MTK_RX_DMA_BUSY BIT(3)
317#define MTK_TX_DMA_BUSY BIT(1)
318#define MTK_RX_DMA_EN BIT(2)
319#define MTK_TX_DMA_EN BIT(0)
320
321#define MTK_PDMA_SIZE_4DWORDS (0 << 4)
322#define MTK_PDMA_SIZE_8DWORDS (1 << 4)
323#define MTK_PDMA_SIZE_16DWORDS (2 << 4)
324
325#define MTK_US_CYC_CNT_MASK 0xff
326#define MTK_US_CYC_CNT_SHIFT 0x8
327#define MTK_US_CYC_CNT_DIVISOR 1000000
328
329/* PDMA descriptor rxd2 */
330#define RX_DMA_DONE BIT(31)
331#define RX_DMA_LSO BIT(30)
332#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
333#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
334#define RX_DMA_TAG BIT(15)
335
336/* PDMA descriptor rxd3 */
337#define RX_DMA_TPID(_x) (((_x) >> 16) & 0xffff)
338#define RX_DMA_VID(_x) ((_x) & 0xfff)
339
340/* PDMA descriptor rxd4 */
341#define RX_DMA_L4VALID BIT(30)
342#define RX_DMA_FPORT_SHIFT 19
343#define RX_DMA_FPORT_MASK 0x7
344
345struct mtk_rx_dma {
346 unsigned int rxd1;
347 unsigned int rxd2;
348 unsigned int rxd3;
349 unsigned int rxd4;
350} __packed __aligned(4);
351
352/* PDMA tx descriptor bits */
353#define TX_DMA_BUF_LEN 0x3fff
354#define TX_DMA_PLEN0_MASK (TX_DMA_BUF_LEN << 16)
355#define TX_DMA_PLEN0(_x) (((_x) & TX_DMA_BUF_LEN) << 16)
356#define TX_DMA_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
357#define TX_DMA_GET_PLEN0(_x) (((_x) >> 16) & TX_DMA_BUF_LEN)
358#define TX_DMA_GET_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
359#define TX_DMA_LS1 BIT(14)
360#define TX_DMA_LS0 BIT(30)
361#define TX_DMA_DONE BIT(31)
362#define TX_DMA_FPORT_SHIFT 25
363#define TX_DMA_FPORT_MASK 0x7
364#define TX_DMA_INS_VLAN_MT7621 BIT(16)
365#define TX_DMA_INS_VLAN BIT(7)
366#define TX_DMA_INS_PPPOE BIT(12)
367#define TX_DMA_TAG BIT(15)
368#define TX_DMA_TAG_MASK BIT(15)
369#define TX_DMA_QN(_x) ((_x) << 16)
370#define TX_DMA_PN(_x) ((_x) << 24)
371#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
372#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
373#define TX_DMA_UDF BIT(20)
374#define TX_DMA_CHKSUM (0x7 << 29)
375#define TX_DMA_TSO BIT(28)
376#define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
377
378/* frame engine counters */
379#define MTK_PPE_AC_BCNT0 (MTK_CMTABLE_OFFSET + 0x00)
380#define MTK_GDMA1_TX_GBCNT (MTK_CMTABLE_OFFSET + 0x300)
381#define MTK_GDMA2_TX_GBCNT (MTK_GDMA1_TX_GBCNT + 0x40)
382
383/* phy device flags */
384#define MTK_PHY_FLAG_PORT BIT(0)
385#define MTK_PHY_FLAG_ATTACH BIT(1)
386
387struct mtk_tx_dma {
388 unsigned int txd1;
389 unsigned int txd2;
390 unsigned int txd3;
391 unsigned int txd4;
392} __packed __aligned(4);
393
394struct mtk_eth;
395struct mtk_mac;
396
397/* manage the attached phys */
398struct mtk_phy {
399 spinlock_t lock;
400
401 struct phy_device *phy[8];
402 struct device_node *phy_node[8];
403 const __be32 *phy_fixed[8];
404 int duplex[8];
405 int speed[8];
406 int tx_fc[8];
407 int rx_fc[8];
408 int (*connect)(struct mtk_mac *mac);
409 void (*disconnect)(struct mtk_mac *mac);
410 void (*start)(struct mtk_mac *mac);
411 void (*stop)(struct mtk_mac *mac);
412};
413
414/* struct mtk_soc_data - the structure that holds the SoC specific data
415 * @reg_table: Some of the legacy registers changed their location
416 * over time. Their offsets are stored in this table
417 *
418 * @init_data: Some features depend on the silicon revision. This
419 * callback allows runtime modification of the content of
420 * this struct
421 * @reset_fe: This callback is used to trigger the reset of the frame
422 * engine
423 * @set_mac: This callback is used to set the unicast mac address
424 * filter
425 * @fwd_config: This callback is used to setup the forward config
426 * register of the MAC
427 * @switch_init: This callback is used to bring up the switch core
428 * @port_init: Some SoCs have ports that can be router to a switch port
429 * or an external PHY. This callback is used to setup these
430 * ports.
431 * @has_carrier: This callback allows driver to check if there is a cable
432 * attached.
433 * @mdio_init: This callbck is used to setup the MDIO bus if one is
434 * present
435 * @mdio_cleanup: This callback is used to cleanup the MDIO state.
436 * @mdio_write: This callback is used to write data to the MDIO bus.
437 * @mdio_read: This callback is used to write data to the MDIO bus.
438 * @mdio_adjust_link: This callback is used to apply the PHY settings.
439 * @piac_offset: the PIAC register has a different different base offset
440 * @hw_features: feature set depends on the SoC type
441 * @dma_ring_size: allow GBit SoCs to set bigger rings than FE SoCs
442 * @napi_weight: allow GBit SoCs to set bigger napi weight than FE SoCs
443 * @dma_type: SoCs is PDMA, QDMA or a mix of the 2
444 * @pdma_glo_cfg: the default DMA configuration
445 * @rx_int: the TX interrupt bits used by the SoC
446 * @tx_int: the TX interrupt bits used by the SoC
447 * @status_int: the Status interrupt bits used by the SoC
448 * @checksum_bit: the bits used to turn on HW checksumming
449 * @txd4: default value of the TXD4 descriptor
450 * @mac_count: the number of MACs that the SoC has
451 * @new_stats: there is a old and new way to read hardware stats
452 * registers
453 * @jumbo_frame: does the SoC support jumbo frames ?
454 * @rx_2b_offset: tell the rx dma to offset the data by 2 bytes
455 * @rx_sg_dma: scatter gather support
456 * @padding_64b enable 64 bit padding
457 * @padding_bug: rt2880 has a padding bug
458 * @has_switch: does the SoC have a built-in switch
459 *
460 * Although all of the supported SoCs share the same basic functionality, there
461 * are several SoC specific functions and features that we need to support. This
462 * struct holds the SoC specific data so that the common core can figure out
463 * how to setup and use these differences.
464 */
465struct mtk_soc_data {
466 const u16 *reg_table;
467
468 void (*init_data)(struct mtk_soc_data *data, struct net_device *netdev);
469 void (*reset_fe)(struct mtk_eth *eth);
470 void (*set_mac)(struct mtk_mac *mac, unsigned char *macaddr);
471 int (*fwd_config)(struct mtk_eth *eth);
472 int (*switch_init)(struct mtk_eth *eth);
473 void (*port_init)(struct mtk_eth *eth, struct mtk_mac *mac,
474 struct device_node *port);
475 int (*has_carrier)(struct mtk_eth *eth);
476 int (*mdio_init)(struct mtk_eth *eth);
477 void (*mdio_cleanup)(struct mtk_eth *eth);
478 int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg,
479 u16 val);
480 int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
481 void (*mdio_adjust_link)(struct mtk_eth *eth, int port);
482 u32 piac_offset;
483 netdev_features_t hw_features;
484 u32 dma_ring_size;
485 u32 napi_weight;
486 u32 dma_type;
487 u32 pdma_glo_cfg;
488 u32 rx_int;
489 u32 tx_int;
490 u32 status_int;
491 u32 checksum_bit;
492 u32 txd4;
493 u32 mac_count;
494
495 u32 new_stats:1;
496 u32 jumbo_frame:1;
497 u32 rx_2b_offset:1;
498 u32 rx_sg_dma:1;
499 u32 padding_64b:1;
500 u32 padding_bug:1;
501 u32 has_switch:1;
502};
503
504#define MTK_STAT_OFFSET 0x40
505
506/* struct mtk_hw_stats - the structure that holds the traffic statistics.
507 * @stats_lock: make sure that stats operations are atomic
508 * @reg_offset: the status register offset of the SoC
509 * @syncp: the refcount
510 *
511 * All of the supported SoCs have hardware counters for traffic statstics.
512 * Whenever the status IRQ triggers we can read the latest stats from these
513 * counters and store them in this struct.
514 */
515struct mtk_hw_stats {
516 spinlock_t stats_lock;
517 u32 reg_offset;
518 struct u64_stats_sync syncp;
519
520 u64 tx_bytes;
521 u64 tx_packets;
522 u64 tx_skip;
523 u64 tx_collisions;
524 u64 rx_bytes;
525 u64 rx_packets;
526 u64 rx_overflow;
527 u64 rx_fcs_errors;
528 u64 rx_short_errors;
529 u64 rx_long_errors;
530 u64 rx_checksum_errors;
531 u64 rx_flow_control_packets;
532};
533
534/* PDMA descriptor can point at 1-2 segments. This enum allows us to track how
535 * memory was allocated so that it can be freed properly
536 */
537enum mtk_tx_flags {
538 MTK_TX_FLAGS_SINGLE0 = 0x01,
539 MTK_TX_FLAGS_PAGE0 = 0x02,
540 MTK_TX_FLAGS_PAGE1 = 0x04,
541};
542
543/* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at
544 * by the TX descriptor s
545 * @skb: The SKB pointer of the packet being sent
546 * @dma_addr0: The base addr of the first segment
547 * @dma_len0: The length of the first segment
548 * @dma_addr1: The base addr of the second segment
549 * @dma_len1: The length of the second segment
550 */
551struct mtk_tx_buf {
552 struct sk_buff *skb;
553 u32 flags;
554 DEFINE_DMA_UNMAP_ADDR(dma_addr0);
555 DEFINE_DMA_UNMAP_LEN(dma_len0);
556 DEFINE_DMA_UNMAP_ADDR(dma_addr1);
557 DEFINE_DMA_UNMAP_LEN(dma_len1);
558};
559
560/* struct mtk_tx_ring - This struct holds info describing a TX ring
561 * @tx_dma: The descriptor ring
562 * @tx_buf: The memory pointed at by the ring
563 * @tx_phys: The physical addr of tx_buf
564 * @tx_next_free: Pointer to the next free descriptor
565 * @tx_last_free: Pointer to the last free descriptor
566 * @tx_thresh: The threshold of minimum amount of free descriptors
567 * @tx_map: Callback to map a new packet into the ring
568 * @tx_poll: Callback for the housekeeping function
569 * @tx_clean: Callback for the cleanup function
570 * @tx_ring_size: How many descriptors are in the ring
571 * @tx_free_idx: The index of th next free descriptor
572 * @tx_next_idx: QDMA uses a linked list. This element points to the next
573 * free descriptor in the list
574 * @tx_free_count: QDMA uses a linked list. Track how many free descriptors
575 * are present
576 */
577struct mtk_tx_ring {
578 struct mtk_tx_dma *tx_dma;
579 struct mtk_tx_buf *tx_buf;
580 dma_addr_t tx_phys;
581 struct mtk_tx_dma *tx_next_free;
582 struct mtk_tx_dma *tx_last_free;
583 u16 tx_thresh;
584 int (*tx_map)(struct sk_buff *skb, struct net_device *dev, int tx_num,
585 struct mtk_tx_ring *ring, bool gso);
586 int (*tx_poll)(struct mtk_eth *eth, int budget, bool *tx_again);
587 void (*tx_clean)(struct mtk_eth *eth);
588
589 /* PDMA only */
590 u16 tx_ring_size;
591 u16 tx_free_idx;
592
593 /* QDMA only */
594 u16 tx_next_idx;
595 atomic_t tx_free_count;
596};
597
598/* struct mtk_rx_ring - This struct holds info describing a RX ring
599 * @rx_dma: The descriptor ring
600 * @rx_data: The memory pointed at by the ring
601 * @trx_phys: The physical addr of rx_buf
602 * @rx_ring_size: How many descriptors are in the ring
603 * @rx_buf_size: The size of each packet buffer
604 * @rx_calc_idx: The current head of ring
605 */
606struct mtk_rx_ring {
607 struct mtk_rx_dma *rx_dma;
608 u8 **rx_data;
609 dma_addr_t rx_phys;
610 u16 rx_ring_size;
611 u16 frag_size;
612 u16 rx_buf_size;
613 u16 rx_calc_idx;
614};
615
616/* currently no SoC has more than 2 macs */
617#define MTK_MAX_DEVS 2
618
619/* struct mtk_eth - This is the main datasructure for holding the state
620 * of the driver
621 * @dev: The device pointer
622 * @base: The mapped register i/o base
623 * @page_lock: Make sure that register operations are atomic
624 * @soc: pointer to our SoC specific data
625 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a
626 * dummy for NAPI to work
627 * @netdev: The netdev instances
628 * @mac: Each netdev is linked to a physical MAC
629 * @switch_np: The phandle for the switch
630 * @irq: The IRQ that we are using
631 * @msg_enable: Ethtool msg level
632 * @ysclk: The sysclk rate - neeed for calibration
633 * @ethsys: The register map pointing at the range used to setup
634 * MII modes
635 * @dma_refcnt: track how many netdevs are using the DMA engine
636 * @tx_ring: Pointer to the memore holding info about the TX ring
637 * @rx_ring: Pointer to the memore holding info about the RX ring
638 * @rx_napi: The NAPI struct
639 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring
640 * @scratch_head: The scratch memory that scratch_ring points to.
641 * @phy: Info about the attached PHYs
642 * @mii_bus: If there is a bus we need to create an instance for it
643 * @link: Track if the ports have a physical link
644 * @sw_priv: Pointer to the switches private data
645 * @vlan_map: RX VID tracking
646 */
647
648struct mtk_eth {
649 struct device *dev;
650 void __iomem *base;
651 spinlock_t page_lock;
652 struct mtk_soc_data *soc;
653 struct net_device dummy_dev;
654 struct net_device *netdev[MTK_MAX_DEVS];
655 struct mtk_mac *mac[MTK_MAX_DEVS];
656 struct device_node *switch_np;
657 int irq;
658 u32 msg_enable;
659 unsigned long sysclk;
660 struct regmap *ethsys;
661 atomic_t dma_refcnt;
662 struct mtk_tx_ring tx_ring;
663 struct mtk_rx_ring rx_ring[2];
664 struct napi_struct rx_napi;
665 struct mtk_tx_dma *scratch_ring;
666 void *scratch_head;
667 struct mtk_phy *phy;
668 struct mii_bus *mii_bus;
669 int link[8];
670 void *sw_priv;
671 unsigned long vlan_map;
672};
673
674/* struct mtk_mac - the structure that holds the info about the MACs of the
675 * SoC
676 * @id: The number of the MAC
677 * @of_node: Our devicetree node
678 * @hw: Backpointer to our main datastruture
679 * @hw_stats: Packet statistics counter
680 * @phy_dev: The attached PHY if available
681 * @phy_flags: The PHYs flags
682 * @pending_work: The workqueue used to reset the dma ring
683 */
684struct mtk_mac {
685 int id;
686 struct device_node *of_node;
687 struct mtk_eth *hw;
688 struct mtk_hw_stats *hw_stats;
689 struct phy_device *phy_dev;
690 u32 phy_flags;
691 struct work_struct pending_work;
692};
693
694/* the struct describing the SoC. these are declared in the soc_xyz.c files */
695extern const struct of_device_id of_mtk_match[];
696
697/* read the hardware status register */
698void mtk_stats_update_mac(struct mtk_mac *mac);
699
700/* default checksum setup handler */
701void mtk_reset(struct mtk_eth *eth, u32 reset_bits);
702
703/* register i/o wrappers */
704void mtk_w32(struct mtk_eth *eth, u32 val, unsigned int reg);
705u32 mtk_r32(struct mtk_eth *eth, unsigned int reg);
706
707/* default clock calibration handler */
708int mtk_set_clock_cycle(struct mtk_eth *eth);
709
710/* default checksum setup handler */
711void mtk_csum_config(struct mtk_eth *eth);
712
713/* default forward config handler */
714void mtk_fwd_config(struct mtk_eth *eth);
715
716#endif /* MTK_ETH_H */
diff --git a/drivers/staging/mt7621-eth/soc_mt7621.c b/drivers/staging/mt7621-eth/soc_mt7621.c
deleted file mode 100644
index 5d63b5d96f6b..000000000000
--- a/drivers/staging/mt7621-eth/soc_mt7621.c
+++ /dev/null
@@ -1,161 +0,0 @@
1/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/if_vlan.h>
18#include <linux/of_net.h>
19
20#include <asm/mach-ralink/ralink_regs.h>
21
22#include "mtk_eth_soc.h"
23#include "gsw_mt7620.h"
24#include "mdio.h"
25
26#define MT7620_CDMA_CSG_CFG 0x400
27#define MT7621_CDMP_IG_CTRL (MT7620_CDMA_CSG_CFG + 0x00)
28#define MT7621_CDMP_EG_CTRL (MT7620_CDMA_CSG_CFG + 0x04)
29#define MT7621_RESET_FE BIT(6)
30#define MT7621_L4_VALID BIT(24)
31
32#define MT7621_TX_DMA_UDF BIT(19)
33
34#define CDMA_ICS_EN BIT(2)
35#define CDMA_UCS_EN BIT(1)
36#define CDMA_TCS_EN BIT(0)
37
38#define GDMA_ICS_EN BIT(22)
39#define GDMA_TCS_EN BIT(21)
40#define GDMA_UCS_EN BIT(20)
41
42/* frame engine counters */
43#define MT7621_REG_MIB_OFFSET 0x2000
44#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
45#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
46#define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
47
48#define GSW_REG_GDMA1_MAC_ADRL 0x508
49#define GSW_REG_GDMA1_MAC_ADRH 0x50C
50#define GSW_REG_GDMA2_MAC_ADRL 0x1508
51#define GSW_REG_GDMA2_MAC_ADRH 0x150C
52
53#define MT7621_MTK_RST_GL 0x04
54#define MT7620_MTK_INT_STATUS2 0x08
55
56/* MTK_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
57 * but after test it should be BIT(13).
58 */
59#define MT7621_MTK_GDM1_AF BIT(28)
60#define MT7621_MTK_GDM2_AF BIT(29)
61
62static const u16 mt7621_reg_table[MTK_REG_COUNT] = {
63 [MTK_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
64 [MTK_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
65 [MTK_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
66 [MTK_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
67 [MTK_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
68 [MTK_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
69 [MTK_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
70 [MTK_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
71 [MTK_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
72 [MTK_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
73 [MTK_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
74 [MTK_REG_MTK_INT_ENABLE] = RT5350_MTK_INT_ENABLE,
75 [MTK_REG_MTK_INT_STATUS] = RT5350_MTK_INT_STATUS,
76 [MTK_REG_MTK_DMA_VID_BASE] = 0,
77 [MTK_REG_MTK_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
78 [MTK_REG_MTK_RST_GL] = MT7621_MTK_RST_GL,
79 [MTK_REG_MTK_INT_STATUS2] = MT7620_MTK_INT_STATUS2,
80};
81
82static void mt7621_mtk_reset(struct mtk_eth *eth)
83{
84 mtk_reset(eth, MT7621_RESET_FE);
85}
86
87static int mt7621_fwd_config(struct mtk_eth *eth)
88{
89 /* Setup GMAC1 only, there is no support for GMAC2 yet */
90 mtk_w32(eth, mtk_r32(eth, MT7620_GDMA1_FWD_CFG) & ~0xffff,
91 MT7620_GDMA1_FWD_CFG);
92
93 /* Enable RX checksum */
94 mtk_w32(eth, mtk_r32(eth, MT7620_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
95 GDMA_TCS_EN | GDMA_UCS_EN),
96 MT7620_GDMA1_FWD_CFG);
97
98 /* Enable RX VLan Offloading */
99 mtk_w32(eth, 0, MT7621_CDMP_EG_CTRL);
100
101 return 0;
102}
103
104static void mt7621_set_mac(struct mtk_mac *mac, unsigned char *hwaddr)
105{
106 unsigned long flags;
107
108 spin_lock_irqsave(&mac->hw->page_lock, flags);
109 if (mac->id == 0) {
110 mtk_w32(mac->hw, (hwaddr[0] << 8) | hwaddr[1],
111 GSW_REG_GDMA1_MAC_ADRH);
112 mtk_w32(mac->hw, (hwaddr[2] << 24) | (hwaddr[3] << 16) |
113 (hwaddr[4] << 8) | hwaddr[5],
114 GSW_REG_GDMA1_MAC_ADRL);
115 }
116 if (mac->id == 1) {
117 mtk_w32(mac->hw, (hwaddr[0] << 8) | hwaddr[1],
118 GSW_REG_GDMA2_MAC_ADRH);
119 mtk_w32(mac->hw, (hwaddr[2] << 24) | (hwaddr[3] << 16) |
120 (hwaddr[4] << 8) | hwaddr[5],
121 GSW_REG_GDMA2_MAC_ADRL);
122 }
123 spin_unlock_irqrestore(&mac->hw->page_lock, flags);
124}
125
126static struct mtk_soc_data mt7621_data = {
127 .hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
128 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
129 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
130 NETIF_F_IPV6_CSUM,
131 .dma_type = MTK_PDMA,
132 .dma_ring_size = 256,
133 .napi_weight = 64,
134 .new_stats = 1,
135 .padding_64b = 1,
136 .rx_2b_offset = 1,
137 .rx_sg_dma = 1,
138 .has_switch = 1,
139 .mac_count = 2,
140 .reset_fe = mt7621_mtk_reset,
141 .set_mac = mt7621_set_mac,
142 .fwd_config = mt7621_fwd_config,
143 .switch_init = mtk_gsw_init,
144 .reg_table = mt7621_reg_table,
145 .pdma_glo_cfg = MTK_PDMA_SIZE_16DWORDS,
146 .rx_int = RT5350_RX_DONE_INT,
147 .tx_int = RT5350_TX_DONE_INT,
148 .status_int = MT7621_MTK_GDM1_AF | MT7621_MTK_GDM2_AF,
149 .checksum_bit = MT7621_L4_VALID,
150 .has_carrier = mt7620_has_carrier,
151 .mdio_read = mt7620_mdio_read,
152 .mdio_write = mt7620_mdio_write,
153 .mdio_adjust_link = mt7620_mdio_link_adjust,
154};
155
156const struct of_device_id of_mtk_match[] = {
157 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
158 {},
159};
160
161MODULE_DEVICE_TABLE(of, of_mtk_match);
diff --git a/drivers/staging/mt7621-pci/Kconfig b/drivers/staging/mt7621-pci/Kconfig
index d33533872a16..c8fa17cfa807 100644
--- a/drivers/staging/mt7621-pci/Kconfig
+++ b/drivers/staging/mt7621-pci/Kconfig
@@ -1,6 +1,7 @@
1config PCI_MT7621 1config PCI_MT7621
2 tristate "MediaTek MT7621 PCI Controller" 2 tristate "MediaTek MT7621 PCI Controller"
3 depends on RALINK 3 depends on RALINK
4 depends on PCI
4 select PCI_DRIVERS_GENERIC 5 select PCI_DRIVERS_GENERIC
5 help 6 help
6 This selects a driver for the MediaTek MT7621 PCI Controller. 7 This selects a driver for the MediaTek MT7621 PCI Controller.
diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c
index d6248eecf123..2aee64fdaec5 100644
--- a/drivers/staging/octeon/ethernet-mdio.c
+++ b/drivers/staging/octeon/ethernet-mdio.c
@@ -163,7 +163,7 @@ int cvm_oct_phy_setup_device(struct net_device *dev)
163 goto no_phy; 163 goto no_phy;
164 164
165 phydev = of_phy_connect(dev, phy_node, cvm_oct_adjust_link, 0, 165 phydev = of_phy_connect(dev, phy_node, cvm_oct_adjust_link, 0,
166 PHY_INTERFACE_MODE_GMII); 166 priv->phy_mode);
167 of_node_put(phy_node); 167 of_node_put(phy_node);
168 168
169 if (!phydev) 169 if (!phydev)
diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c
index ce61c5670ef6..986db76705cc 100644
--- a/drivers/staging/octeon/ethernet.c
+++ b/drivers/staging/octeon/ethernet.c
@@ -653,14 +653,37 @@ static struct device_node *cvm_oct_node_for_port(struct device_node *pip,
653 return np; 653 return np;
654} 654}
655 655
656static void cvm_set_rgmii_delay(struct device_node *np, int iface, int port) 656static void cvm_set_rgmii_delay(struct octeon_ethernet *priv, int iface,
657 int port)
657{ 658{
659 struct device_node *np = priv->of_node;
658 u32 delay_value; 660 u32 delay_value;
661 bool rx_delay;
662 bool tx_delay;
659 663
660 if (!of_property_read_u32(np, "rx-delay", &delay_value)) 664 /* By default, both RX/TX delay is enabled in
665 * __cvmx_helper_rgmii_enable().
666 */
667 rx_delay = true;
668 tx_delay = true;
669
670 if (!of_property_read_u32(np, "rx-delay", &delay_value)) {
661 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, iface), delay_value); 671 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, iface), delay_value);
662 if (!of_property_read_u32(np, "tx-delay", &delay_value)) 672 rx_delay = delay_value > 0;
673 }
674 if (!of_property_read_u32(np, "tx-delay", &delay_value)) {
663 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, iface), delay_value); 675 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, iface), delay_value);
676 tx_delay = delay_value > 0;
677 }
678
679 if (!rx_delay && !tx_delay)
680 priv->phy_mode = PHY_INTERFACE_MODE_RGMII_ID;
681 else if (!rx_delay)
682 priv->phy_mode = PHY_INTERFACE_MODE_RGMII_RXID;
683 else if (!tx_delay)
684 priv->phy_mode = PHY_INTERFACE_MODE_RGMII_TXID;
685 else
686 priv->phy_mode = PHY_INTERFACE_MODE_RGMII;
664} 687}
665 688
666static int cvm_oct_probe(struct platform_device *pdev) 689static int cvm_oct_probe(struct platform_device *pdev)
@@ -825,6 +848,7 @@ static int cvm_oct_probe(struct platform_device *pdev)
825 priv->port = port; 848 priv->port = port;
826 priv->queue = cvmx_pko_get_base_queue(priv->port); 849 priv->queue = cvmx_pko_get_base_queue(priv->port);
827 priv->fau = fau - cvmx_pko_get_num_queues(port) * 4; 850 priv->fau = fau - cvmx_pko_get_num_queues(port) * 4;
851 priv->phy_mode = PHY_INTERFACE_MODE_NA;
828 for (qos = 0; qos < 16; qos++) 852 for (qos = 0; qos < 16; qos++)
829 skb_queue_head_init(&priv->tx_free_list[qos]); 853 skb_queue_head_init(&priv->tx_free_list[qos]);
830 for (qos = 0; qos < cvmx_pko_get_num_queues(port); 854 for (qos = 0; qos < cvmx_pko_get_num_queues(port);
@@ -856,6 +880,7 @@ static int cvm_oct_probe(struct platform_device *pdev)
856 break; 880 break;
857 881
858 case CVMX_HELPER_INTERFACE_MODE_SGMII: 882 case CVMX_HELPER_INTERFACE_MODE_SGMII:
883 priv->phy_mode = PHY_INTERFACE_MODE_SGMII;
859 dev->netdev_ops = &cvm_oct_sgmii_netdev_ops; 884 dev->netdev_ops = &cvm_oct_sgmii_netdev_ops;
860 strcpy(dev->name, "eth%d"); 885 strcpy(dev->name, "eth%d");
861 break; 886 break;
@@ -865,11 +890,16 @@ static int cvm_oct_probe(struct platform_device *pdev)
865 strcpy(dev->name, "spi%d"); 890 strcpy(dev->name, "spi%d");
866 break; 891 break;
867 892
868 case CVMX_HELPER_INTERFACE_MODE_RGMII:
869 case CVMX_HELPER_INTERFACE_MODE_GMII: 893 case CVMX_HELPER_INTERFACE_MODE_GMII:
894 priv->phy_mode = PHY_INTERFACE_MODE_GMII;
895 dev->netdev_ops = &cvm_oct_rgmii_netdev_ops;
896 strcpy(dev->name, "eth%d");
897 break;
898
899 case CVMX_HELPER_INTERFACE_MODE_RGMII:
870 dev->netdev_ops = &cvm_oct_rgmii_netdev_ops; 900 dev->netdev_ops = &cvm_oct_rgmii_netdev_ops;
871 strcpy(dev->name, "eth%d"); 901 strcpy(dev->name, "eth%d");
872 cvm_set_rgmii_delay(priv->of_node, interface, 902 cvm_set_rgmii_delay(priv, interface,
873 port_index); 903 port_index);
874 break; 904 break;
875 } 905 }
diff --git a/drivers/staging/octeon/octeon-ethernet.h b/drivers/staging/octeon/octeon-ethernet.h
index 4a07e7f43d12..be570d33685a 100644
--- a/drivers/staging/octeon/octeon-ethernet.h
+++ b/drivers/staging/octeon/octeon-ethernet.h
@@ -12,7 +12,7 @@
12#define OCTEON_ETHERNET_H 12#define OCTEON_ETHERNET_H
13 13
14#include <linux/of.h> 14#include <linux/of.h>
15 15#include <linux/phy.h>
16#include <asm/octeon/cvmx-helper-board.h> 16#include <asm/octeon/cvmx-helper-board.h>
17 17
18/** 18/**
@@ -33,6 +33,8 @@ struct octeon_ethernet {
33 * cvmx_helper_interface_mode_t 33 * cvmx_helper_interface_mode_t
34 */ 34 */
35 int imode; 35 int imode;
36 /* PHY mode */
37 phy_interface_t phy_mode;
36 /* List of outstanding tx buffers per queue */ 38 /* List of outstanding tx buffers per queue */
37 struct sk_buff_head tx_free_list[16]; 39 struct sk_buff_head tx_free_list[16];
38 unsigned int last_speed; 40 unsigned int last_speed;
diff --git a/drivers/staging/olpc_dcon/olpc_dcon_xo_1.c b/drivers/staging/olpc_dcon/olpc_dcon_xo_1.c
index 80b8d4153414..a54286498a47 100644
--- a/drivers/staging/olpc_dcon/olpc_dcon_xo_1.c
+++ b/drivers/staging/olpc_dcon/olpc_dcon_xo_1.c
@@ -45,7 +45,7 @@ static int dcon_init_xo_1(struct dcon_priv *dcon)
45{ 45{
46 unsigned char lob; 46 unsigned char lob;
47 int ret, i; 47 int ret, i;
48 struct dcon_gpio *pin = &gpios_asis[0]; 48 const struct dcon_gpio *pin = &gpios_asis[0];
49 49
50 for (i = 0; i < ARRAY_SIZE(gpios_asis); i++) { 50 for (i = 0; i < ARRAY_SIZE(gpios_asis); i++) {
51 gpios[i] = devm_gpiod_get(&dcon->client->dev, pin[i].name, 51 gpios[i] = devm_gpiod_get(&dcon->client->dev, pin[i].name,
diff --git a/drivers/staging/rtl8188eu/core/rtw_xmit.c b/drivers/staging/rtl8188eu/core/rtw_xmit.c
index 1723a47a96b4..952f2ab51347 100644
--- a/drivers/staging/rtl8188eu/core/rtw_xmit.c
+++ b/drivers/staging/rtl8188eu/core/rtw_xmit.c
@@ -174,7 +174,9 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, struct adapter *padapter)
174 174
175 pxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf; 175 pxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf;
176 176
177 rtw_alloc_hwxmits(padapter); 177 res = rtw_alloc_hwxmits(padapter);
178 if (res == _FAIL)
179 goto exit;
178 rtw_init_hwxmits(pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry); 180 rtw_init_hwxmits(pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);
179 181
180 for (i = 0; i < 4; i++) 182 for (i = 0; i < 4; i++)
@@ -1503,7 +1505,7 @@ exit:
1503 return res; 1505 return res;
1504} 1506}
1505 1507
1506void rtw_alloc_hwxmits(struct adapter *padapter) 1508s32 rtw_alloc_hwxmits(struct adapter *padapter)
1507{ 1509{
1508 struct hw_xmit *hwxmits; 1510 struct hw_xmit *hwxmits;
1509 struct xmit_priv *pxmitpriv = &padapter->xmitpriv; 1511 struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
@@ -1512,6 +1514,8 @@ void rtw_alloc_hwxmits(struct adapter *padapter)
1512 1514
1513 pxmitpriv->hwxmits = kcalloc(pxmitpriv->hwxmit_entry, 1515 pxmitpriv->hwxmits = kcalloc(pxmitpriv->hwxmit_entry,
1514 sizeof(struct hw_xmit), GFP_KERNEL); 1516 sizeof(struct hw_xmit), GFP_KERNEL);
1517 if (!pxmitpriv->hwxmits)
1518 return _FAIL;
1515 1519
1516 hwxmits = pxmitpriv->hwxmits; 1520 hwxmits = pxmitpriv->hwxmits;
1517 1521
@@ -1519,6 +1523,7 @@ void rtw_alloc_hwxmits(struct adapter *padapter)
1519 hwxmits[1] .sta_queue = &pxmitpriv->vi_pending; 1523 hwxmits[1] .sta_queue = &pxmitpriv->vi_pending;
1520 hwxmits[2] .sta_queue = &pxmitpriv->be_pending; 1524 hwxmits[2] .sta_queue = &pxmitpriv->be_pending;
1521 hwxmits[3] .sta_queue = &pxmitpriv->bk_pending; 1525 hwxmits[3] .sta_queue = &pxmitpriv->bk_pending;
1526 return _SUCCESS;
1522} 1527}
1523 1528
1524void rtw_free_hwxmits(struct adapter *padapter) 1529void rtw_free_hwxmits(struct adapter *padapter)
diff --git a/drivers/staging/rtl8188eu/include/rtw_xmit.h b/drivers/staging/rtl8188eu/include/rtw_xmit.h
index 788f59c74ea1..ba7e15fbde72 100644
--- a/drivers/staging/rtl8188eu/include/rtw_xmit.h
+++ b/drivers/staging/rtl8188eu/include/rtw_xmit.h
@@ -336,7 +336,7 @@ s32 rtw_txframes_sta_ac_pending(struct adapter *padapter,
336void rtw_init_hwxmits(struct hw_xmit *phwxmit, int entry); 336void rtw_init_hwxmits(struct hw_xmit *phwxmit, int entry);
337s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, struct adapter *padapter); 337s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, struct adapter *padapter);
338void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv); 338void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv);
339void rtw_alloc_hwxmits(struct adapter *padapter); 339s32 rtw_alloc_hwxmits(struct adapter *padapter);
340void rtw_free_hwxmits(struct adapter *padapter); 340void rtw_free_hwxmits(struct adapter *padapter);
341s32 rtw_xmit(struct adapter *padapter, struct sk_buff **pkt); 341s32 rtw_xmit(struct adapter *padapter, struct sk_buff **pkt);
342 342
diff --git a/drivers/staging/rtl8712/rtl8712_cmd.c b/drivers/staging/rtl8712/rtl8712_cmd.c
index 1920d02f7c9f..8c36acedf507 100644
--- a/drivers/staging/rtl8712/rtl8712_cmd.c
+++ b/drivers/staging/rtl8712/rtl8712_cmd.c
@@ -147,17 +147,9 @@ static u8 write_macreg_hdl(struct _adapter *padapter, u8 *pbuf)
147 147
148static u8 read_bbreg_hdl(struct _adapter *padapter, u8 *pbuf) 148static u8 read_bbreg_hdl(struct _adapter *padapter, u8 *pbuf)
149{ 149{
150 u32 val;
151 void (*pcmd_callback)(struct _adapter *dev, struct cmd_obj *pcmd);
152 struct cmd_obj *pcmd = (struct cmd_obj *)pbuf; 150 struct cmd_obj *pcmd = (struct cmd_obj *)pbuf;
153 151
154 if (pcmd->rsp && pcmd->rspsz > 0) 152 r8712_free_cmd_obj(pcmd);
155 memcpy(pcmd->rsp, (u8 *)&val, pcmd->rspsz);
156 pcmd_callback = cmd_callback[pcmd->cmdcode].callback;
157 if (!pcmd_callback)
158 r8712_free_cmd_obj(pcmd);
159 else
160 pcmd_callback(padapter, pcmd);
161 return H2C_SUCCESS; 153 return H2C_SUCCESS;
162} 154}
163 155
diff --git a/drivers/staging/rtl8712/rtl8712_cmd.h b/drivers/staging/rtl8712/rtl8712_cmd.h
index 92fb77666d44..1ef86b8c592f 100644
--- a/drivers/staging/rtl8712/rtl8712_cmd.h
+++ b/drivers/staging/rtl8712/rtl8712_cmd.h
@@ -140,7 +140,7 @@ enum rtl8712_h2c_cmd {
140static struct _cmd_callback cmd_callback[] = { 140static struct _cmd_callback cmd_callback[] = {
141 {GEN_CMD_CODE(_Read_MACREG), NULL}, /*0*/ 141 {GEN_CMD_CODE(_Read_MACREG), NULL}, /*0*/
142 {GEN_CMD_CODE(_Write_MACREG), NULL}, 142 {GEN_CMD_CODE(_Write_MACREG), NULL},
143 {GEN_CMD_CODE(_Read_BBREG), &r8712_getbbrfreg_cmdrsp_callback}, 143 {GEN_CMD_CODE(_Read_BBREG), NULL},
144 {GEN_CMD_CODE(_Write_BBREG), NULL}, 144 {GEN_CMD_CODE(_Write_BBREG), NULL},
145 {GEN_CMD_CODE(_Read_RFREG), &r8712_getbbrfreg_cmdrsp_callback}, 145 {GEN_CMD_CODE(_Read_RFREG), &r8712_getbbrfreg_cmdrsp_callback},
146 {GEN_CMD_CODE(_Write_RFREG), NULL}, /*5*/ 146 {GEN_CMD_CODE(_Write_RFREG), NULL}, /*5*/
diff --git a/drivers/staging/rtl8723bs/core/rtw_xmit.c b/drivers/staging/rtl8723bs/core/rtw_xmit.c
index 094d61bcb469..b87f13a0b563 100644
--- a/drivers/staging/rtl8723bs/core/rtw_xmit.c
+++ b/drivers/staging/rtl8723bs/core/rtw_xmit.c
@@ -260,7 +260,9 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, struct adapter *padapter)
260 } 260 }
261 } 261 }
262 262
263 rtw_alloc_hwxmits(padapter); 263 res = rtw_alloc_hwxmits(padapter);
264 if (res == _FAIL)
265 goto exit;
264 rtw_init_hwxmits(pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry); 266 rtw_init_hwxmits(pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);
265 267
266 for (i = 0; i < 4; i++) { 268 for (i = 0; i < 4; i++) {
@@ -2144,7 +2146,7 @@ exit:
2144 return res; 2146 return res;
2145} 2147}
2146 2148
2147void rtw_alloc_hwxmits(struct adapter *padapter) 2149s32 rtw_alloc_hwxmits(struct adapter *padapter)
2148{ 2150{
2149 struct hw_xmit *hwxmits; 2151 struct hw_xmit *hwxmits;
2150 struct xmit_priv *pxmitpriv = &padapter->xmitpriv; 2152 struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
@@ -2155,10 +2157,8 @@ void rtw_alloc_hwxmits(struct adapter *padapter)
2155 2157
2156 pxmitpriv->hwxmits = rtw_zmalloc(sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry); 2158 pxmitpriv->hwxmits = rtw_zmalloc(sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry);
2157 2159
2158 if (pxmitpriv->hwxmits == NULL) { 2160 if (!pxmitpriv->hwxmits)
2159 DBG_871X("alloc hwxmits fail!...\n"); 2161 return _FAIL;
2160 return;
2161 }
2162 2162
2163 hwxmits = pxmitpriv->hwxmits; 2163 hwxmits = pxmitpriv->hwxmits;
2164 2164
@@ -2204,7 +2204,7 @@ void rtw_alloc_hwxmits(struct adapter *padapter)
2204 2204
2205 } 2205 }
2206 2206
2207 2207 return _SUCCESS;
2208} 2208}
2209 2209
2210void rtw_free_hwxmits(struct adapter *padapter) 2210void rtw_free_hwxmits(struct adapter *padapter)
diff --git a/drivers/staging/rtl8723bs/include/rtw_xmit.h b/drivers/staging/rtl8723bs/include/rtw_xmit.h
index 1b38b9182b31..37f42b2f22f1 100644
--- a/drivers/staging/rtl8723bs/include/rtw_xmit.h
+++ b/drivers/staging/rtl8723bs/include/rtw_xmit.h
@@ -487,7 +487,7 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, struct adapter *padapter);
487void _rtw_free_xmit_priv (struct xmit_priv *pxmitpriv); 487void _rtw_free_xmit_priv (struct xmit_priv *pxmitpriv);
488 488
489 489
490void rtw_alloc_hwxmits(struct adapter *padapter); 490s32 rtw_alloc_hwxmits(struct adapter *padapter);
491void rtw_free_hwxmits(struct adapter *padapter); 491void rtw_free_hwxmits(struct adapter *padapter);
492 492
493 493
diff --git a/drivers/staging/rtlwifi/phydm/rtl_phydm.c b/drivers/staging/rtlwifi/phydm/rtl_phydm.c
index 9930ed954abb..4cc77b2016e1 100644
--- a/drivers/staging/rtlwifi/phydm/rtl_phydm.c
+++ b/drivers/staging/rtlwifi/phydm/rtl_phydm.c
@@ -180,6 +180,8 @@ static int rtl_phydm_init_priv(struct rtl_priv *rtlpriv,
180 180
181 rtlpriv->phydm.internal = 181 rtlpriv->phydm.internal =
182 kzalloc(sizeof(struct phy_dm_struct), GFP_KERNEL); 182 kzalloc(sizeof(struct phy_dm_struct), GFP_KERNEL);
183 if (!rtlpriv->phydm.internal)
184 return 0;
183 185
184 _rtl_phydm_init_com_info(rtlpriv, ic, params); 186 _rtl_phydm_init_com_info(rtlpriv, ic, params);
185 187
diff --git a/drivers/staging/rtlwifi/rtl8822be/fw.c b/drivers/staging/rtlwifi/rtl8822be/fw.c
index f061dd1382aa..cf6b7a80b753 100644
--- a/drivers/staging/rtlwifi/rtl8822be/fw.c
+++ b/drivers/staging/rtlwifi/rtl8822be/fw.c
@@ -743,6 +743,8 @@ void rtl8822be_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
743 u1_rsvd_page_loc, 3); 743 u1_rsvd_page_loc, 3);
744 744
745 skb = dev_alloc_skb(totalpacketlen); 745 skb = dev_alloc_skb(totalpacketlen);
746 if (!skb)
747 return;
746 memcpy((u8 *)skb_put(skb, totalpacketlen), &reserved_page_packet, 748 memcpy((u8 *)skb_put(skb, totalpacketlen), &reserved_page_packet,
747 totalpacketlen); 749 totalpacketlen);
748 750
diff --git a/drivers/staging/speakup/speakup_soft.c b/drivers/staging/speakup/speakup_soft.c
index edff6ce85655..9d85a3a1af4c 100644
--- a/drivers/staging/speakup/speakup_soft.c
+++ b/drivers/staging/speakup/speakup_soft.c
@@ -210,12 +210,15 @@ static ssize_t softsynthx_read(struct file *fp, char __user *buf, size_t count,
210 return -EINVAL; 210 return -EINVAL;
211 211
212 spin_lock_irqsave(&speakup_info.spinlock, flags); 212 spin_lock_irqsave(&speakup_info.spinlock, flags);
213 synth_soft.alive = 1;
213 while (1) { 214 while (1) {
214 prepare_to_wait(&speakup_event, &wait, TASK_INTERRUPTIBLE); 215 prepare_to_wait(&speakup_event, &wait, TASK_INTERRUPTIBLE);
215 if (!unicode) 216 if (synth_current() == &synth_soft) {
216 synth_buffer_skip_nonlatin1(); 217 if (!unicode)
217 if (!synth_buffer_empty() || speakup_info.flushing) 218 synth_buffer_skip_nonlatin1();
218 break; 219 if (!synth_buffer_empty() || speakup_info.flushing)
220 break;
221 }
219 spin_unlock_irqrestore(&speakup_info.spinlock, flags); 222 spin_unlock_irqrestore(&speakup_info.spinlock, flags);
220 if (fp->f_flags & O_NONBLOCK) { 223 if (fp->f_flags & O_NONBLOCK) {
221 finish_wait(&speakup_event, &wait); 224 finish_wait(&speakup_event, &wait);
@@ -235,6 +238,8 @@ static ssize_t softsynthx_read(struct file *fp, char __user *buf, size_t count,
235 238
236 /* Keep 3 bytes available for a 16bit UTF-8-encoded character */ 239 /* Keep 3 bytes available for a 16bit UTF-8-encoded character */
237 while (chars_sent <= count - bytes_per_ch) { 240 while (chars_sent <= count - bytes_per_ch) {
241 if (synth_current() != &synth_soft)
242 break;
238 if (speakup_info.flushing) { 243 if (speakup_info.flushing) {
239 speakup_info.flushing = 0; 244 speakup_info.flushing = 0;
240 ch = '\x18'; 245 ch = '\x18';
@@ -331,7 +336,8 @@ static __poll_t softsynth_poll(struct file *fp, struct poll_table_struct *wait)
331 poll_wait(fp, &speakup_event, wait); 336 poll_wait(fp, &speakup_event, wait);
332 337
333 spin_lock_irqsave(&speakup_info.spinlock, flags); 338 spin_lock_irqsave(&speakup_info.spinlock, flags);
334 if (!synth_buffer_empty() || speakup_info.flushing) 339 if (synth_current() == &synth_soft &&
340 (!synth_buffer_empty() || speakup_info.flushing))
335 ret = EPOLLIN | EPOLLRDNORM; 341 ret = EPOLLIN | EPOLLRDNORM;
336 spin_unlock_irqrestore(&speakup_info.spinlock, flags); 342 spin_unlock_irqrestore(&speakup_info.spinlock, flags);
337 return ret; 343 return ret;
diff --git a/drivers/staging/speakup/spk_priv.h b/drivers/staging/speakup/spk_priv.h
index c8e688878fc7..ac6a74883af4 100644
--- a/drivers/staging/speakup/spk_priv.h
+++ b/drivers/staging/speakup/spk_priv.h
@@ -74,6 +74,7 @@ int synth_request_region(unsigned long start, unsigned long n);
74int synth_release_region(unsigned long start, unsigned long n); 74int synth_release_region(unsigned long start, unsigned long n);
75int synth_add(struct spk_synth *in_synth); 75int synth_add(struct spk_synth *in_synth);
76void synth_remove(struct spk_synth *in_synth); 76void synth_remove(struct spk_synth *in_synth);
77struct spk_synth *synth_current(void);
77 78
78extern struct speakup_info_t speakup_info; 79extern struct speakup_info_t speakup_info;
79 80
diff --git a/drivers/staging/speakup/synth.c b/drivers/staging/speakup/synth.c
index 25f259ee4ffc..3568bfb89912 100644
--- a/drivers/staging/speakup/synth.c
+++ b/drivers/staging/speakup/synth.c
@@ -481,4 +481,10 @@ void synth_remove(struct spk_synth *in_synth)
481} 481}
482EXPORT_SYMBOL_GPL(synth_remove); 482EXPORT_SYMBOL_GPL(synth_remove);
483 483
484struct spk_synth *synth_current(void)
485{
486 return synth;
487}
488EXPORT_SYMBOL_GPL(synth_current);
489
484short spk_punc_masks[] = { 0, SOME, MOST, PUNC, PUNC | B_SYM }; 490short spk_punc_masks[] = { 0, SOME, MOST, PUNC, PUNC | B_SYM };
diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
index 804daf83be35..064d0db4c51e 100644
--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
@@ -3513,6 +3513,7 @@ static int vchiq_probe(struct platform_device *pdev)
3513 struct device_node *fw_node; 3513 struct device_node *fw_node;
3514 const struct of_device_id *of_id; 3514 const struct of_device_id *of_id;
3515 struct vchiq_drvdata *drvdata; 3515 struct vchiq_drvdata *drvdata;
3516 struct device *vchiq_dev;
3516 int err; 3517 int err;
3517 3518
3518 of_id = of_match_node(vchiq_of_match, pdev->dev.of_node); 3519 of_id = of_match_node(vchiq_of_match, pdev->dev.of_node);
@@ -3547,9 +3548,12 @@ static int vchiq_probe(struct platform_device *pdev)
3547 goto failed_platform_init; 3548 goto failed_platform_init;
3548 } 3549 }
3549 3550
3550 if (IS_ERR(device_create(vchiq_class, &pdev->dev, vchiq_devid, 3551 vchiq_dev = device_create(vchiq_class, &pdev->dev, vchiq_devid, NULL,
3551 NULL, "vchiq"))) 3552 "vchiq");
3553 if (IS_ERR(vchiq_dev)) {
3554 err = PTR_ERR(vchiq_dev);
3552 goto failed_device_create; 3555 goto failed_device_create;
3556 }
3553 3557
3554 vchiq_debugfs_init(); 3558 vchiq_debugfs_init();
3555 3559
diff --git a/drivers/staging/vt6655/device_main.c b/drivers/staging/vt6655/device_main.c
index b370985b58a1..c6bb4aaf9bd0 100644
--- a/drivers/staging/vt6655/device_main.c
+++ b/drivers/staging/vt6655/device_main.c
@@ -1033,8 +1033,6 @@ static void vnt_interrupt_process(struct vnt_private *priv)
1033 return; 1033 return;
1034 } 1034 }
1035 1035
1036 MACvIntDisable(priv->PortOffset);
1037
1038 spin_lock_irqsave(&priv->lock, flags); 1036 spin_lock_irqsave(&priv->lock, flags);
1039 1037
1040 /* Read low level stats */ 1038 /* Read low level stats */
@@ -1122,8 +1120,6 @@ static void vnt_interrupt_process(struct vnt_private *priv)
1122 } 1120 }
1123 1121
1124 spin_unlock_irqrestore(&priv->lock, flags); 1122 spin_unlock_irqrestore(&priv->lock, flags);
1125
1126 MACvIntEnable(priv->PortOffset, IMR_MASK_VALUE);
1127} 1123}
1128 1124
1129static void vnt_interrupt_work(struct work_struct *work) 1125static void vnt_interrupt_work(struct work_struct *work)
@@ -1133,14 +1129,17 @@ static void vnt_interrupt_work(struct work_struct *work)
1133 1129
1134 if (priv->vif) 1130 if (priv->vif)
1135 vnt_interrupt_process(priv); 1131 vnt_interrupt_process(priv);
1132
1133 MACvIntEnable(priv->PortOffset, IMR_MASK_VALUE);
1136} 1134}
1137 1135
1138static irqreturn_t vnt_interrupt(int irq, void *arg) 1136static irqreturn_t vnt_interrupt(int irq, void *arg)
1139{ 1137{
1140 struct vnt_private *priv = arg; 1138 struct vnt_private *priv = arg;
1141 1139
1142 if (priv->vif) 1140 schedule_work(&priv->interrupt_work);
1143 schedule_work(&priv->interrupt_work); 1141
1142 MACvIntDisable(priv->PortOffset);
1144 1143
1145 return IRQ_HANDLED; 1144 return IRQ_HANDLED;
1146} 1145}
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-25 23:27:40 -0500