11 files changed, 221 insertions, 231 deletions

diff --git a/drivers/net/ethernet/intel/fm10k/fm10k_pci.c b/drivers/net/ethernet/intel/fm10k/fm10k_pci.c
index a434fecfdfeb..aa05fb534942 100644
--- a/drivers/net/ethernet/intel/fm10k/fm10k_pci.c
+++ b/drivers/net/ethernet/intel/fm10k/fm10k_pci.c
@@ -2120,91 +2120,6 @@ static int fm10k_sw_init(struct fm10k_intfc *interface,
         return 0;
 }
 
-static void fm10k_slot_warn(struct fm10k_intfc *interface)
-{
-        enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
-        enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
-        struct fm10k_hw *hw = &interface->hw;
-        int max_gts = 0, expected_gts = 0;
-
-        if (pcie_get_minimum_link(interface->pdev, &speed, &width) ||
-            speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
-                dev_warn(&interface->pdev->dev,
-                         "Unable to determine PCI Express bandwidth.\n");
-                return;
-        }
-
-        switch (speed) {
-        case PCIE_SPEED_2_5GT:
-                /* 8b/10b encoding reduces max throughput by 20% */
-                max_gts = 2 * width;
-                break;
-        case PCIE_SPEED_5_0GT:
-                /* 8b/10b encoding reduces max throughput by 20% */
-                max_gts = 4 * width;
-                break;
-        case PCIE_SPEED_8_0GT:
-                /* 128b/130b encoding has less than 2% impact on throughput */
-                max_gts = 8 * width;
-                break;
-        default:
-                dev_warn(&interface->pdev->dev,
-                         "Unable to determine PCI Express bandwidth.\n");
-                return;
-        }
-
-        dev_info(&interface->pdev->dev,
-                 "PCI Express bandwidth of %dGT/s available\n",
-                 max_gts);
-        dev_info(&interface->pdev->dev,
-                 "(Speed:%s, Width: x%d, Encoding Loss:%s, Payload:%s)\n",
-                 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
-                  speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
-                  speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
-                  "Unknown"),
-                 hw->bus.width,
-                 (speed == PCIE_SPEED_2_5GT ? "20%" :
-                  speed == PCIE_SPEED_5_0GT ? "20%" :
-                  speed == PCIE_SPEED_8_0GT ? "<2%" :
-                  "Unknown"),
-                 (hw->bus.payload == fm10k_bus_payload_128 ? "128B" :
-                  hw->bus.payload == fm10k_bus_payload_256 ? "256B" :
-                  hw->bus.payload == fm10k_bus_payload_512 ? "512B" :
-                  "Unknown"));
-
-        switch (hw->bus_caps.speed) {
-        case fm10k_bus_speed_2500:
-                /* 8b/10b encoding reduces max throughput by 20% */
-                expected_gts = 2 * hw->bus_caps.width;
-                break;
-        case fm10k_bus_speed_5000:
-                /* 8b/10b encoding reduces max throughput by 20% */
-                expected_gts = 4 * hw->bus_caps.width;
-                break;
-        case fm10k_bus_speed_8000:
-                /* 128b/130b encoding has less than 2% impact on throughput */
-                expected_gts = 8 * hw->bus_caps.width;
-                break;
-        default:
-                dev_warn(&interface->pdev->dev,
-                         "Unable to determine expected PCI Express bandwidth.\n");
-                return;
-        }
-
-        if (max_gts >= expected_gts)
-                return;
-
-        dev_warn(&interface->pdev->dev,
-                 "This device requires %dGT/s of bandwidth for optimal performance.\n",
-                 expected_gts);
-        dev_warn(&interface->pdev->dev,
-                 "A %sslot with x%d lanes is suggested.\n",
-                 (hw->bus_caps.speed == fm10k_bus_speed_2500 ? "2.5GT/s " :
-                  hw->bus_caps.speed == fm10k_bus_speed_5000 ? "5.0GT/s " :
-                  hw->bus_caps.speed == fm10k_bus_speed_8000 ? "8.0GT/s " : ""),
-                 hw->bus_caps.width);
-}
-
 /**
  * fm10k_probe - Device Initialization Routine
  * @pdev: PCI device information struct
@@ -2326,7 +2241,7 @@ static int fm10k_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
         mod_timer(&interface->service_timer, (HZ * 2) + jiffies);
 
         /* print warning for non-optimal configurations */
-        fm10k_slot_warn(interface);
+        pcie_print_link_status(interface->pdev);
 
         /* report MAC address for logging */
         dev_info(&pdev->dev, "%pM\n", netdev->dev_addr);
diff --git a/drivers/net/ethernet/mellanox/mlx4/main.c b/drivers/net/ethernet/mellanox/mlx4/main.c
index 4d84cab77105..30cacac54e69 100644
--- a/drivers/net/ethernet/mellanox/mlx4/main.c
+++ b/drivers/net/ethernet/mellanox/mlx4/main.c
@@ -623,85 +623,6 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
         return 0;
 }
 
-static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
-                                       enum pci_bus_speed *speed,
-                                       enum pcie_link_width *width)
-{
-        u32 lnkcap1, lnkcap2;
-        int err1, err2;
-
-#define  PCIE_MLW_CAP_SHIFT 4   /* start of MLW mask in link capabilities */
-
-        *speed = PCI_SPEED_UNKNOWN;
-        *width = PCIE_LNK_WIDTH_UNKNOWN;
-
-        err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
-                                          &lnkcap1);
-        err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
-                                          &lnkcap2);
-        if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
-                if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
-                        *speed = PCIE_SPEED_8_0GT;
-                else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
-                        *speed = PCIE_SPEED_5_0GT;
-                else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
-                        *speed = PCIE_SPEED_2_5GT;
-        }
-        if (!err1) {
-                *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
-                if (!lnkcap2) { /* pre-r3.0 */
-                        if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
-                                *speed = PCIE_SPEED_5_0GT;
-                        else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
-                                *speed = PCIE_SPEED_2_5GT;
-                }
-        }
-
-        if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
-                return err1 ? err1 :
-                        err2 ? err2 : -EINVAL;
-        }
-        return 0;
-}
-
-static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
-{
-        enum pcie_link_width width, width_cap;
-        enum pci_bus_speed speed, speed_cap;
-        int err;
-
-#define PCIE_SPEED_STR(speed) \
-        (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
-         speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
-         speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
-         "Unknown")
-
-        err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
-        if (err) {
-                mlx4_warn(dev,
-                          "Unable to determine PCIe device BW capabilities\n");
-                return;
-        }
-
-        err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
-        if (err || speed == PCI_SPEED_UNKNOWN ||
-            width == PCIE_LNK_WIDTH_UNKNOWN) {
-                mlx4_warn(dev,
-                          "Unable to determine PCI device chain minimum BW\n");
-                return;
-        }
-
-        if (width != width_cap || speed != speed_cap)
-                mlx4_warn(dev,
-                          "PCIe BW is different than device's capability\n");
-
-        mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
-                  PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
-        mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
-                  width, width_cap);
-        return;
-}
-
 /*The function checks if there are live vf, return the num of them*/
 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
 {
@@ -3475,7 +3396,7 @@ slave_start:
          * express device capabilities are under-satisfied by the bus.
          */
         if (!mlx4_is_slave(dev))
-                mlx4_check_pcie_caps(dev);
+                pcie_print_link_status(dev->persist->pdev);
 
         /* In master functions, the communication channel must be initialized
          * after obtaining its address from fw */
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
index 47bab842c5ee..93291ec4a3d1 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
@@ -3864,36 +3864,6 @@ void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
                 indirection_rqt[i] = i % num_channels;
 }
 
-static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
-{
-        enum pcie_link_width width;
-        enum pci_bus_speed speed;
-        int err = 0;
-
-        err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
-        if (err)
-                return err;
-
-        if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
-                return -EINVAL;
-
-        switch (speed) {
-        case PCIE_SPEED_2_5GT:
-                *pci_bw = 2500 * width;
-                break;
-        case PCIE_SPEED_5_0GT:
-                *pci_bw = 5000 * width;
-                break;
-        case PCIE_SPEED_8_0GT:
-                *pci_bw = 8000 * width;
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
 {
         return (link_speed && pci_bw &&
@@ -3979,7 +3949,7 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
         params->num_tc       = 1;
 
         mlx5e_get_max_linkspeed(mdev, &link_speed);
-        mlx5e_get_pci_bw(mdev, &pci_bw);
+        pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
         mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
                       link_speed, pci_bw);
 
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c
index 2ef641c91c26..622f02d34aae 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c
@@ -1043,6 +1043,10 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
         dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
                  fw_rev_min(dev), fw_rev_sub(dev));
 
+        /* Only PFs hold the relevant PCIe information for this query */
+        if (mlx5_core_is_pf(dev))
+                pcie_print_link_status(dev->pdev);
+
         /* on load removing any previous indication of internal error, device is
          * up
          */
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index eb6bee8724cc..63d0952684fb 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -158,45 +158,18 @@ static DEVICE_ATTR_RO(resource);
 static ssize_t max_link_speed_show(struct device *dev,
                                    struct device_attribute *attr, char *buf)
 {
-        struct pci_dev *pci_dev = to_pci_dev(dev);
-        u32 linkcap;
-        int err;
-        const char *speed;
-
-        err = pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &linkcap);
-        if (err)
-                return -EINVAL;
-
-        switch (linkcap & PCI_EXP_LNKCAP_SLS) {
-        case PCI_EXP_LNKCAP_SLS_8_0GB:
-                speed = "8 GT/s";
-                break;
-        case PCI_EXP_LNKCAP_SLS_5_0GB:
-                speed = "5 GT/s";
-                break;
-        case PCI_EXP_LNKCAP_SLS_2_5GB:
-                speed = "2.5 GT/s";
-                break;
-        default:
-                speed = "Unknown speed";
-        }
+        struct pci_dev *pdev = to_pci_dev(dev);
 
-        return sprintf(buf, "%s\n", speed);
+        return sprintf(buf, "%s\n", PCIE_SPEED2STR(pcie_get_speed_cap(pdev)));
 }
 static DEVICE_ATTR_RO(max_link_speed);
 
 static ssize_t max_link_width_show(struct device *dev,
                                    struct device_attribute *attr, char *buf)
 {
-        struct pci_dev *pci_dev = to_pci_dev(dev);
-        u32 linkcap;
-        int err;
-
-        err = pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &linkcap);
-        if (err)
-                return -EINVAL;
+        struct pci_dev *pdev = to_pci_dev(dev);
 
-        return sprintf(buf, "%u\n", (linkcap & PCI_EXP_LNKCAP_MLW) >> 4);
+        return sprintf(buf, "%u\n", pcie_get_width_cap(pdev));
 }
 static DEVICE_ATTR_RO(max_link_width);
 
@@ -213,6 +186,9 @@ static ssize_t current_link_speed_show(struct device *dev,
                 return -EINVAL;
 
         switch (linkstat & PCI_EXP_LNKSTA_CLS) {
+        case PCI_EXP_LNKSTA_CLS_16_0GB:
+                speed = "16 GT/s";
+                break;
         case PCI_EXP_LNKSTA_CLS_8_0GB:
                 speed = "8 GT/s";
                 break;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index f6a4dd10d9b0..e7a3917ed389 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5147,6 +5147,180 @@ int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
 EXPORT_SYMBOL(pcie_get_minimum_link);
 
 /**
+ * pcie_bandwidth_available - determine minimum link settings of a PCIe
+ *                            device and its bandwidth limitation
+ * @dev: PCI device to query
+ * @limiting_dev: storage for device causing the bandwidth limitation
+ * @speed: storage for speed of limiting device
+ * @width: storage for width of limiting device
+ *
+ * Walk up the PCI device chain and find the point where the minimum
+ * bandwidth is available.  Return the bandwidth available there and (if
+ * limiting_dev, speed, and width pointers are supplied) information about
+ * that point.  The bandwidth returned is in Mb/s, i.e., megabits/second of
+ * raw bandwidth.
+ */
+u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
+                             enum pci_bus_speed *speed,
+                             enum pcie_link_width *width)
+{
+        u16 lnksta;
+        enum pci_bus_speed next_speed;
+        enum pcie_link_width next_width;
+        u32 bw, next_bw;
+
+        if (speed)
+                *speed = PCI_SPEED_UNKNOWN;
+        if (width)
+                *width = PCIE_LNK_WIDTH_UNKNOWN;
+
+        bw = 0;
+
+        while (dev) {
+                pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
+
+                next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
+                next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
+                        PCI_EXP_LNKSTA_NLW_SHIFT;
+
+                next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
+
+                /* Check if current device limits the total bandwidth */
+                if (!bw || next_bw <= bw) {
+                        bw = next_bw;
+
+                        if (limiting_dev)
+                                *limiting_dev = dev;
+                        if (speed)
+                                *speed = next_speed;
+                        if (width)
+                                *width = next_width;
+                }
+
+                dev = pci_upstream_bridge(dev);
+        }
+
+        return bw;
+}
+EXPORT_SYMBOL(pcie_bandwidth_available);
+
+/**
+ * pcie_get_speed_cap - query for the PCI device's link speed capability
+ * @dev: PCI device to query
+ *
+ * Query the PCI device speed capability.  Return the maximum link speed
+ * supported by the device.
+ */
+enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
+{
+        u32 lnkcap2, lnkcap;
+
+        /*
+         * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link
+         * Speeds Vector in Link Capabilities 2 when supported, falling
+         * back to Max Link Speed in Link Capabilities otherwise.
+         */
+        pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
+        if (lnkcap2) { /* PCIe r3.0-compliant */
+                if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
+                        return PCIE_SPEED_16_0GT;
+                else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
+                        return PCIE_SPEED_8_0GT;
+                else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
+                        return PCIE_SPEED_5_0GT;
+                else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
+                        return PCIE_SPEED_2_5GT;
+                return PCI_SPEED_UNKNOWN;
+        }
+
+        pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
+        if (lnkcap) {
+                if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
+                        return PCIE_SPEED_16_0GT;
+                else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
+                        return PCIE_SPEED_8_0GT;
+                else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
+                        return PCIE_SPEED_5_0GT;
+                else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
+                        return PCIE_SPEED_2_5GT;
+        }
+
+        return PCI_SPEED_UNKNOWN;
+}
+
+/**
+ * pcie_get_width_cap - query for the PCI device's link width capability
+ * @dev: PCI device to query
+ *
+ * Query the PCI device width capability.  Return the maximum link width
+ * supported by the device.
+ */
+enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
+{
+        u32 lnkcap;
+
+        pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
+        if (lnkcap)
+                return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
+
+        return PCIE_LNK_WIDTH_UNKNOWN;
+}
+
+/**
+ * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
+ * @dev: PCI device
+ * @speed: storage for link speed
+ * @width: storage for link width
+ *
+ * Calculate a PCI device's link bandwidth by querying for its link speed
+ * and width, multiplying them, and applying encoding overhead.  The result
+ * is in Mb/s, i.e., megabits/second of raw bandwidth.
+ */
+u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
+                           enum pcie_link_width *width)
+{
+        *speed = pcie_get_speed_cap(dev);
+        *width = pcie_get_width_cap(dev);
+
+        if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
+                return 0;
+
+        return *width * PCIE_SPEED2MBS_ENC(*speed);
+}
+
+/**
+ * pcie_print_link_status - Report the PCI device's link speed and width
+ * @dev: PCI device to query
+ *
+ * Report the available bandwidth at the device.  If this is less than the
+ * device is capable of, report the device's maximum possible bandwidth and
+ * the upstream link that limits its performance to less than that.
+ */
+void pcie_print_link_status(struct pci_dev *dev)
+{
+        enum pcie_link_width width, width_cap;
+        enum pci_bus_speed speed, speed_cap;
+        struct pci_dev *limiting_dev = NULL;
+        u32 bw_avail, bw_cap;
+
+        bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
+        bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
+
+        if (bw_avail >= bw_cap)
+                pci_info(dev, "%u.%03u Gb/s available bandwidth (%s x%d link)\n",
+                         bw_cap / 1000, bw_cap % 1000,
+                         PCIE_SPEED2STR(speed_cap), width_cap);
+        else
+                pci_info(dev, "%u.%03u Gb/s available bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
+                         bw_avail / 1000, bw_avail % 1000,
+                         PCIE_SPEED2STR(speed), width,
+                         limiting_dev ? pci_name(limiting_dev) : "<unknown>",
+                         bw_cap / 1000, bw_cap % 1000,
+                         PCIE_SPEED2STR(speed_cap), width_cap);
+}
+EXPORT_SYMBOL(pcie_print_link_status);
+
+/**
  * pci_select_bars - Make BAR mask from the type of resource
  * @dev: the PCI device for which BAR mask is made
  * @flags: resource type mask to be selected
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index fcd81911b127..ce9adec6c66e 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -253,6 +253,27 @@ bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
 void pci_disable_bridge_window(struct pci_dev *dev);
 
+/* PCIe link information */
+#define PCIE_SPEED2STR(speed) \
+        ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
+         (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
+         (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
+         (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
+         "Unknown speed")
+
+/* PCIe speed to Mb/s reduced by encoding overhead */
+#define PCIE_SPEED2MBS_ENC(speed) \
+        ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
+         (speed) == PCIE_SPEED_8_0GT  ?  8000*128/130 : \
+         (speed) == PCIE_SPEED_5_0GT  ?  5000*8/10 : \
+         (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
+         0)
+
+enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
+enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
+u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
+                           enum pcie_link_width *width);
+
 /* Single Root I/O Virtualization */
 struct pci_sriov {
         int             pos;            /* Capability position */
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ef5377438a1e..86bf045f3d59 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -592,7 +592,7 @@ const unsigned char pcie_link_speed[] = {
         PCIE_SPEED_2_5GT,               /* 1 */
         PCIE_SPEED_5_0GT,               /* 2 */
         PCIE_SPEED_8_0GT,               /* 3 */
-        PCI_SPEED_UNKNOWN,              /* 4 */
+        PCIE_SPEED_16_0GT,              /* 4 */
         PCI_SPEED_UNKNOWN,              /* 5 */
         PCI_SPEED_UNKNOWN,              /* 6 */
         PCI_SPEED_UNKNOWN,              /* 7 */
diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c
index d10f556dc03e..191893e19d5c 100644
--- a/drivers/pci/slot.c
+++ b/drivers/pci/slot.c
@@ -76,6 +76,7 @@ static const char *pci_bus_speed_strings[] = {
         "2.5 GT/s PCIe",        /* 0x14 */
         "5.0 GT/s PCIe",        /* 0x15 */
         "8.0 GT/s PCIe",        /* 0x16 */
+        "16.0 GT/s PCIe",       /* 0x17 */
 };
 
 static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 24e15510a946..926a8cb5d6d4 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -256,6 +256,7 @@ enum pci_bus_speed {
         PCIE_SPEED_2_5GT                = 0x14,
         PCIE_SPEED_5_0GT                = 0x15,
         PCIE_SPEED_8_0GT                = 0x16,
+        PCIE_SPEED_16_0GT               = 0x17,
         PCI_SPEED_UNKNOWN               = 0xff,
 };
 
@@ -1077,6 +1078,10 @@ int pcie_get_mps(struct pci_dev *dev);
 int pcie_set_mps(struct pci_dev *dev, int mps);
 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
                           enum pcie_link_width *width);
+u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
+                             enum pci_bus_speed *speed,
+                             enum pcie_link_width *width);
+void pcie_print_link_status(struct pci_dev *dev);
 void pcie_flr(struct pci_dev *dev);
 int __pci_reset_function_locked(struct pci_dev *dev);
 int pci_reset_function(struct pci_dev *dev);
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 0c79eac5e9b8..103ba797a8f3 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -520,6 +520,7 @@
 #define  PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
 #define  PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
 #define  PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
+#define  PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
 #define  PCI_EXP_LNKCAP_MLW     0x000003f0 /* Maximum Link Width */
 #define  PCI_EXP_LNKCAP_ASPMS   0x00000c00 /* ASPM Support */
 #define  PCI_EXP_LNKCAP_L0SEL   0x00007000 /* L0s Exit Latency */
@@ -547,6 +548,7 @@
 #define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
 #define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
 #define  PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
+#define  PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */
 #define  PCI_EXP_LNKSTA_NLW     0x03f0  /* Negotiated Link Width */
 #define  PCI_EXP_LNKSTA_NLW_X1  0x0010  /* Current Link Width x1 */
 #define  PCI_EXP_LNKSTA_NLW_X2  0x0020  /* Current Link Width x2 */
@@ -648,8 +650,9 @@
 #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2       44      /* v2 endpoints without link end here */
 #define PCI_EXP_LNKCAP2         44      /* Link Capabilities 2 */
 #define  PCI_EXP_LNKCAP2_SLS_2_5GB      0x00000002 /* Supported Speed 2.5GT/s */
-#define  PCI_EXP_LNKCAP2_SLS_5_0GB      0x00000004 /* Supported Speed 5.0GT/s */
-#define  PCI_EXP_LNKCAP2_SLS_8_0GB      0x00000008 /* Supported Speed 8.0GT/s */
+#define  PCI_EXP_LNKCAP2_SLS_5_0GB      0x00000004 /* Supported Speed 5GT/s */
+#define  PCI_EXP_LNKCAP2_SLS_8_0GB      0x00000008 /* Supported Speed 8GT/s */
+#define  PCI_EXP_LNKCAP2_SLS_16_0GB     0x00000010 /* Supported Speed 16GT/s */
 #define  PCI_EXP_LNKCAP2_CROSSLINK      0x00000100 /* Crosslink supported */
 #define PCI_EXP_LNKCTL2         48      /* Link Control 2 */
 #define PCI_EXP_LNKSTA2         50      /* Link Status 2 */