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-rw-r--r--drivers/pinctrl/Kconfig9
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/pinctrl-lpc18xx.c1144
3 files changed, 1154 insertions, 0 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index aeb5729fbda6..53ae816f494e 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -88,6 +88,15 @@ config PINCTRL_LANTIQ
88 select PINMUX 88 select PINMUX
89 select PINCONF 89 select PINCONF
90 90
91config PINCTRL_LPC18XX
92 bool "NXP LPC18XX/43XX SCU pinctrl driver"
93 depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
94 default ARCH_LPC18XX
95 select PINMUX
96 select GENERIC_PINCONF
97 help
98 Pinctrl driver for NXP LPC18xx/43xx System Control Unit (SCU).
99
91config PINCTRL_FALCON 100config PINCTRL_FALCON
92 bool 101 bool
93 depends on SOC_FALCON 102 depends on SOC_FALCON
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 6eadf04a33b3..6a7b4baa8c94 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
34obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o 34obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
35obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o 35obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
36obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o 36obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
37obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o
37obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o 38obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
38obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o 39obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
39obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o 40obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c
new file mode 100644
index 000000000000..15fe1e2535c2
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-lpc18xx.c
@@ -0,0 +1,1144 @@
1/*
2 * Pinctrl driver for NXP LPC18xx/LPC43xx System Control Unit (SCU)
3 *
4 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/bitops.h>
12#include <linux/clk.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19#include <linux/pinctrl/pinconf-generic.h>
20
21#include "core.h"
22#include "pinctrl-utils.h"
23
24/* LPC18XX SCU analog function registers */
25#define LPC18XX_SCU_REG_ENAIO0 0xc88
26#define LPC18XX_SCU_REG_ENAIO1 0xc8c
27#define LPC18XX_SCU_REG_ENAIO2 0xc90
28#define LPC18XX_SCU_REG_ENAIO2_DAC BIT(0)
29
30/* LPC18XX SCU pin register definitions */
31#define LPC18XX_SCU_PIN_MODE_MASK 0x7
32#define LPC18XX_SCU_PIN_EPD BIT(3)
33#define LPC18XX_SCU_PIN_EPUN BIT(4)
34#define LPC18XX_SCU_PIN_EHS BIT(5)
35#define LPC18XX_SCU_PIN_EZI BIT(6)
36#define LPC18XX_SCU_PIN_ZIF BIT(7)
37#define LPC18XX_SCU_PIN_EHD_MASK 0x300
38#define LPC18XX_SCU_PIN_EHD_POS 8
39
40#define LPC18XX_SCU_I2C0_EFP BIT(0)
41#define LPC18XX_SCU_I2C0_EHD BIT(2)
42#define LPC18XX_SCU_I2C0_EZI BIT(3)
43#define LPC18XX_SCU_I2C0_ZIF BIT(7)
44#define LPC18XX_SCU_I2C0_SCL_SHIFT 0
45#define LPC18XX_SCU_I2C0_SDA_SHIFT 8
46
47#define LPC18XX_SCU_FUNC_PER_PIN 8
48
49struct lpc18xx_scu_data {
50 struct pinctrl_dev *pctl;
51 void __iomem *base;
52 struct clk *clk;
53};
54
55/* LPC18xx pin types */
56enum {
57 TYPE_ND, /* Normal-drive */
58 TYPE_HD, /* High-drive */
59 TYPE_HS, /* High-speed */
60 TYPE_I2C0,
61 TYPE_USB1,
62};
63
64/* LPC18xx pin functions */
65enum {
66 FUNC_R, /* Reserved */
67 FUNC_ADC,
68 FUNC_ADCTRIG,
69 FUNC_CAN0,
70 FUNC_CAN1,
71 FUNC_CGU_OUT,
72 FUNC_CLKIN,
73 FUNC_CLKOUT,
74 FUNC_CTIN,
75 FUNC_CTOUT,
76 FUNC_DAC,
77 FUNC_EMC,
78 FUNC_EMC_ALT,
79 FUNC_ENET,
80 FUNC_ENET_ALT,
81 FUNC_GPIO,
82 FUNC_I2C0,
83 FUNC_I2C1,
84 FUNC_I2S0_RX_MCLK,
85 FUNC_I2S0_RX_SCK,
86 FUNC_I2S0_RX_SDA,
87 FUNC_I2S0_RX_WS,
88 FUNC_I2S0_TX_MCLK,
89 FUNC_I2S0_TX_SCK,
90 FUNC_I2S0_TX_SDA,
91 FUNC_I2S0_TX_WS,
92 FUNC_I2S1,
93 FUNC_LCD,
94 FUNC_LCD_ALT,
95 FUNC_MCTRL,
96 FUNC_NMI,
97 FUNC_QEI,
98 FUNC_SDMMC,
99 FUNC_SGPIO,
100 FUNC_SPI,
101 FUNC_SPIFI,
102 FUNC_SSP0,
103 FUNC_SSP0_ALT,
104 FUNC_SSP1,
105 FUNC_TIMER0,
106 FUNC_TIMER1,
107 FUNC_TIMER2,
108 FUNC_TIMER3,
109 FUNC_TRACE,
110 FUNC_UART0,
111 FUNC_UART1,
112 FUNC_UART2,
113 FUNC_UART3,
114 FUNC_USB0,
115 FUNC_USB1,
116};
117
118static const char *const lpc18xx_function_names[] = {
119 [FUNC_R] = "",
120 [FUNC_ADC] = "adc",
121 [FUNC_ADCTRIG] = "adctrig",
122 [FUNC_CAN0] = "can0",
123 [FUNC_CAN1] = "can1",
124 [FUNC_CGU_OUT] = "cgu_out",
125 [FUNC_CLKIN] = "clkin",
126 [FUNC_CLKOUT] = "clkout",
127 [FUNC_CTIN] = "ctin",
128 [FUNC_CTOUT] = "ctout",
129 [FUNC_DAC] = "dac",
130 [FUNC_EMC] = "emc",
131 [FUNC_EMC_ALT] = "emc_alt",
132 [FUNC_ENET] = "enet",
133 [FUNC_ENET_ALT] = "enet_alt",
134 [FUNC_GPIO] = "gpio",
135 [FUNC_I2C0] = "i2c0",
136 [FUNC_I2C1] = "i2c1",
137 [FUNC_I2S0_RX_MCLK] = "i2s0_rx_mclk",
138 [FUNC_I2S0_RX_SCK] = "i2s0_rx_sck",
139 [FUNC_I2S0_RX_SDA] = "i2s0_rx_sda",
140 [FUNC_I2S0_RX_WS] = "i2s0_rx_ws",
141 [FUNC_I2S0_TX_MCLK] = "i2s0_tx_mclk",
142 [FUNC_I2S0_TX_SCK] = "i2s0_tx_sck",
143 [FUNC_I2S0_TX_SDA] = "i2s0_tx_sda",
144 [FUNC_I2S0_TX_WS] = "i2s0_tx_ws",
145 [FUNC_I2S1] = "i2s1",
146 [FUNC_LCD] = "lcd",
147 [FUNC_LCD_ALT] = "lcd_alt",
148 [FUNC_MCTRL] = "mctrl",
149 [FUNC_NMI] = "nmi",
150 [FUNC_QEI] = "qei",
151 [FUNC_SDMMC] = "sdmmc",
152 [FUNC_SGPIO] = "sgpio",
153 [FUNC_SPI] = "spi",
154 [FUNC_SPIFI] = "spifi",
155 [FUNC_SSP0] = "ssp0",
156 [FUNC_SSP0_ALT] = "ssp0_alt",
157 [FUNC_SSP1] = "ssp1",
158 [FUNC_TIMER0] = "timer0",
159 [FUNC_TIMER1] = "timer1",
160 [FUNC_TIMER2] = "timer2",
161 [FUNC_TIMER3] = "timer3",
162 [FUNC_TRACE] = "trace",
163 [FUNC_UART0] = "uart0",
164 [FUNC_UART1] = "uart1",
165 [FUNC_UART2] = "uart2",
166 [FUNC_UART3] = "uart3",
167 [FUNC_USB0] = "usb0",
168 [FUNC_USB1] = "usb1",
169};
170
171struct lpc18xx_pin_caps {
172 unsigned int offset;
173 unsigned char functions[LPC18XX_SCU_FUNC_PER_PIN];
174 unsigned char analog;
175 unsigned char type;
176};
177
178/* Analog pins are required to have both bias and input disabled */
179#define LPC18XX_SCU_ANALOG_PIN_CFG 0x10
180
181/* Macros to maniupluate analog member in lpc18xx_pin_caps */
182#define LPC18XX_ANALOG_PIN BIT(7)
183#define LPC18XX_ANALOG_ADC(a) ((a >> 5) & 0x3)
184#define LPC18XX_ANALOG_BIT_MASK 0x1f
185#define ADC0 (LPC18XX_ANALOG_PIN | (0x00 << 5))
186#define ADC1 (LPC18XX_ANALOG_PIN | (0x01 << 5))
187#define DAC LPC18XX_ANALOG_PIN
188
189#define LPC_P(port, pin, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \
190static struct lpc18xx_pin_caps lpc18xx_pin_p##port##_##pin = { \
191 .offset = 0x##port * 32 * 4 + pin * 4, \
192 .functions = { \
193 FUNC_##f0, FUNC_##f1, FUNC_##f2, \
194 FUNC_##f3, FUNC_##f4, FUNC_##f5, \
195 FUNC_##f6, FUNC_##f7, \
196 }, \
197 .analog = a, \
198 .type = TYPE_##t, \
199}
200
201#define LPC_N(pname, off, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \
202static struct lpc18xx_pin_caps lpc18xx_pin_##pname = { \
203 .offset = off, \
204 .functions = { \
205 FUNC_##f0, FUNC_##f1, FUNC_##f2, \
206 FUNC_##f3, FUNC_##f4, FUNC_##f5, \
207 FUNC_##f6, FUNC_##f7, \
208 }, \
209 .analog = a, \
210 .type = TYPE_##t, \
211}
212
213
214/* Pinmuxing table taken from data sheet */
215/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG TYPE */
216LPC_P(0,0, GPIO, SSP1, ENET, SGPIO, R, R, I2S0_TX_WS,I2S1, 0, ND);
217LPC_P(0,1, GPIO, SSP1,ENET_ALT,SGPIO, R, R, ENET, I2S1, 0, ND);
218LPC_P(1,0, GPIO, CTIN, EMC, R, R, SSP0, SGPIO, R, 0, ND);
219LPC_P(1,1, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
220LPC_P(1,2, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
221LPC_P(1,3, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
222LPC_P(1,4, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
223LPC_P(1,5, GPIO, CTOUT, R, EMC, USB0, SSP1, SGPIO, SDMMC, 0, ND);
224LPC_P(1,6, GPIO, CTIN, R, EMC, R, R, SGPIO, SDMMC, 0, ND);
225LPC_P(1,7, GPIO, UART1, CTOUT, EMC, USB0, R, R, R, 0, ND);
226LPC_P(1,8, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
227LPC_P(1,9, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
228LPC_P(1,10, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
229LPC_P(1,11, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
230LPC_P(1,12, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
231LPC_P(1,13, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
232LPC_P(1,14, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, R, 0, ND);
233LPC_P(1,15, GPIO, UART2, SGPIO, ENET, TIMER0, R, R, R, 0, ND);
234LPC_P(1,16, GPIO, UART2, SGPIO,ENET_ALT,TIMER0, R, R, ENET, 0, ND);
235LPC_P(1,17, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, HD);
236LPC_P(1,18, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, ND);
237LPC_P(1,19, ENET, SSP1, R, R, CLKOUT, R, I2S0_RX_MCLK,I2S1, 0, ND);
238LPC_P(1,20, GPIO, SSP1, R, ENET, TIMER0, R, SGPIO, R, 0, ND);
239LPC_P(2,0, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, ENET, 0, ND);
240LPC_P(2,1, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, R, 0, ND);
241LPC_P(2,2, SGPIO, UART0, EMC, USB0, GPIO, CTIN, TIMER3, R, 0, ND);
242LPC_P(2,3, SGPIO, I2C1, UART3, CTIN, GPIO, R, TIMER3, USB0, 0, HD);
243LPC_P(2,4, SGPIO, I2C1, UART3, CTIN, GPIO, R, TIMER3, USB0, 0, HD);
244LPC_P(2,5, SGPIO, CTIN, USB1, ADCTRIG, GPIO, R, TIMER3, USB0, 0, HD);
245LPC_P(2,6, SGPIO, UART0, EMC, USB0, GPIO, CTIN, TIMER3, R, 0, ND);
246LPC_P(2,7, GPIO, CTOUT, UART3, EMC, R, R, TIMER3, R, 0, ND);
247LPC_P(2,8, SGPIO, CTOUT, UART3, EMC, GPIO, R, R, R, 0, ND);
248LPC_P(2,9, GPIO, CTOUT, UART3, EMC, R, R, R, R, 0, ND);
249LPC_P(2,10, GPIO, CTOUT, UART2, EMC, R, R, R, R, 0, ND);
250LPC_P(2,11, GPIO, CTOUT, UART2, EMC, R, R, R, R, 0, ND);
251LPC_P(2,12, GPIO, CTOUT, R, EMC, R, R, R, UART2, 0, ND);
252LPC_P(2,13, GPIO, CTIN, R, EMC, R, R, R, UART2, 0, ND);
253LPC_P(3,0, I2S0_RX_SCK, I2S0_RX_MCLK, I2S0_TX_SCK, I2S0_TX_MCLK,SSP0,R,R,R, 0, ND);
254LPC_P(3,1, I2S0_TX_WS, I2S0_RX_WS,CAN0,USB1,GPIO, R, LCD, R, 0, ND);
255LPC_P(3,2, I2S0_TX_SDA, I2S0_RX_SDA,CAN0,USB1,GPIO, R, LCD, R, 0, ND);
256LPC_P(3,3, R, SPI, SSP0, SPIFI, CGU_OUT,R, I2S0_TX_MCLK, I2S1, 0, HS);
257LPC_P(3,4, GPIO, R, R, SPIFI, UART1, I2S0_TX_WS, I2S1, LCD, 0, ND);
258LPC_P(3,5, GPIO, R, R, SPIFI, UART1, I2S0_TX_SDA,I2S1, LCD, 0, ND);
259LPC_P(3,6, GPIO, SPI, SSP0, SPIFI, R, SSP0_ALT, R, R, 0, ND);
260LPC_P(3,7, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND);
261LPC_P(3,8, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND);
262LPC_P(4,0, GPIO, MCTRL, NMI, R, R, LCD, UART3, R, 0, ND);
263LPC_P(4,1, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, ENET, ADC0|1, ND);
264LPC_P(4,2, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, 0, ND);
265LPC_P(4,3, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, ADC0|0, ND);
266LPC_P(4,4, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, DAC, ND);
267LPC_P(4,5, GPIO, CTOUT, LCD, R, R, R, R, SGPIO, 0, ND);
268LPC_P(4,6, GPIO, CTOUT, LCD, R, R, R, R, SGPIO, 0, ND);
269LPC_P(4,7, LCD, CLKIN, R, R, R, R, I2S1,I2S0_TX_SCK, 0, ND);
270LPC_P(4,8, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
271LPC_P(4,9, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
272LPC_P(4,10, R, CTIN, LCD, R, GPIO, LCD_ALT, R, SGPIO, 0, ND);
273LPC_P(5,0, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
274LPC_P(5,1, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
275LPC_P(5,2, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
276LPC_P(5,3, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
277LPC_P(5,4, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
278LPC_P(5,5, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
279LPC_P(5,6, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
280LPC_P(5,7, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
281LPC_P(6,0, R, I2S0_RX_MCLK,R, R, I2S0_RX_SCK, R, R, R, 0, ND);
282LPC_P(6,1, GPIO, EMC, UART0, I2S0_RX_WS, R, TIMER2, R, R, 0, ND);
283LPC_P(6,2, GPIO, EMC, UART0, I2S0_RX_SDA, R, TIMER2, R, R, 0, ND);
284LPC_P(6,3, GPIO, USB0, SGPIO, EMC, R, TIMER2, R, R, 0, ND);
285LPC_P(6,4, GPIO, CTIN, UART0, EMC, R, R, R, R, 0, ND);
286LPC_P(6,5, GPIO, CTOUT, UART0, EMC, R, R, R, R, 0, ND);
287LPC_P(6,6, GPIO, EMC, SGPIO, USB0, R, TIMER2, R, R, 0, ND);
288LPC_P(6,7, R, EMC, SGPIO, USB0, GPIO, TIMER2, R, R, 0, ND);
289LPC_P(6,8, R, EMC, SGPIO, USB0, GPIO, TIMER2, R, R, 0, ND);
290LPC_P(6,9, GPIO, R, R, EMC, R, TIMER2, R, R, 0, ND);
291LPC_P(6,10, GPIO, MCTRL, R, EMC, R, R, R, R, 0, ND);
292LPC_P(6,11, GPIO, R, R, EMC, R, TIMER2, R, R, 0, ND);
293LPC_P(6,12, GPIO, CTOUT, R, EMC, R, R, R, R, 0, ND);
294LPC_P(7,0, GPIO, CTOUT, R, LCD, R, R, R, SGPIO, 0, ND);
295LPC_P(7,1, GPIO, CTOUT,I2S0_TX_WS,LCD,LCD_ALT, R, UART2, SGPIO, 0, ND);
296LPC_P(7,2, GPIO, CTIN,I2S0_TX_SDA,LCD,LCD_ALT, R, UART2, SGPIO, 0, ND);
297LPC_P(7,3, GPIO, CTIN, R, LCD,LCD_ALT, R, R, R, 0, ND);
298LPC_P(7,4, GPIO, CTOUT, R, LCD,LCD_ALT, TRACE, R, R, ADC0|4, ND);
299LPC_P(7,5, GPIO, CTOUT, R, LCD,LCD_ALT, TRACE, R, R, ADC0|3, ND);
300LPC_P(7,6, GPIO, CTOUT, R, LCD, R, TRACE, R, R, 0, ND);
301LPC_P(7,7, GPIO, CTOUT, R, LCD, R, TRACE, ENET, SGPIO, ADC1|6, ND);
302LPC_P(8,0, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
303LPC_P(8,1, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
304LPC_P(8,2, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
305LPC_P(8,3, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
306LPC_P(8,4, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
307LPC_P(8,5, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
308LPC_P(8,6, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
309LPC_P(8,7, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
310LPC_P(8,8, R, USB1, R, R, R, R,CGU_OUT, I2S1, 0, ND);
311LPC_P(9,0, GPIO, MCTRL, R, R, R, ENET, SGPIO, SSP0, 0, ND);
312LPC_P(9,1, GPIO, MCTRL, R, R, I2S0_TX_WS,ENET, SGPIO, SSP0, 0, ND);
313LPC_P(9,2, GPIO, MCTRL, R, R, I2S0_TX_SDA,ENET,SGPIO, SSP0, 0, ND);
314LPC_P(9,3, GPIO, MCTRL, USB1, R, R, ENET, SGPIO, UART3, 0, ND);
315LPC_P(9,4, R, MCTRL, USB1, R, GPIO, ENET, SGPIO, UART3, 0, ND);
316LPC_P(9,5, R, MCTRL, USB1, R, GPIO, ENET, SGPIO, UART0, 0, ND);
317LPC_P(9,6, GPIO, MCTRL, USB1, R, R, ENET, SGPIO, UART0, 0, ND);
318LPC_P(a,0, R, R, R, R, R, I2S1, CGU_OUT, R, 0, ND);
319LPC_P(a,1, GPIO, QEI, R, UART2, R, R, R, R, 0, HD);
320LPC_P(a,2, GPIO, QEI, R, UART2, R, R, R, R, 0, HD);
321LPC_P(a,3, GPIO, QEI, R, R, R, R, R, R, 0, HD);
322LPC_P(a,4, R, CTOUT, R, EMC, GPIO, R, R, R, 0, ND);
323LPC_P(b,0, R, CTOUT, LCD, R, GPIO, R, R, R, 0, ND);
324LPC_P(b,1, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
325LPC_P(b,2, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
326LPC_P(b,3, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
327LPC_P(b,4, R, USB1, LCD, R, GPIO, CTIN, R, R, 0, ND);
328LPC_P(b,5, R, USB1, LCD, R, GPIO, CTIN, LCD_ALT, R, 0, ND);
329LPC_P(b,6, R, USB1, LCD, R, GPIO, CTIN, LCD_ALT, R, ADC0|6, ND);
330LPC_P(c,0, R, USB1, R, ENET, LCD, R, R, SDMMC, ADC1|1, ND);
331LPC_P(c,1, USB1, R, UART1, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
332LPC_P(c,2, USB1, R, UART1, ENET, GPIO, R, R, SDMMC, 0, ND);
333LPC_P(c,3, USB1, R, UART1, ENET, GPIO, R, R, SDMMC, ADC1|0, ND);
334LPC_P(c,4, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
335LPC_P(c,5, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
336LPC_P(c,6, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
337LPC_P(c,7, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
338LPC_P(c,8, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
339LPC_P(c,9, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
340LPC_P(c,10, R, USB1, UART1, R, GPIO, R, TIMER3, SDMMC, 0, ND);
341LPC_P(c,11, R, USB1, UART1, R, GPIO, R, R, SDMMC, 0, ND);
342LPC_P(c,12, R, R, UART1, R, GPIO, SGPIO, I2S0_TX_SDA,SDMMC, 0, ND);
343LPC_P(c,13, R, R, UART1, R, GPIO, SGPIO, I2S0_TX_WS, SDMMC, 0, ND);
344LPC_P(c,14, R, R, UART1, R, GPIO, SGPIO, ENET, SDMMC, 0, ND);
345LPC_P(d,0, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
346LPC_P(d,1, R, R, EMC, R, GPIO, SDMMC, R, SGPIO, 0, ND);
347LPC_P(d,2, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
348LPC_P(d,3, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
349LPC_P(d,4, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
350LPC_P(d,5, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
351LPC_P(d,6, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
352LPC_P(d,7, R, CTIN, EMC, R, GPIO, R, R, SGPIO, 0, ND);
353LPC_P(d,8, R, CTIN, EMC, R, GPIO, R, R, SGPIO, 0, ND);
354LPC_P(d,9, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
355LPC_P(d,10, R, CTIN, EMC, R, GPIO, R, R, R, 0, ND);
356LPC_P(d,11, R, R, EMC, R, GPIO, USB1, CTOUT, R, 0, ND);
357LPC_P(d,12, R, R, EMC, R, GPIO, R, CTOUT, R, 0, ND);
358LPC_P(d,13, R, CTIN, EMC, R, GPIO, R, CTOUT, R, 0, ND);
359LPC_P(d,14, R, R, EMC, R, GPIO, R, CTOUT, R, 0, ND);
360LPC_P(d,15, R, R, EMC, R, GPIO, SDMMC, CTOUT, R, 0, ND);
361LPC_P(d,16, R, R, EMC, R, GPIO, SDMMC, CTOUT, R, 0, ND);
362LPC_P(e,0, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
363LPC_P(e,1, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
364LPC_P(e,2,ADCTRIG, CAN0, R, EMC, GPIO, R, R, R, 0, ND);
365LPC_P(e,3, R, CAN0,ADCTRIG, EMC, GPIO, R, R, R, 0, ND);
366LPC_P(e,4, R, NMI, R, EMC, GPIO, R, R, R, 0, ND);
367LPC_P(e,5, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
368LPC_P(e,6, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
369LPC_P(e,7, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
370LPC_P(e,8, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
371LPC_P(e,9, R, CTIN, UART1, EMC, GPIO, R, R, R, 0, ND);
372LPC_P(e,10, R, CTIN, UART1, EMC, GPIO, R, R, R, 0, ND);
373LPC_P(e,11, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
374LPC_P(e,12, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
375LPC_P(e,13, R, CTOUT, I2C1, EMC, GPIO, R, R, R, 0, ND);
376LPC_P(e,14, R, R, R, EMC, GPIO, R, R, R, 0, ND);
377LPC_P(e,15, R, CTOUT, I2C1, EMC, GPIO, R, R, R, 0, ND);
378LPC_P(f,0, SSP0, CLKIN, R, R, R, R, R, I2S1, 0, ND);
379LPC_P(f,1, R, R, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
380LPC_P(f,2, R, UART3, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
381LPC_P(f,3, R, UART3, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
382LPC_P(f,4, SSP1, CLKIN, TRACE, R, R, R, I2S0_TX_MCLK,I2S0_RX_SCK, 0, ND);
383LPC_P(f,5, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, R, ADC1|4, ND);
384LPC_P(f,6, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|3, ND);
385LPC_P(f,7, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|7, ND);
386LPC_P(f,8, R, UART0, CTIN, TRACE, GPIO, R, SGPIO, R, ADC0|2, ND);
387LPC_P(f,9, R, UART0, CTOUT, R, GPIO, R, SGPIO, R, ADC1|2, ND);
388LPC_P(f,10, R, UART0, R, R, GPIO, R, SDMMC, R, ADC0|5, ND);
389LPC_P(f,11, R, UART0, R, R, GPIO, R, SDMMC, R, ADC1|5, ND);
390
391/* Pin Offset FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG TYPE */
392LPC_N(clk0, 0xc00, EMC, CLKOUT, R, R, SDMMC, EMC_ALT, SSP1, ENET, 0, HS);
393LPC_N(clk1, 0xc04, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS);
394LPC_N(clk2, 0xc08, EMC, CLKOUT, R, R, SDMMC, EMC_ALT,I2S0_TX_MCLK,I2S1, 0, HS);
395LPC_N(clk3, 0xc0c, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS);
396LPC_N(usb1_dm, 0xc80, R, R, R, R, R, R, R, R, 0, USB1);
397LPC_N(usb1_dp, 0xc80, R, R, R, R, R, R, R, R, 0, USB1);
398LPC_N(i2c0_scl, 0xc84, R, R, R, R, R, R, R, R, 0, I2C0);
399LPC_N(i2c0_sda, 0xc84, R, R, R, R, R, R, R, R, 0, I2C0);
400
401#define LPC18XX_PIN_P(port, pin) { \
402 .number = 0x##port * 32 + pin, \
403 .name = "p"#port"_"#pin, \
404 .drv_data = &lpc18xx_pin_p##port##_##pin \
405}
406
407/* Pin numbers for special pins */
408enum {
409 PIN_CLK0 = 600,
410 PIN_CLK1,
411 PIN_CLK2,
412 PIN_CLK3,
413 PIN_USB1_DM,
414 PIN_USB1_DP,
415 PIN_I2C0_SCL,
416 PIN_I2C0_SDA,
417};
418
419#define LPC18XX_PIN(pname, n) { \
420 .number = n, \
421 .name = #pname, \
422 .drv_data = &lpc18xx_pin_##pname \
423}
424
425static const struct pinctrl_pin_desc lpc18xx_pins[] = {
426 LPC18XX_PIN_P(0,0),
427 LPC18XX_PIN_P(0,1),
428 LPC18XX_PIN_P(1,0),
429 LPC18XX_PIN_P(1,1),
430 LPC18XX_PIN_P(1,2),
431 LPC18XX_PIN_P(1,3),
432 LPC18XX_PIN_P(1,4),
433 LPC18XX_PIN_P(1,5),
434 LPC18XX_PIN_P(1,6),
435 LPC18XX_PIN_P(1,7),
436 LPC18XX_PIN_P(1,8),
437 LPC18XX_PIN_P(1,9),
438 LPC18XX_PIN_P(1,10),
439 LPC18XX_PIN_P(1,11),
440 LPC18XX_PIN_P(1,12),
441 LPC18XX_PIN_P(1,13),
442 LPC18XX_PIN_P(1,14),
443 LPC18XX_PIN_P(1,15),
444 LPC18XX_PIN_P(1,16),
445 LPC18XX_PIN_P(1,17),
446 LPC18XX_PIN_P(1,18),
447 LPC18XX_PIN_P(1,19),
448 LPC18XX_PIN_P(1,20),
449 LPC18XX_PIN_P(2,0),
450 LPC18XX_PIN_P(2,1),
451 LPC18XX_PIN_P(2,2),
452 LPC18XX_PIN_P(2,3),
453 LPC18XX_PIN_P(2,4),
454 LPC18XX_PIN_P(2,5),
455 LPC18XX_PIN_P(2,6),
456 LPC18XX_PIN_P(2,7),
457 LPC18XX_PIN_P(2,8),
458 LPC18XX_PIN_P(2,9),
459 LPC18XX_PIN_P(2,10),
460 LPC18XX_PIN_P(2,11),
461 LPC18XX_PIN_P(2,12),
462 LPC18XX_PIN_P(2,13),
463 LPC18XX_PIN_P(3,0),
464 LPC18XX_PIN_P(3,1),
465 LPC18XX_PIN_P(3,2),
466 LPC18XX_PIN_P(3,3),
467 LPC18XX_PIN_P(3,4),
468 LPC18XX_PIN_P(3,5),
469 LPC18XX_PIN_P(3,6),
470 LPC18XX_PIN_P(3,7),
471 LPC18XX_PIN_P(3,8),
472 LPC18XX_PIN_P(4,0),
473 LPC18XX_PIN_P(4,1),
474 LPC18XX_PIN_P(4,2),
475 LPC18XX_PIN_P(4,3),
476 LPC18XX_PIN_P(4,4),
477 LPC18XX_PIN_P(4,5),
478 LPC18XX_PIN_P(4,6),
479 LPC18XX_PIN_P(4,7),
480 LPC18XX_PIN_P(4,8),
481 LPC18XX_PIN_P(4,9),
482 LPC18XX_PIN_P(4,10),
483 LPC18XX_PIN_P(5,0),
484 LPC18XX_PIN_P(5,1),
485 LPC18XX_PIN_P(5,2),
486 LPC18XX_PIN_P(5,3),
487 LPC18XX_PIN_P(5,4),
488 LPC18XX_PIN_P(5,5),
489 LPC18XX_PIN_P(5,6),
490 LPC18XX_PIN_P(5,7),
491 LPC18XX_PIN_P(6,0),
492 LPC18XX_PIN_P(6,1),
493 LPC18XX_PIN_P(6,2),
494 LPC18XX_PIN_P(6,3),
495 LPC18XX_PIN_P(6,4),
496 LPC18XX_PIN_P(6,5),
497 LPC18XX_PIN_P(6,6),
498 LPC18XX_PIN_P(6,7),
499 LPC18XX_PIN_P(6,8),
500 LPC18XX_PIN_P(6,9),
501 LPC18XX_PIN_P(6,10),
502 LPC18XX_PIN_P(6,11),
503 LPC18XX_PIN_P(6,12),
504 LPC18XX_PIN_P(7,0),
505 LPC18XX_PIN_P(7,1),
506 LPC18XX_PIN_P(7,2),
507 LPC18XX_PIN_P(7,3),
508 LPC18XX_PIN_P(7,4),
509 LPC18XX_PIN_P(7,5),
510 LPC18XX_PIN_P(7,6),
511 LPC18XX_PIN_P(7,7),
512 LPC18XX_PIN_P(8,0),
513 LPC18XX_PIN_P(8,1),
514 LPC18XX_PIN_P(8,2),
515 LPC18XX_PIN_P(8,3),
516 LPC18XX_PIN_P(8,4),
517 LPC18XX_PIN_P(8,5),
518 LPC18XX_PIN_P(8,6),
519 LPC18XX_PIN_P(8,7),
520 LPC18XX_PIN_P(8,8),
521 LPC18XX_PIN_P(9,0),
522 LPC18XX_PIN_P(9,1),
523 LPC18XX_PIN_P(9,2),
524 LPC18XX_PIN_P(9,3),
525 LPC18XX_PIN_P(9,4),
526 LPC18XX_PIN_P(9,5),
527 LPC18XX_PIN_P(9,6),
528 LPC18XX_PIN_P(a,0),
529 LPC18XX_PIN_P(a,1),
530 LPC18XX_PIN_P(a,2),
531 LPC18XX_PIN_P(a,3),
532 LPC18XX_PIN_P(a,4),
533 LPC18XX_PIN_P(b,0),
534 LPC18XX_PIN_P(b,1),
535 LPC18XX_PIN_P(b,2),
536 LPC18XX_PIN_P(b,3),
537 LPC18XX_PIN_P(b,4),
538 LPC18XX_PIN_P(b,5),
539 LPC18XX_PIN_P(b,6),
540 LPC18XX_PIN_P(c,0),
541 LPC18XX_PIN_P(c,1),
542 LPC18XX_PIN_P(c,2),
543 LPC18XX_PIN_P(c,3),
544 LPC18XX_PIN_P(c,4),
545 LPC18XX_PIN_P(c,5),
546 LPC18XX_PIN_P(c,6),
547 LPC18XX_PIN_P(c,7),
548 LPC18XX_PIN_P(c,8),
549 LPC18XX_PIN_P(c,9),
550 LPC18XX_PIN_P(c,10),
551 LPC18XX_PIN_P(c,11),
552 LPC18XX_PIN_P(c,12),
553 LPC18XX_PIN_P(c,13),
554 LPC18XX_PIN_P(c,14),
555 LPC18XX_PIN_P(d,0),
556 LPC18XX_PIN_P(d,1),
557 LPC18XX_PIN_P(d,2),
558 LPC18XX_PIN_P(d,3),
559 LPC18XX_PIN_P(d,4),
560 LPC18XX_PIN_P(d,5),
561 LPC18XX_PIN_P(d,6),
562 LPC18XX_PIN_P(d,7),
563 LPC18XX_PIN_P(d,8),
564 LPC18XX_PIN_P(d,9),
565 LPC18XX_PIN_P(d,10),
566 LPC18XX_PIN_P(d,11),
567 LPC18XX_PIN_P(d,12),
568 LPC18XX_PIN_P(d,13),
569 LPC18XX_PIN_P(d,14),
570 LPC18XX_PIN_P(d,15),
571 LPC18XX_PIN_P(d,16),
572 LPC18XX_PIN_P(e,0),
573 LPC18XX_PIN_P(e,1),
574 LPC18XX_PIN_P(e,2),
575 LPC18XX_PIN_P(e,3),
576 LPC18XX_PIN_P(e,4),
577 LPC18XX_PIN_P(e,5),
578 LPC18XX_PIN_P(e,6),
579 LPC18XX_PIN_P(e,7),
580 LPC18XX_PIN_P(e,8),
581 LPC18XX_PIN_P(e,9),
582 LPC18XX_PIN_P(e,10),
583 LPC18XX_PIN_P(e,11),
584 LPC18XX_PIN_P(e,12),
585 LPC18XX_PIN_P(e,13),
586 LPC18XX_PIN_P(e,14),
587 LPC18XX_PIN_P(e,15),
588 LPC18XX_PIN_P(f,0),
589 LPC18XX_PIN_P(f,1),
590 LPC18XX_PIN_P(f,2),
591 LPC18XX_PIN_P(f,3),
592 LPC18XX_PIN_P(f,4),
593 LPC18XX_PIN_P(f,5),
594 LPC18XX_PIN_P(f,6),
595 LPC18XX_PIN_P(f,7),
596 LPC18XX_PIN_P(f,8),
597 LPC18XX_PIN_P(f,9),
598 LPC18XX_PIN_P(f,10),
599 LPC18XX_PIN_P(f,11),
600
601 LPC18XX_PIN(clk0, PIN_CLK0),
602 LPC18XX_PIN(clk1, PIN_CLK1),
603 LPC18XX_PIN(clk2, PIN_CLK2),
604 LPC18XX_PIN(clk3, PIN_CLK3),
605 LPC18XX_PIN(usb1_dm, PIN_USB1_DM),
606 LPC18XX_PIN(usb1_dp, PIN_USB1_DP),
607 LPC18XX_PIN(i2c0_scl, PIN_I2C0_SCL),
608 LPC18XX_PIN(i2c0_sda, PIN_I2C0_SDA),
609};
610
611static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg)
612{
613 /* TODO */
614 return -ENOTSUPP;
615}
616
617static int lpc18xx_pconf_get_i2c0(enum pin_config_param param, int *arg, u32 reg,
618 unsigned pin)
619{
620 u8 shift;
621
622 if (pin == PIN_I2C0_SCL)
623 shift = LPC18XX_SCU_I2C0_SCL_SHIFT;
624 else
625 shift = LPC18XX_SCU_I2C0_SDA_SHIFT;
626
627 switch (param) {
628 case PIN_CONFIG_INPUT_ENABLE:
629 if (reg & (LPC18XX_SCU_I2C0_EZI << shift))
630 *arg = 1;
631 else
632 return -EINVAL;
633 break;
634
635 case PIN_CONFIG_SLEW_RATE:
636 if (reg & (LPC18XX_SCU_I2C0_EHD << shift))
637 *arg = 1;
638 else
639 *arg = 0;
640 break;
641
642 case PIN_CONFIG_INPUT_SCHMITT:
643 if (reg & (LPC18XX_SCU_I2C0_EFP << shift))
644 *arg = 3;
645 else
646 *arg = 50;
647 break;
648
649 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
650 if (reg & (LPC18XX_SCU_I2C0_ZIF << shift))
651 return -EINVAL;
652 else
653 *arg = 1;
654 break;
655
656 default:
657 return -ENOTSUPP;
658 }
659
660 return 0;
661}
662
663static int lpc18xx_pconf_get_pin(enum pin_config_param param, int *arg, u32 reg,
664 struct lpc18xx_pin_caps *pin_cap)
665{
666 switch (param) {
667 case PIN_CONFIG_BIAS_DISABLE:
668 if ((!(reg & LPC18XX_SCU_PIN_EPD)) && (reg & LPC18XX_SCU_PIN_EPUN))
669 ;
670 else
671 return -EINVAL;
672 break;
673
674 case PIN_CONFIG_BIAS_PULL_UP:
675 if (reg & LPC18XX_SCU_PIN_EPUN)
676 return -EINVAL;
677 else
678 *arg = 1;
679 break;
680
681 case PIN_CONFIG_BIAS_PULL_DOWN:
682 if (reg & LPC18XX_SCU_PIN_EPD)
683 *arg = 1;
684 else
685 return -EINVAL;
686 break;
687
688 case PIN_CONFIG_INPUT_ENABLE:
689 if (reg & LPC18XX_SCU_PIN_EZI)
690 *arg = 1;
691 else
692 return -EINVAL;
693 break;
694
695 case PIN_CONFIG_SLEW_RATE:
696 if (pin_cap->type == TYPE_HD)
697 return -ENOTSUPP;
698
699 if (reg & LPC18XX_SCU_PIN_EHS)
700 *arg = 1;
701 else
702 *arg = 0;
703 break;
704
705 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
706 if (reg & LPC18XX_SCU_PIN_ZIF)
707 return -EINVAL;
708 else
709 *arg = 1;
710 break;
711
712 case PIN_CONFIG_DRIVE_STRENGTH:
713 if (pin_cap->type != TYPE_HD)
714 return -ENOTSUPP;
715
716 *arg = (reg & LPC18XX_SCU_PIN_EHD_MASK) >> LPC18XX_SCU_PIN_EHD_POS;
717 switch (*arg) {
718 case 3: *arg += 5;
719 case 2: *arg += 5;
720 case 1: *arg += 3;
721 case 0: *arg += 4;
722 }
723 break;
724
725 default:
726 return -ENOTSUPP;
727 }
728
729 return 0;
730}
731
732static int lpc18xx_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
733 unsigned long *config)
734{
735 struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
736 enum pin_config_param param = pinconf_to_config_param(*config);
737 struct lpc18xx_pin_caps *pin_cap;
738 int ret, arg = 0;
739 u32 reg;
740 int i;
741
742 for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
743 if (lpc18xx_pins[i].number == pin)
744 pin = i;
745 }
746
747 pin_cap = lpc18xx_pins[pin].drv_data;
748 reg = readl(scu->base + pin_cap->offset);
749
750 if (pin_cap->type == TYPE_I2C0)
751 ret = lpc18xx_pconf_get_i2c0(param, &arg, reg, pin);
752 else if (pin_cap->type == TYPE_USB1)
753 ret = lpc18xx_pconf_get_usb1(param, &arg, reg);
754 else
755 ret = lpc18xx_pconf_get_pin(param, &arg, reg, pin_cap);
756
757 if (ret < 0)
758 return ret;
759
760 *config = pinconf_to_config_packed(param, (u16)arg);
761
762 return 0;
763}
764
765static int lpc18xx_pconf_set_usb1(struct pinctrl_dev *pctldev,
766 enum pin_config_param param,
767 u16 param_val, u32 *reg)
768{
769 /* TODO */
770 return -ENOTSUPP;
771}
772
773static int lpc18xx_pconf_set_i2c0(struct pinctrl_dev *pctldev,
774 enum pin_config_param param,
775 u16 param_val, u32 *reg,
776 unsigned pin)
777{
778 u8 shift;
779
780 if (pin == PIN_I2C0_SCL)
781 shift = LPC18XX_SCU_I2C0_SCL_SHIFT;
782 else
783 shift = LPC18XX_SCU_I2C0_SDA_SHIFT;
784
785 switch (param) {
786 case PIN_CONFIG_INPUT_ENABLE:
787 if (param_val)
788 *reg |= (LPC18XX_SCU_I2C0_EZI << shift);
789 else
790 *reg &= ~(LPC18XX_SCU_I2C0_EZI << shift);
791 break;
792
793 case PIN_CONFIG_SLEW_RATE:
794 if (param_val)
795 *reg |= (LPC18XX_SCU_I2C0_EHD << shift);
796 else
797 *reg &= ~(LPC18XX_SCU_I2C0_EHD << shift);
798 break;
799
800 case PIN_CONFIG_INPUT_SCHMITT:
801 if (param_val == 3)
802 *reg |= (LPC18XX_SCU_I2C0_EFP << shift);
803 else if (param_val == 50)
804 *reg &= ~(LPC18XX_SCU_I2C0_EFP << shift);
805 else
806 return -ENOTSUPP;
807 break;
808
809 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
810 if (param)
811 *reg &= ~(LPC18XX_SCU_I2C0_ZIF << shift);
812 else
813 *reg |= (LPC18XX_SCU_I2C0_ZIF << shift);
814 break;
815
816 default:
817 dev_err(pctldev->dev, "Property not supported\n");
818 return -ENOTSUPP;
819 }
820
821 return 0;
822}
823
824static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev,
825 enum pin_config_param param,
826 u16 param_val, u32 *reg,
827 struct lpc18xx_pin_caps *pin_cap)
828{
829 switch (param) {
830 case PIN_CONFIG_BIAS_DISABLE:
831 *reg &= ~LPC18XX_SCU_PIN_EPD;
832 *reg |= LPC18XX_SCU_PIN_EPUN;
833 break;
834
835 case PIN_CONFIG_BIAS_PULL_UP:
836 *reg &= ~LPC18XX_SCU_PIN_EPUN;
837 break;
838
839 case PIN_CONFIG_BIAS_PULL_DOWN:
840 *reg |= LPC18XX_SCU_PIN_EPD;
841 break;
842
843 case PIN_CONFIG_INPUT_ENABLE:
844 if (param_val)
845 *reg |= LPC18XX_SCU_PIN_EZI;
846 else
847 *reg &= ~LPC18XX_SCU_PIN_EZI;
848 break;
849
850 case PIN_CONFIG_SLEW_RATE:
851 if (pin_cap->type == TYPE_HD) {
852 dev_err(pctldev->dev, "Slew rate unsupported on high-drive pins\n");
853 return -ENOTSUPP;
854 }
855
856 if (param_val == 0)
857 *reg &= ~LPC18XX_SCU_PIN_EHS;
858 else
859 *reg |= LPC18XX_SCU_PIN_EHS;
860 break;
861
862 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
863 if (param)
864 *reg &= ~LPC18XX_SCU_PIN_ZIF;
865 else
866 *reg |= LPC18XX_SCU_PIN_ZIF;
867 break;
868
869 case PIN_CONFIG_DRIVE_STRENGTH:
870 if (pin_cap->type != TYPE_HD) {
871 dev_err(pctldev->dev, "Drive strength available only on high-drive pins\n");
872 return -ENOTSUPP;
873 }
874 *reg &= ~LPC18XX_SCU_PIN_EHD_MASK;
875
876 switch (param_val) {
877 case 20: param_val -= 5;
878 case 14: param_val -= 5;
879 case 8: param_val -= 3;
880 case 4: param_val -= 4;
881 break;
882 default:
883 dev_err(pctldev->dev, "Drive strength %u unsupported\n", param_val);
884 return -ENOTSUPP;
885 }
886 *reg |= param_val << LPC18XX_SCU_PIN_EHD_POS;
887 break;
888
889 default:
890 dev_err(pctldev->dev, "Property not supported\n");
891 return -ENOTSUPP;
892 }
893
894 return 0;
895}
896
897static int lpc18xx_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
898 unsigned long *configs, unsigned num_configs)
899{
900 struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
901 struct lpc18xx_pin_caps *pin_cap;
902 enum pin_config_param param;
903 u16 param_val;
904 u32 reg;
905 int ret;
906 int i;
907
908 for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
909 if (lpc18xx_pins[i].number == pin)
910 break;
911 }
912
913 pin_cap = lpc18xx_pins[i].drv_data;
914 reg = readl(scu->base + pin_cap->offset);
915
916 for (i = 0; i < num_configs; i++) {
917 param = pinconf_to_config_param(configs[i]);
918 param_val = pinconf_to_config_argument(configs[i]);
919
920 if (pin_cap->type == TYPE_I2C0)
921 ret = lpc18xx_pconf_set_i2c0(pctldev, param, param_val, &reg, pin);
922 else if (pin_cap->type == TYPE_USB1)
923 ret = lpc18xx_pconf_set_usb1(pctldev, param, param_val, &reg);
924 else
925 ret = lpc18xx_pconf_set_pin(pctldev, param, param_val, &reg, pin_cap);
926
927 if (ret)
928 return ret;
929 }
930
931 writel(reg, scu->base + pin_cap->offset);
932
933 return 0;
934}
935
936static const struct pinconf_ops lpc18xx_pconf_ops = {
937 .is_generic = true,
938 .pin_config_get = lpc18xx_pconf_get,
939 .pin_config_set = lpc18xx_pconf_set,
940};
941
942static int lpc18xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
943{
944 return ARRAY_SIZE(lpc18xx_function_names);
945}
946
947static const char *lpc18xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
948 unsigned function)
949{
950 return lpc18xx_function_names[function];
951}
952
953static int lpc18xx_pmx_get_func_groups(struct pinctrl_dev *pctldev,
954 unsigned function,
955 const char *const **groups,
956 unsigned *const num_groups)
957{
958 return 0;
959}
960
961static int lpc18xx_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
962 unsigned group)
963{
964 struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
965 struct lpc18xx_pin_caps *pin = lpc18xx_pins[group].drv_data;
966 int func;
967 u32 reg;
968
969 /* Dedicated USB1 and I2C0 pins doesn't support muxing */
970 if (pin->type == TYPE_USB1) {
971 if (function == FUNC_USB1)
972 return 0;
973
974 goto fail;
975 }
976
977 if (pin->type == TYPE_I2C0) {
978 if (function == FUNC_I2C0)
979 return 0;
980
981 goto fail;
982 }
983
984 if (function == FUNC_ADC && (pin->analog & LPC18XX_ANALOG_PIN)) {
985 u32 offset;
986
987 writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
988
989 if (LPC18XX_ANALOG_ADC(pin->analog) == 0)
990 offset = LPC18XX_SCU_REG_ENAIO0;
991 else
992 offset = LPC18XX_SCU_REG_ENAIO1;
993
994 reg = readl(scu->base + offset);
995 reg |= pin->analog & LPC18XX_ANALOG_BIT_MASK;
996 writel(reg, scu->base + offset);
997
998 return 0;
999 }
1000
1001 if (function == FUNC_DAC && (pin->analog & LPC18XX_ANALOG_PIN)) {
1002 writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
1003
1004 reg = readl(scu->base + LPC18XX_SCU_REG_ENAIO2);
1005 reg |= LPC18XX_SCU_REG_ENAIO2_DAC;
1006 writel(reg, scu->base + LPC18XX_SCU_REG_ENAIO2);
1007
1008 return 0;
1009 }
1010
1011 for (func = 0; func < LPC18XX_SCU_FUNC_PER_PIN; func++) {
1012 if (function == pin->functions[func])
1013 break;
1014 }
1015
1016 if (func >= LPC18XX_SCU_FUNC_PER_PIN)
1017 goto fail;
1018
1019 reg = readl(scu->base + pin->offset);
1020 reg &= ~LPC18XX_SCU_PIN_MODE_MASK;
1021 writel(reg | func, scu->base + pin->offset);
1022
1023 return 0;
1024fail:
1025 dev_err(pctldev->dev, "Pin %s can't be %s\n", lpc18xx_pins[group].name,
1026 lpc18xx_function_names[function]);
1027 return -EINVAL;
1028}
1029
1030static const struct pinmux_ops lpc18xx_pmx_ops = {
1031 .get_functions_count = lpc18xx_pmx_get_funcs_count,
1032 .get_function_name = lpc18xx_pmx_get_func_name,
1033 .get_function_groups = lpc18xx_pmx_get_func_groups,
1034 .set_mux = lpc18xx_pmx_set,
1035};
1036
1037static int lpc18xx_pctl_get_groups_count(struct pinctrl_dev *pctldev)
1038{
1039 return ARRAY_SIZE(lpc18xx_pins);
1040}
1041
1042static const char *lpc18xx_pctl_get_group_name(struct pinctrl_dev *pctldev,
1043 unsigned group)
1044{
1045 return lpc18xx_pins[group].name;
1046}
1047
1048static int lpc18xx_pctl_get_group_pins(struct pinctrl_dev *pctldev,
1049 unsigned group,
1050 const unsigned **pins,
1051 unsigned *num_pins)
1052{
1053 *pins = &lpc18xx_pins[group].number;
1054 *num_pins = 1;
1055
1056 return 0;
1057}
1058
1059static const struct pinctrl_ops lpc18xx_pctl_ops = {
1060 .get_groups_count = lpc18xx_pctl_get_groups_count,
1061 .get_group_name = lpc18xx_pctl_get_group_name,
1062 .get_group_pins = lpc18xx_pctl_get_group_pins,
1063 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1064 .dt_free_map = pinctrl_utils_dt_free_map,
1065};
1066
1067static struct pinctrl_desc lpc18xx_scu_desc = {
1068 .name = "lpc18xx/43xx-scu",
1069 .pins = lpc18xx_pins,
1070 .npins = ARRAY_SIZE(lpc18xx_pins),
1071 .pctlops = &lpc18xx_pctl_ops,
1072 .pmxops = &lpc18xx_pmx_ops,
1073 .confops = &lpc18xx_pconf_ops,
1074 .owner = THIS_MODULE,
1075};
1076
1077static int lpc18xx_scu_probe(struct platform_device *pdev)
1078{
1079 struct lpc18xx_scu_data *scu;
1080 struct resource *res;
1081 int ret;
1082
1083 scu = devm_kzalloc(&pdev->dev, sizeof(*scu), GFP_KERNEL);
1084 if (!scu)
1085 return -ENOMEM;
1086
1087 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1088 scu->base = devm_ioremap_resource(&pdev->dev, res);
1089 if (IS_ERR(scu->base))
1090 return PTR_ERR(scu->base);
1091
1092 scu->clk = devm_clk_get(&pdev->dev, NULL);
1093 if (IS_ERR(scu->clk)) {
1094 dev_err(&pdev->dev, "Input clock not found.\n");
1095 return PTR_ERR(scu->clk);
1096 }
1097
1098 ret = clk_prepare_enable(scu->clk);
1099 if (ret) {
1100 dev_err(&pdev->dev, "Unable to enable clock.\n");
1101 return ret;
1102 }
1103
1104 platform_set_drvdata(pdev, scu);
1105
1106 scu->pctl = pinctrl_register(&lpc18xx_scu_desc, &pdev->dev, scu);
1107 if (!scu->pctl) {
1108 dev_err(&pdev->dev, "Could not register pinctrl driver\n");
1109 clk_disable_unprepare(scu->clk);
1110 return -EINVAL;
1111 }
1112
1113 return 0;
1114}
1115
1116static int lpc18xx_scu_remove(struct platform_device *pdev)
1117{
1118 struct lpc18xx_scu_data *scu = platform_get_drvdata(pdev);
1119
1120 pinctrl_unregister(scu->pctl);
1121 clk_disable_unprepare(scu->clk);
1122
1123 return 0;
1124}
1125
1126static const struct of_device_id lpc18xx_scu_match[] = {
1127 { .compatible = "nxp,lpc1850-scu" },
1128 {},
1129};
1130MODULE_DEVICE_TABLE(of, lpc18xx_scu_match);
1131
1132static struct platform_driver lpc18xx_scu_driver = {
1133 .probe = lpc18xx_scu_probe,
1134 .remove = lpc18xx_scu_remove,
1135 .driver = {
1136 .name = "lpc18xx-scu",
1137 .of_match_table = lpc18xx_scu_match,
1138 },
1139};
1140module_platform_driver(lpc18xx_scu_driver);
1141
1142MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
1143MODULE_DESCRIPTION("Pinctrl driver for NXP LPC18xx/43xx SCU");
1144MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 04:09:18 -0400