diff options
| -rw-r--r-- | drivers/gpu/drm/tegra/dc.c | 73 | ||||
| -rw-r--r-- | drivers/gpu/drm/tegra/dc.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/tegra/dpaux.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/tegra/drm.c | 35 | ||||
| -rw-r--r-- | drivers/gpu/drm/tegra/drm.h | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/tegra/fb.c | 24 | ||||
| -rw-r--r-- | drivers/gpu/drm/tegra/hub.c | 19 | ||||
| -rw-r--r-- | drivers/gpu/drm/tegra/hub.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/tegra/sor.c | 110 | ||||
| -rw-r--r-- | drivers/gpu/host1x/bus.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/host1x/dev.c | 13 |
11 files changed, 233 insertions, 53 deletions
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 965088afcfad..f80e82e16475 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c | |||
| @@ -1988,6 +1988,28 @@ static int tegra_dc_init(struct host1x_client *client) | |||
| 1988 | struct drm_plane *cursor = NULL; | 1988 | struct drm_plane *cursor = NULL; |
| 1989 | int err; | 1989 | int err; |
| 1990 | 1990 | ||
| 1991 | /* | ||
| 1992 | * XXX do not register DCs with no window groups because we cannot | ||
| 1993 | * assign a primary plane to them, which in turn will cause KMS to | ||
| 1994 | * crash. | ||
| 1995 | */ | ||
| 1996 | if (dc->soc->wgrps) { | ||
| 1997 | bool has_wgrps = false; | ||
| 1998 | unsigned int i; | ||
| 1999 | |||
| 2000 | for (i = 0; i < dc->soc->num_wgrps; i++) { | ||
| 2001 | const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; | ||
| 2002 | |||
| 2003 | if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) { | ||
| 2004 | has_wgrps = true; | ||
| 2005 | break; | ||
| 2006 | } | ||
| 2007 | } | ||
| 2008 | |||
| 2009 | if (!has_wgrps) | ||
| 2010 | return 0; | ||
| 2011 | } | ||
| 2012 | |||
| 1991 | dc->syncpt = host1x_syncpt_request(client, flags); | 2013 | dc->syncpt = host1x_syncpt_request(client, flags); |
| 1992 | if (!dc->syncpt) | 2014 | if (!dc->syncpt) |
| 1993 | dev_warn(dc->dev, "failed to allocate syncpoint\n"); | 2015 | dev_warn(dc->dev, "failed to allocate syncpoint\n"); |
| @@ -2234,8 +2256,59 @@ static const struct tegra_dc_soc_info tegra186_dc_soc_info = { | |||
| 2234 | .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), | 2256 | .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), |
| 2235 | }; | 2257 | }; |
| 2236 | 2258 | ||
| 2259 | static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = { | ||
| 2260 | { | ||
| 2261 | .index = 0, | ||
| 2262 | .dc = 0, | ||
| 2263 | .windows = (const unsigned int[]) { 0 }, | ||
| 2264 | .num_windows = 1, | ||
| 2265 | }, { | ||
| 2266 | .index = 1, | ||
| 2267 | .dc = 1, | ||
| 2268 | .windows = (const unsigned int[]) { 1 }, | ||
| 2269 | .num_windows = 1, | ||
| 2270 | }, { | ||
| 2271 | .index = 2, | ||
| 2272 | .dc = 1, | ||
| 2273 | .windows = (const unsigned int[]) { 2 }, | ||
| 2274 | .num_windows = 1, | ||
| 2275 | }, { | ||
| 2276 | .index = 3, | ||
| 2277 | .dc = 2, | ||
| 2278 | .windows = (const unsigned int[]) { 3 }, | ||
| 2279 | .num_windows = 1, | ||
| 2280 | }, { | ||
| 2281 | .index = 4, | ||
| 2282 | .dc = 2, | ||
| 2283 | .windows = (const unsigned int[]) { 4 }, | ||
| 2284 | .num_windows = 1, | ||
| 2285 | }, { | ||
| 2286 | .index = 5, | ||
| 2287 | .dc = 2, | ||
| 2288 | .windows = (const unsigned int[]) { 5 }, | ||
| 2289 | .num_windows = 1, | ||
| 2290 | }, | ||
| 2291 | }; | ||
| 2292 | |||
| 2293 | static const struct tegra_dc_soc_info tegra194_dc_soc_info = { | ||
| 2294 | .supports_background_color = true, | ||
| 2295 | .supports_interlacing = true, | ||
| 2296 | .supports_cursor = true, | ||
| 2297 | .supports_block_linear = true, | ||
| 2298 | .has_legacy_blending = false, | ||
| 2299 | .pitch_align = 64, | ||
| 2300 | .has_powergate = false, | ||
| 2301 | .coupled_pm = false, | ||
| 2302 | .has_nvdisplay = true, | ||
| 2303 | .wgrps = tegra194_dc_wgrps, | ||
| 2304 | .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps), | ||
| 2305 | }; | ||
| 2306 | |||
| 2237 | static const struct of_device_id tegra_dc_of_match[] = { | 2307 | static const struct of_device_id tegra_dc_of_match[] = { |
| 2238 | { | 2308 | { |
| 2309 | .compatible = "nvidia,tegra194-dc", | ||
| 2310 | .data = &tegra194_dc_soc_info, | ||
| 2311 | }, { | ||
| 2239 | .compatible = "nvidia,tegra186-dc", | 2312 | .compatible = "nvidia,tegra186-dc", |
| 2240 | .data = &tegra186_dc_soc_info, | 2313 | .data = &tegra186_dc_soc_info, |
| 2241 | }, { | 2314 | }, { |
diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index e96f582ca692..1256dfb6b2f5 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h | |||
| @@ -300,7 +300,7 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc); | |||
| 300 | #define SOR1_TIMING_CYA (1 << 27) | 300 | #define SOR1_TIMING_CYA (1 << 27) |
| 301 | #define CURSOR_ENABLE (1 << 16) | 301 | #define CURSOR_ENABLE (1 << 16) |
| 302 | 302 | ||
| 303 | #define SOR_ENABLE(x) (1 << (25 + (x))) | 303 | #define SOR_ENABLE(x) (1 << (25 + (((x) > 1) ? ((x) + 1) : (x)))) |
| 304 | 304 | ||
| 305 | #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 | 305 | #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 |
| 306 | #define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24) | 306 | #define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24) |
diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index d84e81ff36ad..ee4180d8db14 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c | |||
| @@ -521,7 +521,7 @@ static int tegra_dpaux_probe(struct platform_device *pdev) | |||
| 521 | * is no possibility to perform the I2C mode configuration in the | 521 | * is no possibility to perform the I2C mode configuration in the |
| 522 | * HDMI path. | 522 | * HDMI path. |
| 523 | */ | 523 | */ |
| 524 | err = tegra_dpaux_pad_config(dpaux, DPAUX_HYBRID_PADCTL_MODE_I2C); | 524 | err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C); |
| 525 | if (err < 0) | 525 | if (err < 0) |
| 526 | return err; | 526 | return err; |
| 527 | 527 | ||
| @@ -639,6 +639,7 @@ static const struct dev_pm_ops tegra_dpaux_pm_ops = { | |||
| 639 | }; | 639 | }; |
| 640 | 640 | ||
| 641 | static const struct of_device_id tegra_dpaux_of_match[] = { | 641 | static const struct of_device_id tegra_dpaux_of_match[] = { |
| 642 | { .compatible = "nvidia,tegra194-dpaux", }, | ||
| 642 | { .compatible = "nvidia,tegra186-dpaux", }, | 643 | { .compatible = "nvidia,tegra186-dpaux", }, |
| 643 | { .compatible = "nvidia,tegra210-dpaux", }, | 644 | { .compatible = "nvidia,tegra210-dpaux", }, |
| 644 | { .compatible = "nvidia,tegra124-dpaux", }, | 645 | { .compatible = "nvidia,tegra124-dpaux", }, |
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 8cdb610561ba..65ea4988b332 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c | |||
| @@ -15,6 +15,10 @@ | |||
| 15 | #include <drm/drm_atomic.h> | 15 | #include <drm/drm_atomic.h> |
| 16 | #include <drm/drm_atomic_helper.h> | 16 | #include <drm/drm_atomic_helper.h> |
| 17 | 17 | ||
| 18 | #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) | ||
| 19 | #include <asm/dma-iommu.h> | ||
| 20 | #endif | ||
| 21 | |||
| 18 | #include "drm.h" | 22 | #include "drm.h" |
| 19 | #include "gem.h" | 23 | #include "gem.h" |
| 20 | 24 | ||
| @@ -1068,6 +1072,14 @@ struct iommu_group *host1x_client_iommu_attach(struct host1x_client *client, | |||
| 1068 | } | 1072 | } |
| 1069 | 1073 | ||
| 1070 | if (!shared || (shared && (group != tegra->group))) { | 1074 | if (!shared || (shared && (group != tegra->group))) { |
| 1075 | #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) | ||
| 1076 | if (client->dev->archdata.mapping) { | ||
| 1077 | struct dma_iommu_mapping *mapping = | ||
| 1078 | to_dma_iommu_mapping(client->dev); | ||
| 1079 | arm_iommu_detach_device(client->dev); | ||
| 1080 | arm_iommu_release_mapping(mapping); | ||
| 1081 | } | ||
| 1082 | #endif | ||
| 1071 | err = iommu_attach_group(tegra->domain, group); | 1083 | err = iommu_attach_group(tegra->domain, group); |
| 1072 | if (err < 0) { | 1084 | if (err < 0) { |
| 1073 | iommu_group_put(group); | 1085 | iommu_group_put(group); |
| @@ -1216,31 +1228,15 @@ static int host1x_drm_remove(struct host1x_device *dev) | |||
| 1216 | static int host1x_drm_suspend(struct device *dev) | 1228 | static int host1x_drm_suspend(struct device *dev) |
| 1217 | { | 1229 | { |
| 1218 | struct drm_device *drm = dev_get_drvdata(dev); | 1230 | struct drm_device *drm = dev_get_drvdata(dev); |
| 1219 | struct tegra_drm *tegra = drm->dev_private; | ||
| 1220 | |||
| 1221 | drm_kms_helper_poll_disable(drm); | ||
| 1222 | tegra_drm_fb_suspend(drm); | ||
| 1223 | 1231 | ||
| 1224 | tegra->state = drm_atomic_helper_suspend(drm); | 1232 | return drm_mode_config_helper_suspend(drm); |
| 1225 | if (IS_ERR(tegra->state)) { | ||
| 1226 | tegra_drm_fb_resume(drm); | ||
| 1227 | drm_kms_helper_poll_enable(drm); | ||
| 1228 | return PTR_ERR(tegra->state); | ||
| 1229 | } | ||
| 1230 | |||
| 1231 | return 0; | ||
| 1232 | } | 1233 | } |
| 1233 | 1234 | ||
| 1234 | static int host1x_drm_resume(struct device *dev) | 1235 | static int host1x_drm_resume(struct device *dev) |
| 1235 | { | 1236 | { |
| 1236 | struct drm_device *drm = dev_get_drvdata(dev); | 1237 | struct drm_device *drm = dev_get_drvdata(dev); |
| 1237 | struct tegra_drm *tegra = drm->dev_private; | ||
| 1238 | |||
| 1239 | drm_atomic_helper_resume(drm, tegra->state); | ||
| 1240 | tegra_drm_fb_resume(drm); | ||
| 1241 | drm_kms_helper_poll_enable(drm); | ||
| 1242 | 1238 | ||
| 1243 | return 0; | 1239 | return drm_mode_config_helper_resume(drm); |
| 1244 | } | 1240 | } |
| 1245 | #endif | 1241 | #endif |
| 1246 | 1242 | ||
| @@ -1275,6 +1271,9 @@ static const struct of_device_id host1x_drm_subdevs[] = { | |||
| 1275 | { .compatible = "nvidia,tegra186-sor", }, | 1271 | { .compatible = "nvidia,tegra186-sor", }, |
| 1276 | { .compatible = "nvidia,tegra186-sor1", }, | 1272 | { .compatible = "nvidia,tegra186-sor1", }, |
| 1277 | { .compatible = "nvidia,tegra186-vic", }, | 1273 | { .compatible = "nvidia,tegra186-vic", }, |
| 1274 | { .compatible = "nvidia,tegra194-display", }, | ||
| 1275 | { .compatible = "nvidia,tegra194-dc", }, | ||
| 1276 | { .compatible = "nvidia,tegra194-sor", }, | ||
| 1278 | { /* sentinel */ } | 1277 | { /* sentinel */ } |
| 1279 | }; | 1278 | }; |
| 1280 | 1279 | ||
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index 92d248784396..1012335bb489 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h | |||
| @@ -60,8 +60,6 @@ struct tegra_drm { | |||
| 60 | unsigned int pitch_align; | 60 | unsigned int pitch_align; |
| 61 | 61 | ||
| 62 | struct tegra_display_hub *hub; | 62 | struct tegra_display_hub *hub; |
| 63 | |||
| 64 | struct drm_atomic_state *state; | ||
| 65 | }; | 63 | }; |
| 66 | 64 | ||
| 67 | struct tegra_drm_client; | 65 | struct tegra_drm_client; |
| @@ -186,8 +184,6 @@ int tegra_drm_fb_prepare(struct drm_device *drm); | |||
| 186 | void tegra_drm_fb_free(struct drm_device *drm); | 184 | void tegra_drm_fb_free(struct drm_device *drm); |
| 187 | int tegra_drm_fb_init(struct drm_device *drm); | 185 | int tegra_drm_fb_init(struct drm_device *drm); |
| 188 | void tegra_drm_fb_exit(struct drm_device *drm); | 186 | void tegra_drm_fb_exit(struct drm_device *drm); |
| 189 | void tegra_drm_fb_suspend(struct drm_device *drm); | ||
| 190 | void tegra_drm_fb_resume(struct drm_device *drm); | ||
| 191 | 187 | ||
| 192 | extern struct platform_driver tegra_display_hub_driver; | 188 | extern struct platform_driver tegra_display_hub_driver; |
| 193 | extern struct platform_driver tegra_dc_driver; | 189 | extern struct platform_driver tegra_dc_driver; |
diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index 4c22cdded3c2..b947e82bbeb1 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c | |||
| @@ -356,7 +356,7 @@ static void tegra_fbdev_exit(struct tegra_fbdev *fbdev) | |||
| 356 | /* Undo the special mapping we made in fbdev probe. */ | 356 | /* Undo the special mapping we made in fbdev probe. */ |
| 357 | if (bo && bo->pages) { | 357 | if (bo && bo->pages) { |
| 358 | vunmap(bo->vaddr); | 358 | vunmap(bo->vaddr); |
| 359 | bo->vaddr = 0; | 359 | bo->vaddr = NULL; |
| 360 | } | 360 | } |
| 361 | 361 | ||
| 362 | drm_framebuffer_remove(fbdev->fb); | 362 | drm_framebuffer_remove(fbdev->fb); |
| @@ -412,25 +412,3 @@ void tegra_drm_fb_exit(struct drm_device *drm) | |||
| 412 | tegra_fbdev_exit(tegra->fbdev); | 412 | tegra_fbdev_exit(tegra->fbdev); |
| 413 | #endif | 413 | #endif |
| 414 | } | 414 | } |
| 415 | |||
| 416 | void tegra_drm_fb_suspend(struct drm_device *drm) | ||
| 417 | { | ||
| 418 | #ifdef CONFIG_DRM_FBDEV_EMULATION | ||
| 419 | struct tegra_drm *tegra = drm->dev_private; | ||
| 420 | |||
| 421 | console_lock(); | ||
| 422 | drm_fb_helper_set_suspend(&tegra->fbdev->base, 1); | ||
| 423 | console_unlock(); | ||
| 424 | #endif | ||
| 425 | } | ||
| 426 | |||
| 427 | void tegra_drm_fb_resume(struct drm_device *drm) | ||
| 428 | { | ||
| 429 | #ifdef CONFIG_DRM_FBDEV_EMULATION | ||
| 430 | struct tegra_drm *tegra = drm->dev_private; | ||
| 431 | |||
| 432 | console_lock(); | ||
| 433 | drm_fb_helper_set_suspend(&tegra->fbdev->base, 0); | ||
| 434 | console_unlock(); | ||
| 435 | #endif | ||
| 436 | } | ||
diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c index 8f4fcbb515fb..6112d9042979 100644 --- a/drivers/gpu/drm/tegra/hub.c +++ b/drivers/gpu/drm/tegra/hub.c | |||
| @@ -758,10 +758,12 @@ static int tegra_display_hub_probe(struct platform_device *pdev) | |||
| 758 | return err; | 758 | return err; |
| 759 | } | 759 | } |
| 760 | 760 | ||
| 761 | hub->clk_dsc = devm_clk_get(&pdev->dev, "dsc"); | 761 | if (hub->soc->supports_dsc) { |
| 762 | if (IS_ERR(hub->clk_dsc)) { | 762 | hub->clk_dsc = devm_clk_get(&pdev->dev, "dsc"); |
| 763 | err = PTR_ERR(hub->clk_dsc); | 763 | if (IS_ERR(hub->clk_dsc)) { |
| 764 | return err; | 764 | err = PTR_ERR(hub->clk_dsc); |
| 765 | return err; | ||
| 766 | } | ||
| 765 | } | 767 | } |
| 766 | 768 | ||
| 767 | hub->clk_hub = devm_clk_get(&pdev->dev, "hub"); | 769 | hub->clk_hub = devm_clk_get(&pdev->dev, "hub"); |
| @@ -890,10 +892,19 @@ static const struct dev_pm_ops tegra_display_hub_pm_ops = { | |||
| 890 | 892 | ||
| 891 | static const struct tegra_display_hub_soc tegra186_display_hub = { | 893 | static const struct tegra_display_hub_soc tegra186_display_hub = { |
| 892 | .num_wgrps = 6, | 894 | .num_wgrps = 6, |
| 895 | .supports_dsc = true, | ||
| 896 | }; | ||
| 897 | |||
| 898 | static const struct tegra_display_hub_soc tegra194_display_hub = { | ||
| 899 | .num_wgrps = 6, | ||
| 900 | .supports_dsc = false, | ||
| 893 | }; | 901 | }; |
| 894 | 902 | ||
| 895 | static const struct of_device_id tegra_display_hub_of_match[] = { | 903 | static const struct of_device_id tegra_display_hub_of_match[] = { |
| 896 | { | 904 | { |
| 905 | .compatible = "nvidia,tegra194-display", | ||
| 906 | .data = &tegra194_display_hub | ||
| 907 | }, { | ||
| 897 | .compatible = "nvidia,tegra186-display", | 908 | .compatible = "nvidia,tegra186-display", |
| 898 | .data = &tegra186_display_hub | 909 | .data = &tegra186_display_hub |
| 899 | }, { | 910 | }, { |
diff --git a/drivers/gpu/drm/tegra/hub.h b/drivers/gpu/drm/tegra/hub.h index 85b8bf41a395..6696a85fc1f2 100644 --- a/drivers/gpu/drm/tegra/hub.h +++ b/drivers/gpu/drm/tegra/hub.h | |||
| @@ -38,6 +38,7 @@ to_tegra_shared_plane(struct drm_plane *plane) | |||
| 38 | 38 | ||
| 39 | struct tegra_display_hub_soc { | 39 | struct tegra_display_hub_soc { |
| 40 | unsigned int num_wgrps; | 40 | unsigned int num_wgrps; |
| 41 | bool supports_dsc; | ||
| 41 | }; | 42 | }; |
| 42 | 43 | ||
| 43 | struct tegra_display_hub { | 44 | struct tegra_display_hub { |
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index d7fe9f15def1..b129da2e5afd 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c | |||
| @@ -282,6 +282,85 @@ static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = { | |||
| 282 | } | 282 | } |
| 283 | }; | 283 | }; |
| 284 | 284 | ||
| 285 | static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = { | ||
| 286 | { | ||
| 287 | .frequency = 54000000, | ||
| 288 | .vcocap = 0, | ||
| 289 | .filter = 5, | ||
| 290 | .ichpmp = 5, | ||
| 291 | .loadadj = 3, | ||
| 292 | .tmds_termadj = 0xf, | ||
| 293 | .tx_pu_value = 0, | ||
| 294 | .bg_temp_coef = 3, | ||
| 295 | .bg_vref_level = 8, | ||
| 296 | .avdd10_level = 4, | ||
| 297 | .avdd14_level = 4, | ||
| 298 | .sparepll = 0x54, | ||
| 299 | .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, | ||
| 300 | .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, | ||
| 301 | }, { | ||
| 302 | .frequency = 75000000, | ||
| 303 | .vcocap = 1, | ||
| 304 | .filter = 5, | ||
| 305 | .ichpmp = 5, | ||
| 306 | .loadadj = 3, | ||
| 307 | .tmds_termadj = 0xf, | ||
| 308 | .tx_pu_value = 0, | ||
| 309 | .bg_temp_coef = 3, | ||
| 310 | .bg_vref_level = 8, | ||
| 311 | .avdd10_level = 4, | ||
| 312 | .avdd14_level = 4, | ||
| 313 | .sparepll = 0x44, | ||
| 314 | .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, | ||
| 315 | .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, | ||
| 316 | }, { | ||
| 317 | .frequency = 150000000, | ||
| 318 | .vcocap = 3, | ||
| 319 | .filter = 5, | ||
| 320 | .ichpmp = 5, | ||
| 321 | .loadadj = 3, | ||
| 322 | .tmds_termadj = 15, | ||
| 323 | .tx_pu_value = 0x66 /* 0 */, | ||
| 324 | .bg_temp_coef = 3, | ||
| 325 | .bg_vref_level = 8, | ||
| 326 | .avdd10_level = 4, | ||
| 327 | .avdd14_level = 4, | ||
| 328 | .sparepll = 0x00, /* 0x34 */ | ||
| 329 | .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, | ||
| 330 | .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, | ||
| 331 | }, { | ||
| 332 | .frequency = 300000000, | ||
| 333 | .vcocap = 3, | ||
| 334 | .filter = 5, | ||
| 335 | .ichpmp = 5, | ||
| 336 | .loadadj = 3, | ||
| 337 | .tmds_termadj = 15, | ||
| 338 | .tx_pu_value = 64, | ||
| 339 | .bg_temp_coef = 3, | ||
| 340 | .bg_vref_level = 8, | ||
| 341 | .avdd10_level = 4, | ||
| 342 | .avdd14_level = 4, | ||
| 343 | .sparepll = 0x34, | ||
| 344 | .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, | ||
| 345 | .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, | ||
| 346 | }, { | ||
| 347 | .frequency = 600000000, | ||
| 348 | .vcocap = 3, | ||
| 349 | .filter = 5, | ||
| 350 | .ichpmp = 5, | ||
| 351 | .loadadj = 3, | ||
| 352 | .tmds_termadj = 12, | ||
| 353 | .tx_pu_value = 96, | ||
| 354 | .bg_temp_coef = 3, | ||
| 355 | .bg_vref_level = 8, | ||
| 356 | .avdd10_level = 4, | ||
| 357 | .avdd14_level = 4, | ||
| 358 | .sparepll = 0x34, | ||
| 359 | .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, | ||
| 360 | .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, | ||
| 361 | } | ||
| 362 | }; | ||
| 363 | |||
| 285 | struct tegra_sor_regs { | 364 | struct tegra_sor_regs { |
| 286 | unsigned int head_state0; | 365 | unsigned int head_state0; |
| 287 | unsigned int head_state1; | 366 | unsigned int head_state1; |
| @@ -2894,7 +2973,38 @@ static const struct tegra_sor_soc tegra186_sor1 = { | |||
| 2894 | .xbar_cfg = tegra124_sor_xbar_cfg, | 2973 | .xbar_cfg = tegra124_sor_xbar_cfg, |
| 2895 | }; | 2974 | }; |
| 2896 | 2975 | ||
| 2976 | static const struct tegra_sor_regs tegra194_sor_regs = { | ||
| 2977 | .head_state0 = 0x151, | ||
| 2978 | .head_state1 = 0x155, | ||
| 2979 | .head_state2 = 0x159, | ||
| 2980 | .head_state3 = 0x15d, | ||
| 2981 | .head_state4 = 0x161, | ||
| 2982 | .head_state5 = 0x165, | ||
| 2983 | .pll0 = 0x169, | ||
| 2984 | .pll1 = 0x16a, | ||
| 2985 | .pll2 = 0x16b, | ||
| 2986 | .pll3 = 0x16c, | ||
| 2987 | .dp_padctl0 = 0x16e, | ||
| 2988 | .dp_padctl2 = 0x16f, | ||
| 2989 | }; | ||
| 2990 | |||
| 2991 | static const struct tegra_sor_soc tegra194_sor = { | ||
| 2992 | .supports_edp = true, | ||
| 2993 | .supports_lvds = false, | ||
| 2994 | .supports_hdmi = true, | ||
| 2995 | .supports_dp = true, | ||
| 2996 | |||
| 2997 | .regs = &tegra194_sor_regs, | ||
| 2998 | .has_nvdisplay = true, | ||
| 2999 | |||
| 3000 | .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults), | ||
| 3001 | .settings = tegra194_sor_hdmi_defaults, | ||
| 3002 | |||
| 3003 | .xbar_cfg = tegra210_sor_xbar_cfg, | ||
| 3004 | }; | ||
| 3005 | |||
| 2897 | static const struct of_device_id tegra_sor_of_match[] = { | 3006 | static const struct of_device_id tegra_sor_of_match[] = { |
| 3007 | { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor }, | ||
| 2898 | { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 }, | 3008 | { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 }, |
| 2899 | { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor }, | 3009 | { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor }, |
| 2900 | { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, | 3010 | { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, |
diff --git a/drivers/gpu/host1x/bus.c b/drivers/gpu/host1x/bus.c index 815bdb42e3f0..b4c385d4a6af 100644 --- a/drivers/gpu/host1x/bus.c +++ b/drivers/gpu/host1x/bus.c | |||
| @@ -331,7 +331,7 @@ static const struct dev_pm_ops host1x_device_pm_ops = { | |||
| 331 | struct bus_type host1x_bus_type = { | 331 | struct bus_type host1x_bus_type = { |
| 332 | .name = "host1x", | 332 | .name = "host1x", |
| 333 | .match = host1x_device_match, | 333 | .match = host1x_device_match, |
| 334 | .dma_configure = host1x_dma_configure, | 334 | .dma_configure = host1x_dma_configure, |
| 335 | .pm = &host1x_device_pm_ops, | 335 | .pm = &host1x_device_pm_ops, |
| 336 | }; | 336 | }; |
| 337 | 337 | ||
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c index d88073e7d22d..de6bc4e7fa23 100644 --- a/drivers/gpu/host1x/dev.c +++ b/drivers/gpu/host1x/dev.c | |||
| @@ -29,6 +29,10 @@ | |||
| 29 | #include <trace/events/host1x.h> | 29 | #include <trace/events/host1x.h> |
| 30 | #undef CREATE_TRACE_POINTS | 30 | #undef CREATE_TRACE_POINTS |
| 31 | 31 | ||
| 32 | #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) | ||
| 33 | #include <asm/dma-iommu.h> | ||
| 34 | #endif | ||
| 35 | |||
| 32 | #include "bus.h" | 36 | #include "bus.h" |
| 33 | #include "channel.h" | 37 | #include "channel.h" |
| 34 | #include "debug.h" | 38 | #include "debug.h" |
| @@ -217,7 +221,14 @@ static int host1x_probe(struct platform_device *pdev) | |||
| 217 | dev_err(&pdev->dev, "failed to get reset: %d\n", err); | 221 | dev_err(&pdev->dev, "failed to get reset: %d\n", err); |
| 218 | return err; | 222 | return err; |
| 219 | } | 223 | } |
| 220 | 224 | #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) | |
| 225 | if (host->dev->archdata.mapping) { | ||
| 226 | struct dma_iommu_mapping *mapping = | ||
| 227 | to_dma_iommu_mapping(host->dev); | ||
| 228 | arm_iommu_detach_device(host->dev); | ||
| 229 | arm_iommu_release_mapping(mapping); | ||
| 230 | } | ||
| 231 | #endif | ||
| 221 | if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL)) | 232 | if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL)) |
| 222 | goto skip_iommu; | 233 | goto skip_iommu; |
| 223 | 234 | ||
