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-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c6
3 files changed, 13 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 992f00b65be4..01c36b8d6222 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -799,6 +799,7 @@ struct amdgpu_ring {
799 unsigned cond_exe_offs; 799 unsigned cond_exe_offs;
800 u64 cond_exe_gpu_addr; 800 u64 cond_exe_gpu_addr;
801 volatile u32 *cond_exe_cpu_addr; 801 volatile u32 *cond_exe_cpu_addr;
802 int vmid;
802}; 803};
803 804
804/* 805/*
@@ -936,7 +937,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
936 unsigned vm_id, uint64_t pd_addr, 937 unsigned vm_id, uint64_t pd_addr,
937 uint32_t gds_base, uint32_t gds_size, 938 uint32_t gds_base, uint32_t gds_size,
938 uint32_t gws_base, uint32_t gws_size, 939 uint32_t gws_base, uint32_t gws_size,
939 uint32_t oa_base, uint32_t oa_size); 940 uint32_t oa_base, uint32_t oa_size,
941 bool vmid_switch);
940void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); 942void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
941uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 943uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
942int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 944int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 34e35423b78e..7a0b1e50f293 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -122,6 +122,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
122 bool skip_preamble, need_ctx_switch; 122 bool skip_preamble, need_ctx_switch;
123 unsigned patch_offset = ~0; 123 unsigned patch_offset = ~0;
124 struct amdgpu_vm *vm; 124 struct amdgpu_vm *vm;
125 int vmid = 0, old_vmid = ring->vmid;
125 struct fence *hwf; 126 struct fence *hwf;
126 uint64_t ctx; 127 uint64_t ctx;
127 128
@@ -135,9 +136,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
135 if (job) { 136 if (job) {
136 vm = job->vm; 137 vm = job->vm;
137 ctx = job->ctx; 138 ctx = job->ctx;
139 vmid = job->vm_id;
138 } else { 140 } else {
139 vm = NULL; 141 vm = NULL;
140 ctx = 0; 142 ctx = 0;
143 vmid = 0;
141 } 144 }
142 145
143 if (!ring->ready) { 146 if (!ring->ready) {
@@ -163,7 +166,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
163 r = amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr, 166 r = amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr,
164 job->gds_base, job->gds_size, 167 job->gds_base, job->gds_size,
165 job->gws_base, job->gws_size, 168 job->gws_base, job->gws_size,
166 job->oa_base, job->oa_size); 169 job->oa_base, job->oa_size,
170 (ring->current_ctx == ctx) && (old_vmid != vmid));
167 if (r) { 171 if (r) {
168 amdgpu_ring_undo(ring); 172 amdgpu_ring_undo(ring);
169 return r; 173 return r;
@@ -180,7 +184,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
180 need_ctx_switch = ring->current_ctx != ctx; 184 need_ctx_switch = ring->current_ctx != ctx;
181 for (i = 0; i < num_ibs; ++i) { 185 for (i = 0; i < num_ibs; ++i) {
182 ib = &ibs[i]; 186 ib = &ibs[i];
183
184 /* drop preamble IBs if we don't have a context switch */ 187 /* drop preamble IBs if we don't have a context switch */
185 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble) 188 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble)
186 continue; 189 continue;
@@ -188,6 +191,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
188 amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0, 191 amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,
189 need_ctx_switch); 192 need_ctx_switch);
190 need_ctx_switch = false; 193 need_ctx_switch = false;
194 ring->vmid = vmid;
191 } 195 }
192 196
193 if (ring->funcs->emit_hdp_invalidate) 197 if (ring->funcs->emit_hdp_invalidate)
@@ -198,6 +202,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
198 dev_err(adev->dev, "failed to emit fence (%d)\n", r); 202 dev_err(adev->dev, "failed to emit fence (%d)\n", r);
199 if (job && job->vm_id) 203 if (job && job->vm_id)
200 amdgpu_vm_reset_id(adev, job->vm_id); 204 amdgpu_vm_reset_id(adev, job->vm_id);
205 ring->vmid = old_vmid;
201 amdgpu_ring_undo(ring); 206 amdgpu_ring_undo(ring);
202 return r; 207 return r;
203 } 208 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 9f36ed30ba11..62a4c127620f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -298,7 +298,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
298 unsigned vm_id, uint64_t pd_addr, 298 unsigned vm_id, uint64_t pd_addr,
299 uint32_t gds_base, uint32_t gds_size, 299 uint32_t gds_base, uint32_t gds_size,
300 uint32_t gws_base, uint32_t gws_size, 300 uint32_t gws_base, uint32_t gws_size,
301 uint32_t oa_base, uint32_t oa_size) 301 uint32_t oa_base, uint32_t oa_size,
302 bool vmid_switch)
302{ 303{
303 struct amdgpu_device *adev = ring->adev; 304 struct amdgpu_device *adev = ring->adev;
304 struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; 305 struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
@@ -312,8 +313,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
312 int r; 313 int r;
313 314
314 if (ring->funcs->emit_pipeline_sync && ( 315 if (ring->funcs->emit_pipeline_sync && (
315 pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed || 316 pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed || vmid_switch))
316 ring->type == AMDGPU_RING_TYPE_COMPUTE))
317 amdgpu_ring_emit_pipeline_sync(ring); 317 amdgpu_ring_emit_pipeline_sync(ring);
318 318
319 if (ring->funcs->emit_vm_flush && 319 if (ring->funcs->emit_vm_flush &&