diff options
| -rw-r--r-- | drivers/clk/ti/clk-7xx-compat.c | 2 | ||||
| -rw-r--r-- | drivers/clk/ti/clk-7xx.c | 2 | ||||
| -rw-r--r-- | drivers/clk/ti/clkctrl.c | 14 | ||||
| -rw-r--r-- | drivers/clk/ti/clock.h | 6 |
4 files changed, 22 insertions, 2 deletions
diff --git a/drivers/clk/ti/clk-7xx-compat.c b/drivers/clk/ti/clk-7xx-compat.c index e3cb7f0b03ae..0d53bd0998ba 100644 --- a/drivers/clk/ti/clk-7xx-compat.c +++ b/drivers/clk/ti/clk-7xx-compat.c | |||
| @@ -362,7 +362,7 @@ static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst | |||
| 362 | { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" }, | 362 | { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" }, |
| 363 | { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, | 363 | { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, |
| 364 | { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, | 364 | { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, |
| 365 | { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, | 365 | { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" }, |
| 366 | { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, | 366 | { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, |
| 367 | { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" }, | 367 | { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" }, |
| 368 | { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" }, | 368 | { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" }, |
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 597fb4a59318..098c342d9c36 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c | |||
| @@ -348,7 +348,7 @@ static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst | |||
| 348 | { DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" }, | 348 | { DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" }, |
| 349 | { DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, | 349 | { DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, |
| 350 | { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, | 350 | { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, |
| 351 | { DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, | 351 | { DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" }, |
| 352 | { DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, | 352 | { DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, |
| 353 | { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, | 353 | { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, |
| 354 | { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, | 354 | { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, |
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index 639f515e08f0..4cdeb8d4830c 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c | |||
| @@ -446,6 +446,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) | |||
| 446 | u32 addr; | 446 | u32 addr; |
| 447 | int ret; | 447 | int ret; |
| 448 | char *c; | 448 | char *c; |
| 449 | u16 soc_mask = 0; | ||
| 449 | 450 | ||
| 450 | if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) && | 451 | if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) && |
| 451 | of_node_name_eq(node, "clk")) | 452 | of_node_name_eq(node, "clk")) |
| @@ -469,6 +470,13 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) | |||
| 469 | else | 470 | else |
| 470 | data = dra7_clkctrl_data; | 471 | data = dra7_clkctrl_data; |
| 471 | } | 472 | } |
| 473 | |||
| 474 | if (of_machine_is_compatible("ti,dra72")) | ||
| 475 | soc_mask = CLKF_SOC_DRA72; | ||
| 476 | if (of_machine_is_compatible("ti,dra74")) | ||
| 477 | soc_mask = CLKF_SOC_DRA74; | ||
| 478 | if (of_machine_is_compatible("ti,dra76")) | ||
| 479 | soc_mask = CLKF_SOC_DRA76; | ||
| 472 | #endif | 480 | #endif |
| 473 | #ifdef CONFIG_SOC_AM33XX | 481 | #ifdef CONFIG_SOC_AM33XX |
| 474 | if (of_machine_is_compatible("ti,am33xx")) { | 482 | if (of_machine_is_compatible("ti,am33xx")) { |
| @@ -562,6 +570,12 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) | |||
| 562 | reg_data = data->regs; | 570 | reg_data = data->regs; |
| 563 | 571 | ||
| 564 | while (reg_data->parent) { | 572 | while (reg_data->parent) { |
| 573 | if ((reg_data->flags & CLKF_SOC_MASK) && | ||
| 574 | (reg_data->flags & soc_mask) == 0) { | ||
| 575 | reg_data++; | ||
| 576 | continue; | ||
| 577 | } | ||
| 578 | |||
| 565 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); | 579 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); |
| 566 | if (!hw) | 580 | if (!hw) |
| 567 | return; | 581 | return; |
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 4223a399b317..773e2c4ac390 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h | |||
| @@ -83,6 +83,12 @@ enum { | |||
| 83 | #define CLKF_HW_SUP BIT(6) | 83 | #define CLKF_HW_SUP BIT(6) |
| 84 | #define CLKF_NO_IDLEST BIT(7) | 84 | #define CLKF_NO_IDLEST BIT(7) |
| 85 | 85 | ||
| 86 | #define CLKF_SOC_MASK GENMASK(10, 8) | ||
| 87 | |||
| 88 | #define CLKF_SOC_DRA72 BIT(8) | ||
| 89 | #define CLKF_SOC_DRA74 BIT(9) | ||
| 90 | #define CLKF_SOC_DRA76 BIT(10) | ||
| 91 | |||
| 86 | #define CLK(dev, con, ck) \ | 92 | #define CLK(dev, con, ck) \ |
| 87 | { \ | 93 | { \ |
| 88 | .lk = { \ | 94 | .lk = { \ |
