diff options
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/dsi.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/dsi_phy.c | 16 |
2 files changed, 6 insertions, 12 deletions
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 09492bfc0e02..5f5a3732cdf6 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h | |||
| @@ -168,7 +168,7 @@ void msm_dsi_phy_driver_register(void); | |||
| 168 | void msm_dsi_phy_driver_unregister(void); | 168 | void msm_dsi_phy_driver_unregister(void); |
| 169 | int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, | 169 | int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, |
| 170 | const unsigned long bit_rate, const unsigned long esc_rate); | 170 | const unsigned long bit_rate, const unsigned long esc_rate); |
| 171 | int msm_dsi_phy_disable(struct msm_dsi_phy *phy); | 171 | void msm_dsi_phy_disable(struct msm_dsi_phy *phy); |
| 172 | void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy, | 172 | void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy, |
| 173 | u32 *clk_pre, u32 *clk_post); | 173 | u32 *clk_pre, u32 *clk_post); |
| 174 | struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy); | 174 | struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy); |
diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy.c b/drivers/gpu/drm/msm/dsi/dsi_phy.c index 799201e1a14f..77f1efe4e013 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/dsi_phy.c | |||
| @@ -23,7 +23,7 @@ | |||
| 23 | struct dsi_phy_ops { | 23 | struct dsi_phy_ops { |
| 24 | int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, | 24 | int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, |
| 25 | const unsigned long bit_rate, const unsigned long esc_rate); | 25 | const unsigned long bit_rate, const unsigned long esc_rate); |
| 26 | int (*disable)(struct msm_dsi_phy *phy); | 26 | void (*disable)(struct msm_dsi_phy *phy); |
| 27 | }; | 27 | }; |
| 28 | 28 | ||
| 29 | struct dsi_phy_cfg { | 29 | struct dsi_phy_cfg { |
| @@ -399,7 +399,7 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, | |||
| 399 | return 0; | 399 | return 0; |
| 400 | } | 400 | } |
| 401 | 401 | ||
| 402 | static int dsi_28nm_phy_disable(struct msm_dsi_phy *phy) | 402 | static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy) |
| 403 | { | 403 | { |
| 404 | dsi_phy_write(phy->base + REG_DSI_28nm_PHY_CTRL_0, 0); | 404 | dsi_phy_write(phy->base + REG_DSI_28nm_PHY_CTRL_0, 0); |
| 405 | dsi_28nm_phy_regulator_ctrl(phy, false); | 405 | dsi_28nm_phy_regulator_ctrl(phy, false); |
| @@ -409,8 +409,6 @@ static int dsi_28nm_phy_disable(struct msm_dsi_phy *phy) | |||
| 409 | * ensure that the phy is completely disabled | 409 | * ensure that the phy is completely disabled |
| 410 | */ | 410 | */ |
| 411 | wmb(); | 411 | wmb(); |
| 412 | |||
| 413 | return 0; | ||
| 414 | } | 412 | } |
| 415 | 413 | ||
| 416 | static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) | 414 | static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) |
| @@ -515,12 +513,10 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, | |||
| 515 | return 0; | 513 | return 0; |
| 516 | } | 514 | } |
| 517 | 515 | ||
| 518 | static int dsi_20nm_phy_disable(struct msm_dsi_phy *phy) | 516 | static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy) |
| 519 | { | 517 | { |
| 520 | dsi_phy_write(phy->base + REG_DSI_20nm_PHY_CTRL_0, 0); | 518 | dsi_phy_write(phy->base + REG_DSI_20nm_PHY_CTRL_0, 0); |
| 521 | dsi_20nm_phy_regulator_ctrl(phy, false); | 519 | dsi_20nm_phy_regulator_ctrl(phy, false); |
| 522 | |||
| 523 | return 0; | ||
| 524 | } | 520 | } |
| 525 | 521 | ||
| 526 | static int dsi_phy_enable_resource(struct msm_dsi_phy *phy) | 522 | static int dsi_phy_enable_resource(struct msm_dsi_phy *phy) |
| @@ -730,15 +726,13 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, | |||
| 730 | return phy->cfg->ops.enable(phy, src_pll_id, bit_rate, esc_rate); | 726 | return phy->cfg->ops.enable(phy, src_pll_id, bit_rate, esc_rate); |
| 731 | } | 727 | } |
| 732 | 728 | ||
| 733 | int msm_dsi_phy_disable(struct msm_dsi_phy *phy) | 729 | void msm_dsi_phy_disable(struct msm_dsi_phy *phy) |
| 734 | { | 730 | { |
| 735 | if (!phy || !phy->cfg->ops.disable) | 731 | if (!phy || !phy->cfg->ops.disable) |
| 736 | return -EINVAL; | 732 | return; |
| 737 | 733 | ||
| 738 | phy->cfg->ops.disable(phy); | 734 | phy->cfg->ops.disable(phy); |
| 739 | dsi_phy_regulator_disable(phy); | 735 | dsi_phy_regulator_disable(phy); |
| 740 | |||
| 741 | return 0; | ||
| 742 | } | 736 | } |
| 743 | 737 | ||
| 744 | void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy, | 738 | void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy, |
