6 files changed, 57 insertions, 35 deletions

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 43c4ea9cd907..4e7772387c6e 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -100,7 +100,7 @@
 #define X86_FEATURE_XTOPOLOGY   ( 3*32+22) /* cpu topology enum extensions */
 #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
 #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
-/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
+#define X86_FEATURE_CPUID       ( 3*32+25) /* CPU has CPUID instruction itself */
 #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
 #define X86_FEATURE_AMD_DCM     ( 3*32+27) /* multi-node processor */
 #define X86_FEATURE_APERFMPERF  ( 3*32+28) /* APERFMPERF */
diff --git a/arch/x86/include/asm/fpu/internal.h b/arch/x86/include/asm/fpu/internal.h
index d4a684997497..255645f60ca2 100644
--- a/arch/x86/include/asm/fpu/internal.h
+++ b/arch/x86/include/asm/fpu/internal.h
@@ -87,6 +87,16 @@ extern void fpstate_init_soft(struct swregs_state *soft);
 #else
 static inline void fpstate_init_soft(struct swregs_state *soft) {}
 #endif
+
+static inline void fpstate_init_xstate(struct xregs_state *xsave)
+{
+        /*
+         * XRSTORS requires these bits set in xcomp_bv, or it will
+         * trigger #GP:
+         */
+        xsave->header.xcomp_bv = XCOMP_BV_COMPACTED_FORMAT | xfeatures_mask;
+}
+
 static inline void fpstate_init_fxstate(struct fxregs_state *fx)
 {
         fx->cwd = 0x37f;
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 5200adcaaac3..f07005e6f461 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -659,6 +659,16 @@ void cpu_detect(struct cpuinfo_x86 *c)
         }
 }
 
+static void apply_forced_caps(struct cpuinfo_x86 *c)
+{
+        int i;
+
+        for (i = 0; i < NCAPINTS; i++) {
+                c->x86_capability[i] &= ~cpu_caps_cleared[i];
+                c->x86_capability[i] |= cpu_caps_set[i];
+        }
+}
+
 void get_cpu_cap(struct cpuinfo_x86 *c)
 {
         u32 eax, ebx, ecx, edx;
@@ -752,6 +762,13 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
                 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
 
         init_scattered_cpuid_features(c);
+
+        /*
+         * Clear/Set all flags overridden by options, after probe.
+         * This needs to happen each time we re-probe, which may happen
+         * several times during CPU initialization.
+         */
+        apply_forced_caps(c);
 }
 
 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
@@ -805,14 +822,12 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
         memset(&c->x86_capability, 0, sizeof c->x86_capability);
         c->extended_cpuid_level = 0;
 
-        if (!have_cpuid_p())
-                identify_cpu_without_cpuid(c);
-
         /* cyrix could have cpuid enabled via c_identify()*/
         if (have_cpuid_p()) {
                 cpu_detect(c);
                 get_cpu_vendor(c);
                 get_cpu_cap(c);
+                setup_force_cpu_cap(X86_FEATURE_CPUID);
 
                 if (this_cpu->c_early_init)
                         this_cpu->c_early_init(c);
@@ -822,6 +837,9 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
 
                 if (this_cpu->c_bsp_init)
                         this_cpu->c_bsp_init(c);
+        } else {
+                identify_cpu_without_cpuid(c);
+                setup_clear_cpu_cap(X86_FEATURE_CPUID);
         }
 
         setup_force_cpu_cap(X86_FEATURE_ALWAYS);
@@ -1039,10 +1057,7 @@ static void identify_cpu(struct cpuinfo_x86 *c)
                 this_cpu->c_identify(c);
 
         /* Clear/Set all flags overridden by options, after probe */
-        for (i = 0; i < NCAPINTS; i++) {
-                c->x86_capability[i] &= ~cpu_caps_cleared[i];
-                c->x86_capability[i] |= cpu_caps_set[i];
-        }
+        apply_forced_caps(c);
 
 #ifdef CONFIG_X86_64
         c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
@@ -1103,10 +1118,7 @@ static void identify_cpu(struct cpuinfo_x86 *c)
          * Clear/Set all flags overridden by options, need do it
          * before following smp all cpus cap AND.
          */
-        for (i = 0; i < NCAPINTS; i++) {
-                c->x86_capability[i] &= ~cpu_caps_cleared[i];
-                c->x86_capability[i] |= cpu_caps_set[i];
-        }
+        apply_forced_caps(c);
 
         /*
          * On SMP, boot_cpu_data holds the common feature set between
diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c
index de7234401275..e1114f070c2d 100644
--- a/arch/x86/kernel/fpu/core.c
+++ b/arch/x86/kernel/fpu/core.c
@@ -9,7 +9,6 @@
 #include <asm/fpu/regset.h>
 #include <asm/fpu/signal.h>
 #include <asm/fpu/types.h>
-#include <asm/fpu/xstate.h>
 #include <asm/traps.h>
 
 #include <linux/hardirq.h>
@@ -179,14 +178,8 @@ void fpstate_init(union fpregs_state *state)
 
         memset(state, 0, fpu_kernel_xstate_size);
 
-        /*
-         * XRSTORS requires that this bit is set in xcomp_bv, or
-         * it will #GP. Make sure it is replaced after the memset().
-         */
         if (static_cpu_has(X86_FEATURE_XSAVES))
-                state->xsave.header.xcomp_bv = XCOMP_BV_COMPACTED_FORMAT |
-                                               xfeatures_mask;
-
+                fpstate_init_xstate(&state->xsave);
         if (static_cpu_has(X86_FEATURE_FXSR))
                 fpstate_init_fxstate(&state->fxsave);
         else
diff --git a/arch/x86/kernel/fpu/init.c b/arch/x86/kernel/fpu/init.c
index 60dece392b3a..19bdd1bf8160 100644
--- a/arch/x86/kernel/fpu/init.c
+++ b/arch/x86/kernel/fpu/init.c
@@ -48,13 +48,7 @@ void fpu__init_cpu(void)
         fpu__init_cpu_xstate();
 }
 
-/*
- * The earliest FPU detection code.
- *
- * Set the X86_FEATURE_FPU CPU-capability bit based on
- * trying to execute an actual sequence of FPU instructions:
- */
-static void fpu__init_system_early_generic(struct cpuinfo_x86 *c)
+static bool fpu__probe_without_cpuid(void)
 {
         unsigned long cr0;
         u16 fsw, fcw;
@@ -65,18 +59,25 @@ static void fpu__init_system_early_generic(struct cpuinfo_x86 *c)
         cr0 &= ~(X86_CR0_TS | X86_CR0_EM);
         write_cr0(cr0);
 
-        if (!test_bit(X86_FEATURE_FPU, (unsigned long *)cpu_caps_cleared)) {
-                asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
-                             : "+m" (fsw), "+m" (fcw));
+        asm volatile("fninit ; fnstsw %0 ; fnstcw %1" : "+m" (fsw), "+m" (fcw));
+
+        pr_info("x86/fpu: Probing for FPU: FSW=0x%04hx FCW=0x%04hx\n", fsw, fcw);
 
-                if (fsw == 0 && (fcw & 0x103f) == 0x003f)
-                        set_cpu_cap(c, X86_FEATURE_FPU);
+        return fsw == 0 && (fcw & 0x103f) == 0x003f;
+}
+
+static void fpu__init_system_early_generic(struct cpuinfo_x86 *c)
+{
+        if (!boot_cpu_has(X86_FEATURE_CPUID) &&
+            !test_bit(X86_FEATURE_FPU, (unsigned long *)cpu_caps_cleared)) {
+                if (fpu__probe_without_cpuid())
+                        setup_force_cpu_cap(X86_FEATURE_FPU);
                 else
-                        clear_cpu_cap(c, X86_FEATURE_FPU);
+                        setup_clear_cpu_cap(X86_FEATURE_FPU);
         }
 
 #ifndef CONFIG_MATH_EMULATION
-        if (!boot_cpu_has(X86_FEATURE_FPU)) {
+        if (!test_cpu_cap(&boot_cpu_data, X86_FEATURE_FPU)) {
                 pr_emerg("x86/fpu: Giving up, no FPU found and no math emulation present\n");
                 for (;;)
                         asm volatile("hlt");
diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
index 35f7024aace5..c24ac1efb12d 100644
--- a/arch/x86/kernel/fpu/xstate.c
+++ b/arch/x86/kernel/fpu/xstate.c
@@ -706,8 +706,14 @@ void __init fpu__init_system_xstate(void)
         WARN_ON_FPU(!on_boot_cpu);
         on_boot_cpu = 0;
 
+        if (!boot_cpu_has(X86_FEATURE_FPU)) {
+                pr_info("x86/fpu: No FPU detected\n");
+                return;
+        }
+
         if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
-                pr_info("x86/fpu: Legacy x87 FPU detected.\n");
+                pr_info("x86/fpu: x87 FPU will use %s\n",
+                        boot_cpu_has(X86_FEATURE_FXSR) ? "FXSAVE" : "FSAVE");
                 return;
         }