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-rw-r--r--drivers/gpu/drm/msm/dsi/phy/dsi_phy.c33
-rw-r--r--drivers/gpu/drm/msm/dsi/phy/dsi_phy.h2
-rw-r--r--drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c1
-rw-r--r--drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c2
-rw-r--r--drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c1
5 files changed, 30 insertions, 9 deletions
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index f39386ed75e4..03a354933606 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -295,6 +295,24 @@ static int dsi_phy_get_id(struct msm_dsi_phy *phy)
295 return -EINVAL; 295 return -EINVAL;
296} 296}
297 297
298int msm_dsi_phy_init_common(struct msm_dsi_phy *phy)
299{
300 struct platform_device *pdev = phy->pdev;
301 int ret = 0;
302
303 phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
304 "DSI_PHY_REG");
305 if (IS_ERR(phy->reg_base)) {
306 dev_err(&pdev->dev, "%s: failed to map phy regulator base\n",
307 __func__);
308 ret = -ENOMEM;
309 goto fail;
310 }
311
312fail:
313 return ret;
314}
315
298static int dsi_phy_driver_probe(struct platform_device *pdev) 316static int dsi_phy_driver_probe(struct platform_device *pdev)
299{ 317{
300 struct msm_dsi_phy *phy; 318 struct msm_dsi_phy *phy;
@@ -331,15 +349,6 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
331 goto fail; 349 goto fail;
332 } 350 }
333 351
334 phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
335 "DSI_PHY_REG");
336 if (IS_ERR(phy->reg_base)) {
337 dev_err(dev, "%s: failed to map phy regulator base\n",
338 __func__);
339 ret = -ENOMEM;
340 goto fail;
341 }
342
343 ret = dsi_phy_regulator_init(phy); 352 ret = dsi_phy_regulator_init(phy);
344 if (ret) { 353 if (ret) {
345 dev_err(dev, "%s: failed to init regulator\n", __func__); 354 dev_err(dev, "%s: failed to init regulator\n", __func__);
@@ -353,6 +362,12 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
353 goto fail; 362 goto fail;
354 } 363 }
355 364
365 if (phy->cfg->ops.init) {
366 ret = phy->cfg->ops.init(phy);
367 if (ret)
368 goto fail;
369 }
370
356 /* PLL init will call into clk_register which requires 371 /* PLL init will call into clk_register which requires
357 * register access, so we need to enable power and ahb clock. 372 * register access, so we need to enable power and ahb clock.
358 */ 373 */
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index f24a85439b94..b9d7d02260da 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -22,6 +22,7 @@
22#define dsi_phy_write(offset, data) msm_writel((data), (offset)) 22#define dsi_phy_write(offset, data) msm_writel((data), (offset))
23 23
24struct msm_dsi_phy_ops { 24struct msm_dsi_phy_ops {
25 int (*init) (struct msm_dsi_phy *phy);
25 int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, 26 int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
26 const unsigned long bit_rate, const unsigned long esc_rate); 27 const unsigned long bit_rate, const unsigned long esc_rate);
27 void (*disable)(struct msm_dsi_phy *phy); 28 void (*disable)(struct msm_dsi_phy *phy);
@@ -87,6 +88,7 @@ int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
87 const unsigned long bit_rate, const unsigned long esc_rate); 88 const unsigned long bit_rate, const unsigned long esc_rate);
88void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, 89void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
89 u32 bit_mask); 90 u32 bit_mask);
91int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);
90 92
91#endif /* __DSI_PHY_H__ */ 93#endif /* __DSI_PHY_H__ */
92 94
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
index c757e2070cac..c4a7be5dee60 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
@@ -145,6 +145,7 @@ const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
145 .ops = { 145 .ops = {
146 .enable = dsi_20nm_phy_enable, 146 .enable = dsi_20nm_phy_enable,
147 .disable = dsi_20nm_phy_disable, 147 .disable = dsi_20nm_phy_disable,
148 .init = msm_dsi_phy_init_common,
148 }, 149 },
149 .io_start = { 0xfd998300, 0xfd9a0300 }, 150 .io_start = { 0xfd998300, 0xfd9a0300 },
150 .num_dsi_phy = 2, 151 .num_dsi_phy = 2,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index 63d7fba31380..ea740c5fb235 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -144,6 +144,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
144 .ops = { 144 .ops = {
145 .enable = dsi_28nm_phy_enable, 145 .enable = dsi_28nm_phy_enable,
146 .disable = dsi_28nm_phy_disable, 146 .disable = dsi_28nm_phy_disable,
147 .init = msm_dsi_phy_init_common,
147 }, 148 },
148 .io_start = { 0xfd922b00, 0xfd923100 }, 149 .io_start = { 0xfd922b00, 0xfd923100 },
149 .num_dsi_phy = 2, 150 .num_dsi_phy = 2,
@@ -161,6 +162,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
161 .ops = { 162 .ops = {
162 .enable = dsi_28nm_phy_enable, 163 .enable = dsi_28nm_phy_enable,
163 .disable = dsi_28nm_phy_disable, 164 .disable = dsi_28nm_phy_disable,
165 .init = msm_dsi_phy_init_common,
164 }, 166 },
165 .io_start = { 0x1a98500 }, 167 .io_start = { 0x1a98500 },
166 .num_dsi_phy = 1, 168 .num_dsi_phy = 1,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 7bdb9de54968..9aff0ba069cc 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -191,6 +191,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
191 .ops = { 191 .ops = {
192 .enable = dsi_28nm_phy_enable, 192 .enable = dsi_28nm_phy_enable,
193 .disable = dsi_28nm_phy_disable, 193 .disable = dsi_28nm_phy_disable,
194 .init = msm_dsi_phy_init_common,
194 }, 195 },
195 .io_start = { 0x4700300, 0x5800300 }, 196 .io_start = { 0x4700300, 0x5800300 },
196 .num_dsi_phy = 2, 197 .num_dsi_phy = 2,