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-rw-r--r--drivers/soc/mediatek/mtk-pmic-wrap.c28
1 files changed, 12 insertions, 16 deletions
diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index aa54df304449..a2bacda5a65d 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -374,20 +374,11 @@ struct pmic_wrapper_type {
374 u32 int_en_all; 374 u32 int_en_all;
375 u32 spi_w; 375 u32 spi_w;
376 u32 wdt_src; 376 u32 wdt_src;
377 int has_bridge:1;
377 int (*init_reg_clock)(struct pmic_wrapper *wrp); 378 int (*init_reg_clock)(struct pmic_wrapper *wrp);
378 int (*init_soc_specific)(struct pmic_wrapper *wrp); 379 int (*init_soc_specific)(struct pmic_wrapper *wrp);
379}; 380};
380 381
381static inline int pwrap_is_mt8135(struct pmic_wrapper *wrp)
382{
383 return wrp->master->type == PWRAP_MT8135;
384}
385
386static inline int pwrap_is_mt8173(struct pmic_wrapper *wrp)
387{
388 return wrp->master->type == PWRAP_MT8173;
389}
390
391static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg) 382static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
392{ 383{
393 return readl(wrp->base + wrp->master->regs[reg]); 384 return readl(wrp->base + wrp->master->regs[reg]);
@@ -619,11 +610,14 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
619 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL); 610 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
620 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL); 611 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
621 612
622 if (pwrap_is_mt8135(wrp)) { 613 switch (wrp->master->type) {
614 case PWRAP_MT8135:
623 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD); 615 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
624 pwrap_writel(wrp, 1, PWRAP_CIPHER_START); 616 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
625 } else { 617 break;
618 case PWRAP_MT8173:
626 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN); 619 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
620 break;
627 } 621 }
628 622
629 /* Config cipher mode @PMIC */ 623 /* Config cipher mode @PMIC */
@@ -713,7 +707,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
713 if (wrp->rstc_bridge) 707 if (wrp->rstc_bridge)
714 reset_control_reset(wrp->rstc_bridge); 708 reset_control_reset(wrp->rstc_bridge);
715 709
716 if (pwrap_is_mt8173(wrp)) { 710 if (wrp->master->type == PWRAP_MT8173) {
717 /* Enable DCM */ 711 /* Enable DCM */
718 pwrap_writel(wrp, 3, PWRAP_DCM_EN); 712 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
719 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); 713 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
@@ -773,7 +767,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
773 pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR); 767 pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
774 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); 768 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
775 769
776 if (pwrap_is_mt8135(wrp)) 770 if (wrp->master->type == PWRAP_MT8135)
777 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN); 771 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
778 772
779 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN); 773 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
@@ -793,7 +787,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
793 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0); 787 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
794 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1); 788 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
795 789
796 if (pwrap_is_mt8135(wrp)) { 790 if (wrp->master->has_bridge) {
797 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3); 791 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
798 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4); 792 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
799 } 793 }
@@ -831,6 +825,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
831 .int_en_all = ~(BIT(31) | BIT(1)), 825 .int_en_all = ~(BIT(31) | BIT(1)),
832 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 826 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
833 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 827 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
828 .has_bridge = 1,
834 .init_reg_clock = pwrap_mt8135_init_reg_clock, 829 .init_reg_clock = pwrap_mt8135_init_reg_clock,
835 .init_soc_specific = pwrap_mt8135_init_soc_specific, 830 .init_soc_specific = pwrap_mt8135_init_soc_specific,
836}; 831};
@@ -842,6 +837,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
842 .int_en_all = ~(BIT(31) | BIT(1)), 837 .int_en_all = ~(BIT(31) | BIT(1)),
843 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 838 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
844 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD, 839 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
840 .has_bridge = 0,
845 .init_reg_clock = pwrap_mt8173_init_reg_clock, 841 .init_reg_clock = pwrap_mt8173_init_reg_clock,
846 .init_soc_specific = pwrap_mt8173_init_soc_specific, 842 .init_soc_specific = pwrap_mt8173_init_soc_specific,
847}; 843};
@@ -889,7 +885,7 @@ static int pwrap_probe(struct platform_device *pdev)
889 return ret; 885 return ret;
890 } 886 }
891 887
892 if (pwrap_is_mt8135(wrp)) { 888 if (wrp->master->has_bridge) {
893 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 889 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
894 "pwrap-bridge"); 890 "pwrap-bridge");
895 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res); 891 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);