diff options
| -rw-r--r-- | drivers/pci/controller/dwc/pci-keystone.c | 11 | ||||
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware.h | 4 |
2 files changed, 7 insertions, 8 deletions
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 2decbaec81a3..e181e6277323 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c | |||
| @@ -38,8 +38,6 @@ | |||
| 38 | 38 | ||
| 39 | /* Application register defines */ | 39 | /* Application register defines */ |
| 40 | #define LTSSM_EN_VAL BIT(0) | 40 | #define LTSSM_EN_VAL BIT(0) |
| 41 | #define LTSSM_STATE_MASK 0x1f | ||
| 42 | #define LTSSM_STATE_L0 0x11 | ||
| 43 | #define DBI_CS2 BIT(5) | 41 | #define DBI_CS2 BIT(5) |
| 44 | #define OB_XLAT_EN_VAL BIT(1) | 42 | #define OB_XLAT_EN_VAL BIT(1) |
| 45 | 43 | ||
| @@ -87,11 +85,7 @@ | |||
| 87 | #define ERR_IRQ_ENABLE_SET 0x1c8 | 85 | #define ERR_IRQ_ENABLE_SET 0x1c8 |
| 88 | #define ERR_IRQ_ENABLE_CLR 0x1cc | 86 | #define ERR_IRQ_ENABLE_CLR 0x1cc |
| 89 | 87 | ||
| 90 | /* Config space registers */ | ||
| 91 | #define DEBUG0 0x728 | ||
| 92 | |||
| 93 | #define MAX_MSI_HOST_IRQS 8 | 88 | #define MAX_MSI_HOST_IRQS 8 |
| 94 | |||
| 95 | /* PCIE controller device IDs */ | 89 | /* PCIE controller device IDs */ |
| 96 | #define PCIE_RC_K2HK 0xb008 | 90 | #define PCIE_RC_K2HK 0xb008 |
| 97 | #define PCIE_RC_K2E 0xb009 | 91 | #define PCIE_RC_K2E 0xb009 |
| @@ -442,8 +436,9 @@ static int ks_pcie_link_up(struct dw_pcie *pci) | |||
| 442 | { | 436 | { |
| 443 | u32 val; | 437 | u32 val; |
| 444 | 438 | ||
| 445 | val = dw_pcie_readl_dbi(pci, DEBUG0); | 439 | val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); |
| 446 | return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0; | 440 | val &= PORT_LOGIC_LTSSM_STATE_MASK; |
| 441 | return (val == PORT_LOGIC_LTSSM_STATE_L0); | ||
| 447 | } | 442 | } |
| 448 | 443 | ||
| 449 | static void ks_pcie_initiate_link_train(struct keystone_pcie *ks_pcie) | 444 | static void ks_pcie_initiate_link_train(struct keystone_pcie *ks_pcie) |
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 96126fd8403c..a4d939536faf 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h | |||
| @@ -37,6 +37,10 @@ | |||
| 37 | #define PORT_LINK_MODE_4_LANES (0x7 << 16) | 37 | #define PORT_LINK_MODE_4_LANES (0x7 << 16) |
| 38 | #define PORT_LINK_MODE_8_LANES (0xf << 16) | 38 | #define PORT_LINK_MODE_8_LANES (0xf << 16) |
| 39 | 39 | ||
| 40 | #define PCIE_PORT_DEBUG0 0x728 | ||
| 41 | #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f | ||
| 42 | #define PORT_LOGIC_LTSSM_STATE_L0 0x11 | ||
| 43 | |||
| 40 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C | 44 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C |
| 41 | #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) | 45 | #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) |
| 42 | #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) | 46 | #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) |
