4 files changed, 536 insertions, 0 deletions

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 56ff8f6d31fc..4a28e07d4c0e 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -98,6 +98,9 @@ config PCI_ECAM
 config PCI_LOCKLESS_CONFIG
         bool
 
+config PCI_BRIDGE_EMUL
+        bool
+
 config PCI_IOV
         bool "PCI IOV support"
         depends on PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 1b2cfe51e8d7..3e5caf7347e9 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_HOTPLUG_PCI)	+= hotplug/
 obj-$(CONFIG_PCI_MSI)           += msi.o
 obj-$(CONFIG_PCI_ATS)           += ats.o
 obj-$(CONFIG_PCI_IOV)           += iov.o
+obj-$(CONFIG_PCI_BRIDGE_EMUL)   += pci-bridge-emul.o
 obj-$(CONFIG_ACPI)              += pci-acpi.o
 obj-$(CONFIG_PCI_LABEL)         += pci-label.o
 obj-$(CONFIG_X86_INTEL_MID)     += pci-mid.o
diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
new file mode 100644
index 000000000000..129738362d90
--- /dev/null
+++ b/drivers/pci/pci-bridge-emul.c
@@ -0,0 +1,408 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell
+ *
+ * Author: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
+ *
+ * This file helps PCI controller drivers implement a fake root port
+ * PCI bridge when the HW doesn't provide such a root port PCI
+ * bridge.
+ *
+ * It emulates a PCI bridge by providing a fake PCI configuration
+ * space (and optionally a PCIe capability configuration space) in
+ * memory. By default the read/write operations simply read and update
+ * this fake configuration space in memory. However, PCI controller
+ * drivers can provide through the 'struct pci_sw_bridge_ops'
+ * structure a set of operations to override or complement this
+ * default behavior.
+ */
+
+#include <linux/pci.h>
+#include "pci-bridge-emul.h"
+
+#define PCI_BRIDGE_CONF_END     PCI_STD_HEADER_SIZEOF
+#define PCI_CAP_PCIE_START      PCI_BRIDGE_CONF_END
+#define PCI_CAP_PCIE_END        (PCI_CAP_PCIE_START + PCI_EXP_SLTSTA2 + 2)
+
+/*
+ * Initialize a pci_bridge_emul structure to represent a fake PCI
+ * bridge configuration space. The caller needs to have initialized
+ * the PCI configuration space with whatever values make sense
+ * (typically at least vendor, device, revision), the ->ops pointer,
+ * and optionally ->data and ->has_pcie.
+ */
+void pci_bridge_emul_init(struct pci_bridge_emul *bridge)
+{
+        bridge->conf.class_revision |= PCI_CLASS_BRIDGE_PCI << 16;
+        bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
+        bridge->conf.cache_line_size = 0x10;
+        bridge->conf.status = PCI_STATUS_CAP_LIST;
+
+        if (bridge->has_pcie) {
+                bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
+                bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
+                /* Set PCIe v2, root port, slot support */
+                bridge->pcie_conf.cap = PCI_EXP_TYPE_ROOT_PORT << 4 | 2 |
+                        PCI_EXP_FLAGS_SLOT;
+        }
+}
+
+struct pci_bridge_reg_behavior {
+        /* Read-only bits */
+        u32 ro;
+
+        /* Read-write bits */
+        u32 rw;
+
+        /* Write-1-to-clear bits */
+        u32 w1c;
+
+        /* Reserved bits (hardwired to 0) */
+        u32 rsvd;
+};
+
+const static struct pci_bridge_reg_behavior pci_regs_behavior[] = {
+        [PCI_VENDOR_ID / 4] = { .ro = ~0 },
+        [PCI_COMMAND / 4] = {
+                .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+                       PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
+                       PCI_COMMAND_SERR),
+                .ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
+                        PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
+                        PCI_COMMAND_FAST_BACK) |
+                       (PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ |
+                        PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16),
+                .rsvd = GENMASK(15, 10) | ((BIT(6) | GENMASK(3, 0)) << 16),
+                .w1c = (PCI_STATUS_PARITY |
+                        PCI_STATUS_SIG_TARGET_ABORT |
+                        PCI_STATUS_REC_TARGET_ABORT |
+                        PCI_STATUS_REC_MASTER_ABORT |
+                        PCI_STATUS_SIG_SYSTEM_ERROR |
+                        PCI_STATUS_DETECTED_PARITY) << 16,
+        },
+        [PCI_CLASS_REVISION / 4] = { .ro = ~0 },
+
+        /*
+         * Cache Line Size register: implement as read-only, we do not
+         * pretend implementing "Memory Write and Invalidate"
+         * transactions"
+         *
+         * Latency Timer Register: implemented as read-only, as "A
+         * bridge that is not capable of a burst transfer of more than
+         * two data phases on its primary interface is permitted to
+         * hardwire the Latency Timer to a value of 16 or less"
+         *
+         * Header Type: always read-only
+         *
+         * BIST register: implemented as read-only, as "A bridge that
+         * does not support BIST must implement this register as a
+         * read-only register that returns 0 when read"
+         */
+        [PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 },
+
+        /*
+         * Base Address registers not used must be implemented as
+         * read-only registers that return 0 when read.
+         */
+        [PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 },
+        [PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 },
+
+        [PCI_PRIMARY_BUS / 4] = {
+                /* Primary, secondary and subordinate bus are RW */
+                .rw = GENMASK(24, 0),
+                /* Secondary latency is read-only */
+                .ro = GENMASK(31, 24),
+        },
+
+        [PCI_IO_BASE / 4] = {
+                /* The high four bits of I/O base/limit are RW */
+                .rw = (GENMASK(15, 12) | GENMASK(7, 4)),
+
+                /* The low four bits of I/O base/limit are RO */
+                .ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
+                         PCI_STATUS_DEVSEL_MASK) << 16) |
+                       GENMASK(11, 8) | GENMASK(3, 0)),
+
+                .w1c = (PCI_STATUS_PARITY |
+                        PCI_STATUS_SIG_TARGET_ABORT |
+                        PCI_STATUS_REC_TARGET_ABORT |
+                        PCI_STATUS_REC_MASTER_ABORT |
+                        PCI_STATUS_SIG_SYSTEM_ERROR |
+                        PCI_STATUS_DETECTED_PARITY) << 16,
+
+                .rsvd = ((BIT(6) | GENMASK(4, 0)) << 16),
+        },
+
+        [PCI_MEMORY_BASE / 4] = {
+                /* The high 12-bits of mem base/limit are RW */
+                .rw = GENMASK(31, 20) | GENMASK(15, 4),
+
+                /* The low four bits of mem base/limit are RO */
+                .ro = GENMASK(19, 16) | GENMASK(3, 0),
+        },
+
+        [PCI_PREF_MEMORY_BASE / 4] = {
+                /* The high 12-bits of pref mem base/limit are RW */
+                .rw = GENMASK(31, 20) | GENMASK(15, 4),
+
+                /* The low four bits of pref mem base/limit are RO */
+                .ro = GENMASK(19, 16) | GENMASK(3, 0),
+        },
+
+        [PCI_PREF_BASE_UPPER32 / 4] = {
+                .rw = ~0,
+        },
+
+        [PCI_PREF_LIMIT_UPPER32 / 4] = {
+                .rw = ~0,
+        },
+
+        [PCI_IO_BASE_UPPER16 / 4] = {
+                .rw = ~0,
+        },
+
+        [PCI_CAPABILITY_LIST / 4] = {
+                .ro = GENMASK(7, 0),
+                .rsvd = GENMASK(31, 8),
+        },
+
+        [PCI_ROM_ADDRESS1 / 4] = {
+                .rw = GENMASK(31, 11) | BIT(0),
+                .rsvd = GENMASK(10, 1),
+        },
+
+        /*
+         * Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8)
+         * are RO, and bridge control (31:16) are a mix of RW, RO,
+         * reserved and W1C bits
+         */
+        [PCI_INTERRUPT_LINE / 4] = {
+                /* Interrupt line is RW */
+                .rw = (GENMASK(7, 0) |
+                       ((PCI_BRIDGE_CTL_PARITY |