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-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi116
4 files changed, 111 insertions, 11 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index b0dd010979e7..8bc1f8f6fcfc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -46,7 +46,7 @@
46 46
47/dts-v1/; 47/dts-v1/;
48 48
49/include/ "fsl-ls2080a.dtsi" 49#include "fsl-ls2080a.dtsi"
50 50
51/ { 51/ {
52 model = "Freescale Layerscape 2080a QDS Board"; 52 model = "Freescale Layerscape 2080a QDS Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
index ad0ebb8a1949..265e0a8b107b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
@@ -46,7 +46,7 @@
46 46
47/dts-v1/; 47/dts-v1/;
48 48
49/include/ "fsl-ls2080a.dtsi" 49#include "fsl-ls2080a.dtsi"
50 50
51/ { 51/ {
52 model = "Freescale Layerscape 2080a RDB Board"; 52 model = "Freescale Layerscape 2080a RDB Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
index 505d038078a3..290604b0a603 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
@@ -46,7 +46,7 @@
46 46
47/dts-v1/; 47/dts-v1/;
48 48
49/include/ "fsl-ls2080a.dtsi" 49#include "fsl-ls2080a.dtsi"
50 50
51/ { 51/ {
52 model = "Freescale Layerscape 2080a software Simulator model"; 52 model = "Freescale Layerscape 2080a software Simulator model";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 337da90bd7da..723185e85d6f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -44,6 +44,8 @@
44 * OTHER DEALINGS IN THE SOFTWARE. 44 * OTHER DEALINGS IN THE SOFTWARE.
45 */ 45 */
46 46
47#include <dt-bindings/thermal/thermal.h>
48
47/ { 49/ {
48 compatible = "fsl,ls2080a"; 50 compatible = "fsl,ls2080a";
49 interrupt-parent = <&gic>; 51 interrupt-parent = <&gic>;
@@ -62,15 +64,16 @@
62 */ 64 */
63 65
64 /* We have 4 clusters having 2 Cortex-A57 cores each */ 66 /* We have 4 clusters having 2 Cortex-A57 cores each */
65 cpu@0 { 67 cpu0: cpu@0 {
66 device_type = "cpu"; 68 device_type = "cpu";
67 compatible = "arm,cortex-a57"; 69 compatible = "arm,cortex-a57";
68 reg = <0x0>; 70 reg = <0x0>;
69 clocks = <&clockgen 1 0>; 71 clocks = <&clockgen 1 0>;
70 next-level-cache = <&cluster0_l2>; 72 next-level-cache = <&cluster0_l2>;
73 #cooling-cells = <2>;
71 }; 74 };
72 75
73 cpu@1 { 76 cpu1: cpu@1 {
74 device_type = "cpu"; 77 device_type = "cpu";
75 compatible = "arm,cortex-a57"; 78 compatible = "arm,cortex-a57";
76 reg = <0x1>; 79 reg = <0x1>;
@@ -78,15 +81,16 @@
78 next-level-cache = <&cluster0_l2>; 81 next-level-cache = <&cluster0_l2>;
79 }; 82 };
80 83
81 cpu@100 { 84 cpu2: cpu@100 {
82 device_type = "cpu"; 85 device_type = "cpu";
83 compatible = "arm,cortex-a57"; 86 compatible = "arm,cortex-a57";
84 reg = <0x100>; 87 reg = <0x100>;
85 clocks = <&clockgen 1 1>; 88 clocks = <&clockgen 1 1>;
86 next-level-cache = <&cluster1_l2>; 89 next-level-cache = <&cluster1_l2>;
90 #cooling-cells = <2>;
87 }; 91 };
88 92
89 cpu@101 { 93 cpu3: cpu@101 {
90 device_type = "cpu"; 94 device_type = "cpu";
91 compatible = "arm,cortex-a57"; 95 compatible = "arm,cortex-a57";
92 reg = <0x101>; 96 reg = <0x101>;
@@ -94,15 +98,16 @@
94 next-level-cache = <&cluster1_l2>; 98 next-level-cache = <&cluster1_l2>;
95 }; 99 };
96 100
97 cpu@200 { 101 cpu4: cpu@200 {
98 device_type = "cpu"; 102 device_type = "cpu";
99 compatible = "arm,cortex-a57"; 103 compatible = "arm,cortex-a57";
100 reg = <0x200>; 104 reg = <0x200>;
101 clocks = <&clockgen 1 2>; 105 clocks = <&clockgen 1 2>;
102 next-level-cache = <&cluster2_l2>; 106 next-level-cache = <&cluster2_l2>;
107 #cooling-cells = <2>;
103 }; 108 };
104 109
105 cpu@201 { 110 cpu5: cpu@201 {
106 device_type = "cpu"; 111 device_type = "cpu";
107 compatible = "arm,cortex-a57"; 112 compatible = "arm,cortex-a57";
108 reg = <0x201>; 113 reg = <0x201>;
@@ -110,15 +115,16 @@
110 next-level-cache = <&cluster2_l2>; 115 next-level-cache = <&cluster2_l2>;
111 }; 116 };
112 117
113 cpu@300 { 118 cpu6: cpu@300 {
114 device_type = "cpu"; 119 device_type = "cpu";
115 compatible = "arm,cortex-a57"; 120 compatible = "arm,cortex-a57";
116 reg = <0x300>; 121 reg = <0x300>;
117 clocks = <&clockgen 1 3>; 122 clocks = <&clockgen 1 3>;
118 next-level-cache = <&cluster3_l2>; 123 next-level-cache = <&cluster3_l2>;
124 #cooling-cells = <2>;
119 }; 125 };
120 126
121 cpu@301 { 127 cpu7: cpu@301 {
122 device_type = "cpu"; 128 device_type = "cpu";
123 compatible = "arm,cortex-a57"; 129 compatible = "arm,cortex-a57";
124 reg = <0x301>; 130 reg = <0x301>;
@@ -215,6 +221,100 @@
215 clocks = <&sysclk>; 221 clocks = <&sysclk>;
216 }; 222 };
217 223
224 tmu: tmu@1f80000 {
225 compatible = "fsl,qoriq-tmu";
226 reg = <0x0 0x1f80000 0x0 0x10000>;
227 interrupts = <0 23 0x4>;
228 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
229 fsl,tmu-calibration = <0x00000000 0x00000026
230 0x00000001 0x0000002d
231 0x00000002 0x00000032
232 0x00000003 0x00000039
233 0x00000004 0x0000003f
234 0x00000005 0x00000046
235 0x00000006 0x0000004d
236 0x00000007 0x00000054
237 0x00000008 0x0000005a
238 0x00000009 0x00000061
239 0x0000000a 0x0000006a
240 0x0000000b 0x00000071
241
242 0x00010000 0x00000025
243 0x00010001 0x0000002c
244 0x00010002 0x00000035
245 0x00010003 0x0000003d
246 0x00010004 0x00000045
247 0x00010005 0x0000004e
248 0x00010006 0x00000057
249 0x00010007 0x00000061
250 0x00010008 0x0000006b
251 0x00010009 0x00000076
252
253 0x00020000 0x00000029
254 0x00020001 0x00000033
255 0x00020002 0x0000003d
256 0x00020003 0x00000049
257 0x00020004 0x00000056
258 0x00020005 0x00000061
259 0x00020006 0x0000006d
260
261 0x00030000 0x00000021
262 0x00030001 0x0000002a
263 0x00030002 0x0000003c
264 0x00030003 0x0000004e>;
265 little-endian;
266 #thermal-sensor-cells = <1>;
267 };
268
269 thermal-zones {
270 cpu_thermal: cpu-thermal {
271 polling-delay-passive = <1000>;
272 polling-delay = <5000>;
273
274 thermal-sensors = <&tmu 4>;
275
276 trips {
277 cpu_alert: cpu-alert {
278 temperature = <75000>;
279 hysteresis = <2000>;
280 type = "passive";
281 };
282 cpu_crit: cpu-crit {
283 temperature = <85000>;
284 hysteresis = <2000>;
285 type = "critical";
286 };
287 };
288
289 cooling-maps {
290 map0 {
291 trip = <&cpu_alert>;
292 cooling-device =
293 <&cpu0 THERMAL_NO_LIMIT
294 THERMAL_NO_LIMIT>;
295 };
296 map1 {
297 trip = <&cpu_alert>;
298 cooling-device =
299 <&cpu2 THERMAL_NO_LIMIT
300 THERMAL_NO_LIMIT>;
301 };
302 map2 {
303 trip = <&cpu_alert>;
304 cooling-device =
305 <&cpu4 THERMAL_NO_LIMIT
306 THERMAL_NO_LIMIT>;
307 };
308 map3 {
309 trip = <&cpu_alert>;
310 cooling-device =
311 <&cpu6 THERMAL_NO_LIMIT
312 THERMAL_NO_LIMIT>;
313 };
314 };
315 };
316 };
317
218 serial0: serial@21c0500 { 318 serial0: serial@21c0500 {
219 compatible = "fsl,ns16550", "ns16550a"; 319 compatible = "fsl,ns16550", "ns16550a";
220 reg = <0x0 0x21c0500 0x0 0x100>; 320 reg = <0x0 0x21c0500 0x0 0x100>;
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-06 22:05:12 -0500