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-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c7
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c16
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h4
3 files changed, 13 insertions, 14 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index f6cb502c303f..25f064c01038 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -138,13 +138,6 @@ int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc)
138 lut = (struct drm_color_lut *)blob->data; 138 lut = (struct drm_color_lut *)blob->data;
139 lut_size = blob->length / sizeof(struct drm_color_lut); 139 lut_size = blob->length / sizeof(struct drm_color_lut);
140 140
141 if (__is_lut_linear(lut, lut_size)) {
142 /* Set to bypass if lut is set to linear */
143 stream->out_transfer_func->type = TF_TYPE_BYPASS;
144 stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
145 return 0;
146 }
147
148 gamma = dc_create_gamma(); 141 gamma = dc_create_gamma();
149 if (!gamma) 142 if (!gamma)
150 return -ENOMEM; 143 return -ENOMEM;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index add90675fd2a..26fbeafc3c96 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4743,23 +4743,27 @@ static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
4743 4743
4744 for (i=0; i < dep_table->count; i++) { 4744 for (i=0; i < dep_table->count; i++) {
4745 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 4745 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
4746 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; 4746 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
4747 break; 4747 return;
4748 } 4748 }
4749 } 4749 }
4750 if (i == dep_table->count) 4750 if (i == dep_table->count && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
4751 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC; 4751 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
4752 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4753 }
4752 4754
4753 dep_table = table_info->vdd_dep_on_sclk; 4755 dep_table = table_info->vdd_dep_on_sclk;
4754 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk); 4756 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
4755 for (i=0; i < dep_table->count; i++) { 4757 for (i=0; i < dep_table->count; i++) {
4756 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 4758 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
4757 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; 4759 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
4758 break; 4760 return;
4759 } 4761 }
4760 } 4762 }
4761 if (i == dep_table->count) 4763 if (i == dep_table->count && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
4762 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC; 4764 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
4765 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4766 }
4763} 4767}
4764 4768
4765static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, 4769static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h
index fb696e3d06cf..2f8a3b983cce 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h
@@ -412,8 +412,10 @@ typedef struct {
412 QuadraticInt_t ReservedEquation2; 412 QuadraticInt_t ReservedEquation2;
413 QuadraticInt_t ReservedEquation3; 413 QuadraticInt_t ReservedEquation3;
414 414
415 uint16_t MinVoltageUlvGfx;
416 uint16_t MinVoltageUlvSoc;
415 417
416 uint32_t Reserved[15]; 418 uint32_t Reserved[14];
417 419
418 420
419 421