diff options
| -rw-r--r-- | drivers/net/netxen/netxen_nic_hdr.h | 6 | ||||
| -rw-r--r-- | drivers/net/netxen/netxen_nic_hw.c | 52 |
2 files changed, 8 insertions, 50 deletions
diff --git a/drivers/net/netxen/netxen_nic_hdr.h b/drivers/net/netxen/netxen_nic_hdr.h index d9300688ccb4..d8bd73d7e296 100644 --- a/drivers/net/netxen/netxen_nic_hdr.h +++ b/drivers/net/netxen/netxen_nic_hdr.h | |||
| @@ -681,14 +681,8 @@ enum { | |||
| 681 | #define MIU_TEST_AGT_ADDR_HI (0x08) | 681 | #define MIU_TEST_AGT_ADDR_HI (0x08) |
| 682 | #define MIU_TEST_AGT_WRDATA_LO (0x10) | 682 | #define MIU_TEST_AGT_WRDATA_LO (0x10) |
| 683 | #define MIU_TEST_AGT_WRDATA_HI (0x14) | 683 | #define MIU_TEST_AGT_WRDATA_HI (0x14) |
| 684 | #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x20) | ||
| 685 | #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x24) | ||
| 686 | #define MIU_TEST_AGT_WRDATA(i) (0x10+(0x10*((i)>>1))+(4*((i)&1))) | ||
| 687 | #define MIU_TEST_AGT_RDDATA_LO (0x18) | 684 | #define MIU_TEST_AGT_RDDATA_LO (0x18) |
| 688 | #define MIU_TEST_AGT_RDDATA_HI (0x1c) | 685 | #define MIU_TEST_AGT_RDDATA_HI (0x1c) |
| 689 | #define MIU_TEST_AGT_RDDATA_UPPER_LO (0x28) | ||
| 690 | #define MIU_TEST_AGT_RDDATA_UPPER_HI (0x2c) | ||
| 691 | #define MIU_TEST_AGT_RDDATA(i) (0x18+(0x10*((i)>>1))+(4*((i)&1))) | ||
| 692 | 686 | ||
| 693 | #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8 | 687 | #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8 |
| 694 | #define MIU_TEST_AGT_UPPER_ADDR(off) (0) | 688 | #define MIU_TEST_AGT_UPPER_ADDR(off) (0) |
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c index 5e5fe2fd6397..87bc910f9772 100644 --- a/drivers/net/netxen/netxen_nic_hw.c +++ b/drivers/net/netxen/netxen_nic_hw.c | |||
| @@ -1621,9 +1621,8 @@ static int | |||
| 1621 | netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, | 1621 | netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, |
| 1622 | u64 off, u64 data) | 1622 | u64 off, u64 data) |
| 1623 | { | 1623 | { |
| 1624 | int i, j, ret; | 1624 | int j, ret; |
| 1625 | u32 temp, off8; | 1625 | u32 temp, off8; |
| 1626 | u64 stride; | ||
| 1627 | void __iomem *mem_crb; | 1626 | void __iomem *mem_crb; |
| 1628 | 1627 | ||
| 1629 | /* Only 64-bit aligned access */ | 1628 | /* Only 64-bit aligned access */ |
| @@ -1650,44 +1649,17 @@ netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, | |||
| 1650 | return -EIO; | 1649 | return -EIO; |
| 1651 | 1650 | ||
| 1652 | correct: | 1651 | correct: |
| 1653 | stride = NX_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8; | 1652 | off8 = off & 0xfffffff8; |
| 1654 | |||
| 1655 | off8 = off & ~(stride-1); | ||
| 1656 | 1653 | ||
| 1657 | spin_lock(&adapter->ahw.mem_lock); | 1654 | spin_lock(&adapter->ahw.mem_lock); |
| 1658 | 1655 | ||
| 1659 | writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO)); | 1656 | writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO)); |
| 1660 | writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); | 1657 | writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); |
| 1661 | 1658 | ||
| 1662 | i = 0; | ||
| 1663 | if (stride == 16) { | ||
| 1664 | writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL)); | ||
| 1665 | writel((TA_CTL_START | TA_CTL_ENABLE), | ||
| 1666 | (mem_crb + TEST_AGT_CTRL)); | ||
| 1667 | |||
| 1668 | for (j = 0; j < MAX_CTL_CHECK; j++) { | ||
| 1669 | temp = readl(mem_crb + TEST_AGT_CTRL); | ||
| 1670 | if ((temp & TA_CTL_BUSY) == 0) | ||
| 1671 | break; | ||
| 1672 | } | ||
| 1673 | |||
| 1674 | if (j >= MAX_CTL_CHECK) { | ||
| 1675 | ret = -EIO; | ||
| 1676 | goto done; | ||
| 1677 | } | ||
| 1678 | |||
| 1679 | i = (off & 0xf) ? 0 : 2; | ||
| 1680 | writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)), | ||
| 1681 | mem_crb + MIU_TEST_AGT_WRDATA(i)); | ||
| 1682 | writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)), | ||
| 1683 | mem_crb + MIU_TEST_AGT_WRDATA(i+1)); | ||
| 1684 | i = (off & 0xf) ? 2 : 0; | ||
| 1685 | } | ||
| 1686 | |||
| 1687 | writel(data & 0xffffffff, | 1659 | writel(data & 0xffffffff, |
| 1688 | mem_crb + MIU_TEST_AGT_WRDATA(i)); | 1660 | mem_crb + MIU_TEST_AGT_WRDATA_LO); |
| 1689 | writel((data >> 32) & 0xffffffff, | 1661 | writel((data >> 32) & 0xffffffff, |
| 1690 | mem_crb + MIU_TEST_AGT_WRDATA(i+1)); | 1662 | mem_crb + MIU_TEST_AGT_WRDATA_HI); |
| 1691 | 1663 | ||
| 1692 | writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL)); | 1664 | writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL)); |
| 1693 | writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE), | 1665 | writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE), |
| @@ -1707,7 +1679,6 @@ correct: | |||
| 1707 | } else | 1679 | } else |
| 1708 | ret = 0; | 1680 | ret = 0; |
| 1709 | 1681 | ||
| 1710 | done: | ||
| 1711 | spin_unlock(&adapter->ahw.mem_lock); | 1682 | spin_unlock(&adapter->ahw.mem_lock); |
| 1712 | 1683 | ||
| 1713 | return ret; | 1684 | return ret; |
| @@ -1719,7 +1690,7 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, | |||
| 1719 | { | 1690 | { |
| 1720 | int j, ret; | 1691 | int j, ret; |
| 1721 | u32 temp, off8; | 1692 | u32 temp, off8; |
| 1722 | u64 val, stride; | 1693 | u64 val; |
| 1723 | void __iomem *mem_crb; | 1694 | void __iomem *mem_crb; |
| 1724 | 1695 | ||
| 1725 | /* Only 64-bit aligned access */ | 1696 | /* Only 64-bit aligned access */ |
| @@ -1748,9 +1719,7 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, | |||
| 1748 | return -EIO; | 1719 | return -EIO; |
| 1749 | 1720 | ||
| 1750 | correct: | 1721 | correct: |
| 1751 | stride = NX_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8; | 1722 | off8 = off & 0xfffffff8; |
| 1752 | |||
| 1753 | off8 = off & ~(stride-1); | ||
| 1754 | 1723 | ||
| 1755 | spin_lock(&adapter->ahw.mem_lock); | 1724 | spin_lock(&adapter->ahw.mem_lock); |
| 1756 | 1725 | ||
| @@ -1771,13 +1740,8 @@ correct: | |||
| 1771 | "failed to read through agent\n"); | 1740 | "failed to read through agent\n"); |
| 1772 | ret = -EIO; | 1741 | ret = -EIO; |
| 1773 | } else { | 1742 | } else { |
| 1774 | off8 = MIU_TEST_AGT_RDDATA_LO; | 1743 | val = (u64)(readl(mem_crb + MIU_TEST_AGT_RDDATA_HI)) << 32; |
| 1775 | if ((stride == 16) && (off & 0xf)) | 1744 | val |= readl(mem_crb + MIU_TEST_AGT_RDDATA_LO); |
| 1776 | off8 = MIU_TEST_AGT_RDDATA_UPPER_LO; | ||
| 1777 | |||
| 1778 | temp = readl(mem_crb + off8 + 4); | ||
| 1779 | val = (u64)temp << 32; | ||
| 1780 | val |= readl(mem_crb + off8); | ||
| 1781 | *data = val; | 1745 | *data = val; |
| 1782 | ret = 0; | 1746 | ret = 0; |
| 1783 | } | 1747 | } |
