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-rw-r--r--drivers/irqchip/irq-gic-v3-its.c2
-rw-r--r--include/linux/irqchip/arm-gic-common.h6
-rw-r--r--include/linux/irqchip/arm-gic.h5
3 files changed, 7 insertions, 6 deletions
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 4251d2d8e6e7..db20e992a40f 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -68,7 +68,7 @@ static u32 lpi_id_bits;
68#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K) 68#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
69#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K) 69#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
70 70
71#define LPI_PROP_DEFAULT_PRIO 0xa0 71#define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI
72 72
73/* 73/*
74 * Collection structure - just an ID, and a redistributor address to 74 * Collection structure - just an ID, and a redistributor address to
diff --git a/include/linux/irqchip/arm-gic-common.h b/include/linux/irqchip/arm-gic-common.h
index 0a83b4379f34..9a1a479a2bf4 100644
--- a/include/linux/irqchip/arm-gic-common.h
+++ b/include/linux/irqchip/arm-gic-common.h
@@ -13,6 +13,12 @@
13#include <linux/types.h> 13#include <linux/types.h>
14#include <linux/ioport.h> 14#include <linux/ioport.h>
15 15
16#define GICD_INT_DEF_PRI 0xa0
17#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\
18 (GICD_INT_DEF_PRI << 16) |\
19 (GICD_INT_DEF_PRI << 8) |\
20 GICD_INT_DEF_PRI)
21
16enum gic_type { 22enum gic_type {
17 GIC_V2, 23 GIC_V2,
18 GIC_V3, 24 GIC_V3,
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 6c4aaf04046c..626179077bb0 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -65,11 +65,6 @@
65#define GICD_INT_EN_CLR_X32 0xffffffff 65#define GICD_INT_EN_CLR_X32 0xffffffff
66#define GICD_INT_EN_SET_SGI 0x0000ffff 66#define GICD_INT_EN_SET_SGI 0x0000ffff
67#define GICD_INT_EN_CLR_PPI 0xffff0000 67#define GICD_INT_EN_CLR_PPI 0xffff0000
68#define GICD_INT_DEF_PRI 0xa0
69#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\
70 (GICD_INT_DEF_PRI << 16) |\
71 (GICD_INT_DEF_PRI << 8) |\
72 GICD_INT_DEF_PRI)
73 68
74#define GICD_IIDR_IMPLEMENTER_SHIFT 0 69#define GICD_IIDR_IMPLEMENTER_SHIFT 0
75#define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT) 70#define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT)