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-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c11
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c1
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c27
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h2
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c79
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h1
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link.c4
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc.h1
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c7
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c3
-rw-r--r--drivers/gpu/drm/amd/include/amd_shared.h4
-rw-r--r--drivers/gpu/drm/amd/include/atomfirmware.h7
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c53
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h1
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h3
-rw-r--r--drivers/gpu/drm/etnaviv/etnaviv_sched.c2
-rw-r--r--drivers/gpu/drm/exynos/exynos5433_drm_decon.c9
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_crtc.c11
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_drv.h1
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_dsi.c14
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_fbdev.c2
-rw-r--r--drivers/gpu/drm/i915/gvt/gtt.c115
-rw-r--r--drivers/gpu/drm/i915/gvt/gtt.h10
-rw-r--r--drivers/gpu/drm/i915/gvt/handlers.c8
-rw-r--r--drivers/gpu/drm/i915/gvt/mmio_context.c2
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c15
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c2
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c2
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.h36
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h20
-rw-r--r--drivers/gpu/drm/i915/intel_audio.c17
-rw-r--r--drivers/gpu/drm/i915/intel_cdclk.c18
-rw-r--r--drivers/gpu/drm/i915/intel_display.c19
-rw-r--r--drivers/gpu/drm/i915/intel_lpe_audio.c4
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c3
-rw-r--r--drivers/gpu/drm/i915/selftests/huge_pages.c2
-rw-r--r--drivers/gpu/drm/i915/selftests/i915_gem_gtt.c6
-rw-r--r--drivers/gpu/drm/sun4i/sun4i_lvds.c4
-rw-r--r--drivers/gpu/drm/sun4i/sun4i_rgb.c4
-rw-r--r--drivers/gpu/drm/sun4i/sun4i_tcon.c5
-rw-r--r--include/uapi/linux/kfd_ioctl.h18
43 files changed, 258 insertions, 297 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d0102cfc8efb..104b2e0d893b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -151,6 +151,7 @@ extern int amdgpu_compute_multipipe;
151extern int amdgpu_gpu_recovery; 151extern int amdgpu_gpu_recovery;
152extern int amdgpu_emu_mode; 152extern int amdgpu_emu_mode;
153extern uint amdgpu_smu_memory_pool_size; 153extern uint amdgpu_smu_memory_pool_size;
154extern uint amdgpu_dc_feature_mask;
154extern struct amdgpu_mgpu_info mgpu_info; 155extern struct amdgpu_mgpu_info mgpu_info;
155 156
156#ifdef CONFIG_DRM_AMDGPU_SI 157#ifdef CONFIG_DRM_AMDGPU_SI
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 943dbf3c5da1..8de55f7f1a3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -127,6 +127,9 @@ int amdgpu_compute_multipipe = -1;
127int amdgpu_gpu_recovery = -1; /* auto */ 127int amdgpu_gpu_recovery = -1; /* auto */
128int amdgpu_emu_mode = 0; 128int amdgpu_emu_mode = 0;
129uint amdgpu_smu_memory_pool_size = 0; 129uint amdgpu_smu_memory_pool_size = 0;
130/* FBC (bit 0) disabled by default*/
131uint amdgpu_dc_feature_mask = 0;
132
130struct amdgpu_mgpu_info mgpu_info = { 133struct amdgpu_mgpu_info mgpu_info = {
131 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 134 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
132}; 135};
@@ -631,6 +634,14 @@ module_param(halt_if_hws_hang, int, 0644);
631MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 634MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
632#endif 635#endif
633 636
637/**
638 * DOC: dcfeaturemask (uint)
639 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
640 * The default is the current set of stable display features.
641 */
642MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
643module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
644
634static const struct pci_device_id pciidlist[] = { 645static const struct pci_device_id pciidlist[] = {
635#ifdef CONFIG_DRM_AMDGPU_SI 646#ifdef CONFIG_DRM_AMDGPU_SI
636 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 647 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
index 2d4473557b0d..d13fc4fcb517 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
@@ -49,6 +49,7 @@ int vega20_reg_base_init(struct amdgpu_device *adev)
49 adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); 49 adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
50 adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); 50 adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
51 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); 51 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
52 adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
52 } 53 }
53 return 0; 54 return 0;
54} 55}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b0df6dc9a775..c1262f62cd9f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -429,6 +429,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
429 adev->asic_type < CHIP_RAVEN) 429 adev->asic_type < CHIP_RAVEN)
430 init_data.flags.gpu_vm_support = true; 430 init_data.flags.gpu_vm_support = true;
431 431
432 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
433 init_data.flags.fbc_support = true;
434
432 /* Display Core create. */ 435 /* Display Core create. */
433 adev->dm.dc = dc_create(&init_data); 436 adev->dm.dc = dc_create(&init_data);
434 437
@@ -1524,13 +1527,6 @@ static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1524{ 1527{
1525 struct amdgpu_display_manager *dm = bl_get_data(bd); 1528 struct amdgpu_display_manager *dm = bl_get_data(bd);
1526 1529
1527 /*
1528 * PWM interperts 0 as 100% rather than 0% because of HW
1529 * limitation for level 0.So limiting minimum brightness level
1530 * to 1.
1531 */
1532 if (bd->props.brightness < 1)
1533 return 1;
1534 if (dc_link_set_backlight_level(dm->backlight_link, 1530 if (dc_link_set_backlight_level(dm->backlight_link,
1535 bd->props.brightness, 0, 0)) 1531 bd->props.brightness, 0, 0))
1536 return 0; 1532 return 0;
@@ -2707,18 +2703,11 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2707 drm_connector = &aconnector->base; 2703 drm_connector = &aconnector->base;
2708 2704
2709 if (!aconnector->dc_sink) { 2705 if (!aconnector->dc_sink) {
2710 /* 2706 if (!aconnector->mst_port) {
2711 * Create dc_sink when necessary to MST 2707 sink = create_fake_sink(aconnector);
2712 * Don't apply fake_sink to MST 2708 if (!sink)
2713 */ 2709 return stream;
2714 if (aconnector->mst_port) {
2715 dm_dp_mst_dc_sink_create(drm_connector);
2716 return stream;
2717 } 2710 }
2718
2719 sink = create_fake_sink(aconnector);
2720 if (!sink)
2721 return stream;
2722 } else { 2711 } else {
2723 sink = aconnector->dc_sink; 2712 sink = aconnector->dc_sink;
2724 } 2713 }
@@ -3308,7 +3297,7 @@ void dm_drm_plane_destroy_state(struct drm_plane *plane,
3308static const struct drm_plane_funcs dm_plane_funcs = { 3297static const struct drm_plane_funcs dm_plane_funcs = {
3309 .update_plane = drm_atomic_helper_update_plane, 3298 .update_plane = drm_atomic_helper_update_plane,
3310 .disable_plane = drm_atomic_helper_disable_plane, 3299 .disable_plane = drm_atomic_helper_disable_plane,
3311 .destroy = drm_plane_cleanup, 3300 .destroy = drm_primary_helper_destroy,
3312 .reset = dm_drm_plane_reset, 3301 .reset = dm_drm_plane_reset,
3313 .atomic_duplicate_state = dm_drm_plane_duplicate_state, 3302 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3314 .atomic_destroy_state = dm_drm_plane_destroy_state, 3303 .atomic_destroy_state = dm_drm_plane_destroy_state,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 978b34a5011c..924a38a1fc44 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -160,8 +160,6 @@ struct amdgpu_dm_connector {
160 struct mutex hpd_lock; 160 struct mutex hpd_lock;
161 161
162 bool fake_enable; 162 bool fake_enable;
163
164 bool mst_connected;
165}; 163};
166 164
167#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 165#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 03601d717fed..d02c32a1039c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -205,40 +205,6 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
205 .atomic_get_property = amdgpu_dm_connector_atomic_get_property 205 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
206}; 206};
207 207
208void dm_dp_mst_dc_sink_create(struct drm_connector *connector)
209{
210 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
211 struct dc_sink *dc_sink;
212 struct dc_sink_init_data init_params = {
213 .link = aconnector->dc_link,
214 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
215
216 /* FIXME none of this is safe. we shouldn't touch aconnector here in
217 * atomic_check
218 */
219
220 /*
221 * TODO: Need to further figure out why ddc.algo is NULL while MST port exists
222 */
223 if (!aconnector->port || !aconnector->port->aux.ddc.algo)
224 return;
225
226 ASSERT(aconnector->edid);
227
228 dc_sink = dc_link_add_remote_sink(
229 aconnector->dc_link,
230 (uint8_t *)aconnector->edid,
231 (aconnector->edid->extensions + 1) * EDID_LENGTH,
232 &init_params);
233
234 dc_sink->priv = aconnector;
235 aconnector->dc_sink = dc_sink;
236
237 if (aconnector->dc_sink)
238 amdgpu_dm_update_freesync_caps(
239 connector, aconnector->edid);
240}
241
242static int dm_dp_mst_get_modes(struct drm_connector *connector) 208static int dm_dp_mst_get_modes(struct drm_connector *connector)
243{ 209{
244 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 210 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
@@ -319,12 +285,7 @@ dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector)
319 struct amdgpu_device *adev = dev->dev_private; 285 struct amdgpu_device *adev = dev->dev_private;
320 struct amdgpu_encoder *amdgpu_encoder; 286 struct amdgpu_encoder *amdgpu_encoder;
321 struct drm_encoder *encoder; 287 struct drm_encoder *encoder;
322 const struct drm_connector_helper_funcs *connector_funcs =
323 connector->base.helper_private;
324 struct drm_encoder *enc_master =
325 connector_funcs->best_encoder(&connector->base);
326 288
327 DRM_DEBUG_KMS("enc master is %p\n", enc_master);
328 amdgpu_encoder = kzalloc(sizeof(*amdgpu_encoder), GFP_KERNEL); 289 amdgpu_encoder = kzalloc(sizeof(*amdgpu_encoder), GFP_KERNEL);
329 if (!amdgpu_encoder) 290 if (!amdgpu_encoder)
330 return NULL; 291 return NULL;
@@ -354,25 +315,6 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
354 struct amdgpu_device *adev = dev->dev_private; 315 struct amdgpu_device *adev = dev->dev_private;
355 struct amdgpu_dm_connector *aconnector; 316 struct amdgpu_dm_connector *aconnector;
356 struct drm_connector *connector; 317 struct drm_connector *connector;
357 struct drm_connector_list_iter conn_iter;
358
359 drm_connector_list_iter_begin(dev, &conn_iter);
360 drm_for_each_connector_iter(connector, &conn_iter) {
361 aconnector = to_amdgpu_dm_connector(connector);
362 if (aconnector->mst_port == master
363 && !aconnector->port) {
364 DRM_INFO("DM_MST: reusing connector: %p [id: %d] [master: %p]\n",
365 aconnector, connector->base.id, aconnector->mst_port);
366
367 aconnector->port = port;
368 drm_connector_set_path_property(connector, pathprop);
369
370 drm_connector_list_iter_end(&conn_iter);
371 aconnector->mst_connected = true;
372 return &aconnector->base;
373 }
374 }
375 drm_connector_list_iter_end(&conn_iter);
376 318
377 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 319 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
378 if (!aconnector) 320 if (!aconnector)
@@ -421,8 +363,6 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
421 */ 363 */
422 amdgpu_dm_connector_funcs_reset(connector); 364 amdgpu_dm_connector_funcs_reset(connector);
423 365
424 aconnector->mst_connected = true;
425
426 DRM_INFO("DM_MST: added connector: %p [id: %d] [master: %p]\n", 366 DRM_INFO("DM_MST: added connector: %p [id: %d] [master: %p]\n",
427 aconnector, connector->base.id, aconnector->mst_port); 367 aconnector, connector->base.id, aconnector->mst_port);
428 368
@@ -434,6 +374,9 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
434static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 374static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
435 struct drm_connector *connector) 375 struct drm_connector *connector)
436{ 376{
377 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
378 struct drm_device *dev = master->base.dev;
379 struct amdgpu_device *adev = dev->dev_private;
437 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 380 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
438 381
439 DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n", 382 DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n",
@@ -447,7 +390,10 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
447 aconnector->dc_sink = NULL; 390 aconnector->dc_sink = NULL;
448 } 391 }
449 392
450 aconnector->mst_connected = false; 393 drm_connector_unregister(connector);
394 if (adev->mode_info.rfbdev)
395 drm_fb_helper_remove_one_connector(&adev->mode_info.rfbdev->helper, connector);
396 drm_connector_put(connector);
451} 397}
452 398
453static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) 399static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
@@ -458,18 +404,10 @@ static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
458 drm_kms_helper_hotplug_event(dev); 404 drm_kms_helper_hotplug_event(dev);
459} 405}
460 406
461static void dm_dp_mst_link_status_reset(struct drm_connector *connector)
462{
463 mutex_lock(&connector->dev->mode_config.mutex);
464 drm_connector_set_link_status_property(connector, DRM_MODE_LINK_STATUS_BAD);
465 mutex_unlock(&connector->dev->mode_config.mutex);
466}
467
468static void dm_dp_mst_register_connector(struct drm_connector *connector) 407static void dm_dp_mst_register_connector(struct drm_connector *connector)
469{ 408{
470 struct drm_device *dev = connector->dev; 409 struct drm_device *dev = connector->dev;
471 struct amdgpu_device *adev = dev->dev_private; 410 struct amdgpu_device *adev = dev->dev_private;
472 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
473 411
474 if (adev->mode_info.rfbdev) 412 if (adev->mode_info.rfbdev)
475 drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector); 413 drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector);
@@ -477,9 +415,6 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector)
477 DRM_ERROR("adev->mode_info.rfbdev is NULL\n"); 415 DRM_ERROR("adev->mode_info.rfbdev is NULL\n");
478 416
479 drm_connector_register(connector); 417 drm_connector_register(connector);
480
481 if (aconnector->mst_connected)
482 dm_dp_mst_link_status_reset(connector);
483} 418}
484 419
485static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { 420static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index 8cf51da26657..2da851b40042 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -31,6 +31,5 @@ struct amdgpu_dm_connector;
31 31
32void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, 32void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
33 struct amdgpu_dm_connector *aconnector); 33 struct amdgpu_dm_connector *aconnector);
34void dm_dp_mst_dc_sink_create(struct drm_connector *connector);
35 34
36#endif 35#endif
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index fb04a4ad141f..5da2186b3615 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1722,7 +1722,7 @@ static void write_i2c_retimer_setting(
1722 i2c_success = i2c_write(pipe_ctx, slave_address, 1722 i2c_success = i2c_write(pipe_ctx, slave_address,
1723 buffer, sizeof(buffer)); 1723 buffer, sizeof(buffer));
1724 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 1724 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1725 offset = 0x%d, reg_val = 0x%d, i2c_success = %d\n", 1725 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1726 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1726 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1727 if (!i2c_success) 1727 if (!i2c_success)
1728 /* Write failure */ 1728 /* Write failure */
@@ -1734,7 +1734,7 @@ static void write_i2c_retimer_setting(
1734 i2c_success = i2c_write(pipe_ctx, slave_address, 1734 i2c_success = i2c_write(pipe_ctx, slave_address,
1735 buffer, sizeof(buffer)); 1735 buffer, sizeof(buffer));
1736 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 1736 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1737 offset = 0x%d, reg_val = 0x%d, i2c_success = %d\n", 1737 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1738 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1738 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1739 if (!i2c_success) 1739 if (!i2c_success)
1740 /* Write failure */ 1740 /* Write failure */
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 199527171100..b57fa61b3034 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -169,6 +169,7 @@ struct link_training_settings;
169struct dc_config { 169struct dc_config {
170 bool gpu_vm_support; 170 bool gpu_vm_support;
171 bool disable_disp_pll_sharing; 171 bool disable_disp_pll_sharing;
172 bool fbc_support;
172}; 173};
173 174
174enum visual_confirm { 175enum visual_confirm {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index b75ede5f84f7..b459867a05b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1736,7 +1736,12 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1736 if (events->force_trigger) 1736 if (events->force_trigger)
1737 value |= 0x1; 1737 value |= 0x1;
1738 1738
1739 value |= 0x84; 1739 if (num_pipes) {
1740 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
1741
1742 if (dc->fbc_compressor)
1743 value |= 0x84;
1744 }
1740 1745
1741 for (i = 0; i < num_pipes; i++) 1746 for (i = 0; i < num_pipes; i++)
1742 pipe_ctx[i]->stream_res.tg->funcs-> 1747 pipe_ctx[i]->stream_res.tg->funcs->
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index e3624ca24574..7c9fd9052ee2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1362,7 +1362,8 @@ static bool construct(
1362 pool->base.sw_i2cs[i] = NULL; 1362 pool->base.sw_i2cs[i] = NULL;
1363 } 1363 }
1364 1364
1365 dc->fbc_compressor = dce110_compressor_create(ctx); 1365 if (dc->config.fbc_support)
1366 dc->fbc_compressor = dce110_compressor_create(ctx);
1366 1367
1367 if (!underlay_create(ctx, &pool->base)) 1368 if (!underlay_create(ctx, &pool->base))
1368 goto res_create_fail; 1369 goto res_create_fail;
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 2083c308007c..470d7b89071a 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -133,6 +133,10 @@ enum PP_FEATURE_MASK {
133 PP_AVFS_MASK = 0x40000, 133 PP_AVFS_MASK = 0x40000,
134}; 134};
135 135
136enum DC_FEATURE_MASK {
137 DC_FBC_MASK = 0x1,
138};
139
136/** 140/**
137 * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks 141 * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
138 */ 142 */
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index d2e7c0fa96c2..8eb0bb241210 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -1325,7 +1325,7 @@ struct atom_smu_info_v3_3 {
1325 struct atom_common_table_header table_header; 1325 struct atom_common_table_header table_header;
1326 uint8_t smuip_min_ver; 1326 uint8_t smuip_min_ver;
1327 uint8_t smuip_max_ver; 1327 uint8_t smuip_max_ver;
1328 uint8_t smu_rsd1; 1328 uint8_t waflclk_ss_mode;
1329 uint8_t gpuclk_ss_mode; 1329 uint8_t gpuclk_ss_mode;
1330 uint16_t sclk_ss_percentage; 1330 uint16_t sclk_ss_percentage;
1331 uint16_t sclk_ss_rate_10hz; 1331 uint16_t sclk_ss_rate_10hz;
@@ -1355,7 +1355,10 @@ struct atom_smu_info_v3_3 {
1355 uint32_t syspll3_1_vco_freq_10khz; 1355 uint32_t syspll3_1_vco_freq_10khz;
1356 uint32_t bootup_fclk_10khz; 1356 uint32_t bootup_fclk_10khz;
1357 uint32_t bootup_waflclk_10khz; 1357 uint32_t bootup_waflclk_10khz;
1358 uint32_t reserved[3]; 1358 uint32_t smu_info_caps;
1359 uint16_t waflclk_ss_percentage; // in unit of 0.001%
1360 uint16_t smuinitoffset;
1361 uint32_t reserved;
1359}; 1362};
1360 1363
1361/* 1364/*
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 57143d51e3ee..99861f32b1f9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -120,6 +120,7 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
120 data->registry_data.disable_auto_wattman = 1; 120 data->registry_data.disable_auto_wattman = 1;
121 data->registry_data.auto_wattman_debug = 0; 121 data->registry_data.auto_wattman_debug = 0;
122 data->registry_data.auto_wattman_sample_period = 100; 122 data->registry_data.auto_wattman_sample_period = 100;
123 data->registry_data.fclk_gfxclk_ratio = 0x3F6CCCCD;
123 data->registry_data.auto_wattman_threshold = 50; 124 data->registry_data.auto_wattman_threshold = 50;
124 data->registry_data.gfxoff_controlled_by_driver = 1; 125 data->registry_data.gfxoff_controlled_by_driver = 1;
125 data->gfxoff_allowed = false; 126 data->gfxoff_allowed = false;
@@ -829,6 +830,28 @@ static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
829 return 0; 830 return 0;
830} 831}
831 832
833static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
834{
835 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
836
837 if (data->smu_features[GNLD_DPM_UCLK].enabled)
838 return smum_send_msg_to_smc_with_parameter(hwmgr,
839 PPSMC_MSG_SetUclkFastSwitch,
840 1);
841
842 return 0;
843}
844
845static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
846{
847 struct vega20_hwmgr *data =
848 (struct vega20_hwmgr *)(hwmgr->backend);
849
850 return smum_send_msg_to_smc_with_parameter(hwmgr,
851 PPSMC_MSG_SetFclkGfxClkRatio,
852 data->registry_data.fclk_gfxclk_ratio);
853}
854
832static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr) 855static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
833{ 856{
834 struct vega20_hwmgr *data = 857 struct vega20_hwmgr *data =
@@ -1532,6 +1555,16 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1532 "[EnableDPMTasks] Failed to enable all smu features!", 1555 "[EnableDPMTasks] Failed to enable all smu features!",
1533 return result); 1556 return result);
1534 1557
1558 result = vega20_notify_smc_display_change(hwmgr);
1559 PP_ASSERT_WITH_CODE(!result,
1560 "[EnableDPMTasks] Failed to notify smc display change!",
1561 return result);
1562
1563 result = vega20_send_clock_ratio(hwmgr);
1564 PP_ASSERT_WITH_CODE(!result,
1565 "[EnableDPMTasks] Failed to send clock ratio!",
1566 return result);
1567
1535 /* Initialize UVD/VCE powergating state */ 1568 /* Initialize UVD/VCE powergating state */
1536 vega20_init_powergate_state(hwmgr); 1569 vega20_init_powergate_state(hwmgr);
1537 1570
@@ -1972,19 +2005,6 @@ static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1972 return ret; 2005 return ret;
1973} 2006}
1974 2007
1975static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr,
1976 bool has_disp)
1977{
1978 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1979
1980 if (data->smu_features[GNLD_DPM_UCLK].enabled)
1981 return smum_send_msg_to_smc_with_parameter(hwmgr,
1982 PPSMC_MSG_SetUclkFastSwitch,
1983 has_disp ? 1 : 0);
1984
1985 return 0;
1986}
1987
1988int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr, 2008int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
1989 struct pp_display_clock_request *clock_req) 2009 struct pp_display_clock_request *clock_req)
1990{ 2010{
@@ -2044,13 +2064,6 @@ static int vega20_notify_smc_display_config_after_ps_adjustment(
2044 struct pp_display_clock_request clock_req; 2064 struct pp_display_clock_request clock_req;
2045 int ret = 0; 2065 int ret = 0;
2046 2066
2047 if ((hwmgr->display_config->num_display > 1) &&
2048 !hwmgr->display_config->multi_monitor_in_sync &&
2049 !hwmgr->display_config->nb_pstate_switch_disable)
2050 vega20_notify_smc_display_change(hwmgr, false);
2051 else
2052 vega20_notify_smc_display_change(hwmgr, true);
2053
2054 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; 2067 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2055 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; 2068 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2056 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 2069 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
index 56fe6a0d42e8..25faaa5c5b10 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
@@ -328,6 +328,7 @@ struct vega20_registry_data {
328 uint8_t disable_auto_wattman; 328 uint8_t disable_auto_wattman;
329 uint32_t auto_wattman_debug; 329 uint32_t auto_wattman_debug;
330 uint32_t auto_wattman_sample_period; 330 uint32_t auto_wattman_sample_period;
331 uint32_t fclk_gfxclk_ratio;
331 uint8_t auto_wattman_threshold; 332 uint8_t auto_wattman_threshold;
332 uint8_t log_avfs_param; 333 uint8_t log_avfs_param;
333 uint8_t enable_enginess; 334 uint8_t enable_enginess;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
index 45d64a81e945..4f63a736ea0e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
@@ -105,7 +105,8 @@
105#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x4B 105#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x4B
106#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x4C 106#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x4C
107#define PPSMC_MSG_WaflTest 0x4D 107#define PPSMC_MSG_WaflTest 0x4D
108// Unused ID 0x4E to 0x50 108#define PPSMC_MSG_SetFclkGfxClkRatio 0x4E
109// Unused ID 0x4F to 0x50
109#define PPSMC_MSG_AllowGfxOff 0x51 110#define PPSMC_MSG_AllowGfxOff 0x51
110#define PPSMC_MSG_DisallowGfxOff 0x52 111#define PPSMC_MSG_DisallowGfxOff 0x52
111#define PPSMC_MSG_GetPptLimit 0x53 112#define PPSMC_MSG_GetPptLimit 0x53
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_sched.c b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
index e7c3ed6c9a2e..9b476368aa31 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_sched.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
@@ -93,7 +93,7 @@ static void etnaviv_sched_timedout_job(struct drm_sched_job *sched_job)
93 * If the GPU managed to complete this jobs fence, the timout is 93 * If the GPU managed to complete this jobs fence, the timout is
94 * spurious. Bail out. 94 * spurious. Bail out.
95 */ 95 */
96 if (fence_completed(gpu, submit->out_fence->seqno)) 96 if (dma_fence_is_signaled(submit->out_fence))
97 return; 97 return;
98 98
99 /* 99 /*
diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 94529aa82339..aef487dd8731 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -164,13 +164,6 @@ static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
164 return frm; 164 return frm;
165} 165}
166 166
167static u32 decon_get_vblank_counter(struct exynos_drm_crtc *crtc)
168{
169 struct decon_context *ctx = crtc->ctx;
170
171 return decon_get_frame_count(ctx, false);
172}
173
174static void decon_setup_trigger(struct decon_context *ctx) 167static void decon_setup_trigger(struct decon_context *ctx)
175{ 168{
176 if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG)) 169 if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG))
@@ -536,7 +529,6 @@ static const struct exynos_drm_crtc_ops decon_crtc_ops = {
536 .disable = decon_disable, 529 .disable = decon_disable,
537 .enable_vblank = decon_enable_vblank, 530 .enable_vblank = decon_enable_vblank,
538 .disable_vblank = decon_disable_vblank, 531 .disable_vblank = decon_disable_vblank,
539 .get_vblank_counter = decon_get_vblank_counter,
540 .atomic_begin = decon_atomic_begin, 532 .atomic_begin = decon_atomic_begin,
541 .update_plane = decon_update_plane, 533 .update_plane = decon_update_plane,
542 .disable_plane = decon_disable_plane, 534 .disable_plane = decon_disable_plane,
@@ -554,7 +546,6 @@ static int decon_bind(struct device *dev, struct device *master, void *data)
554 int ret; 546 int ret;
555 547
556 ctx->drm_dev = drm_dev; 548 ctx->drm_dev = drm_dev;
557 drm_dev->max_vblank_count = 0xffffffff;
558 549
559 for (win = ctx->first_win; win < WINDOWS_NR; win++) { 550 for (win = ctx->first_win; win < WINDOWS_NR; win++) {
560 ctx->configs[win].pixel_formats = decon_formats; 551 ctx->configs[win].pixel_formats = decon_formats;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index eea90251808f..2696289ecc78 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -162,16 +162,6 @@ static void exynos_drm_crtc_disable_vblank(struct drm_crtc *crtc)
162 exynos_crtc->ops->disable_vblank(exynos_crtc); 162 exynos_crtc->ops->disable_vblank(exynos_crtc);
163} 163}
164 164
165static u32 exynos_drm_crtc_get_vblank_counter(struct drm_crtc *crtc)
166{
167 struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
168
169 if (exynos_crtc->ops->get_vblank_counter)
170 return exynos_crtc->ops->get_vblank_counter(exynos_crtc);
171
172 return 0;
173}
174
175static const struct drm_crtc_funcs exynos_crtc_funcs = { 165static const struct drm_crtc_funcs exynos_crtc_funcs = {
176 .set_config = drm_atomic_helper_set_config, 166 .set_config = drm_atomic_helper_set_config,
177 .page_flip = drm_atomic_helper_page_flip, 167 .page_flip = drm_atomic_helper_page_flip,
@@ -181,7 +171,6 @@ static const struct drm_crtc_funcs exynos_crtc_funcs = {
181 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 171 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
182 .enable_vblank = exynos_drm_crtc_enable_vblank, 172 .enable_vblank = exynos_drm_crtc_enable_vblank,
183 .disable_vblank = exynos_drm_crtc_disable_vblank, 173 .disable_vblank = exynos_drm_crtc_disable_vblank,
184 .get_vblank_counter = exynos_drm_crtc_get_vblank_counter,
185}; 174};
186 175
187struct exynos_drm_crtc *exynos_drm_crtc_create(struct drm_device *drm_dev, 176struct exynos_drm_crtc *exynos_drm_crtc_create(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index ec9604f1272b..5e61e707f955 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -135,7 +135,6 @@ struct exynos_drm_crtc_ops {
135 void (*disable)(struct exynos_drm_crtc *crtc); 135 void (*disable)(struct exynos_drm_crtc *crtc);
136 int (*enable_vblank)(struct exynos_drm_crtc *crtc); 136 int (*enable_vblank)(struct exynos_drm_crtc *crtc);
137 void (*disable_vblank)(struct exynos_drm_crtc *crtc); 137 void (*disable_vblank)(struct exynos_drm_crtc *crtc);
138 u32 (*get_vblank_counter)(struct exynos_drm_crtc *crtc);
139 enum drm_mode_status (*mode_valid)(struct exynos_drm_crtc *crtc, 138 enum drm_mode_status (*mode_valid)(struct exynos_drm_crtc *crtc,
140 const struct drm_display_mode *mode); 139 const struct drm_display_mode *mode);
141 bool (*mode_fixup)(struct exynos_drm_crtc *crtc, 140 bool (*mode_fixup)(struct exynos_drm_crtc *crtc,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 07af7758066d..d81e62ae286a 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -14,6 +14,7 @@
14 14
15#include <drm/drmP.h> 15#include <drm/drmP.h>
16#include <drm/drm_crtc_helper.h> 16#include <drm/drm_crtc_helper.h>
17#include <drm/drm_fb_helper.h>
17#include <drm/drm_mipi_dsi.h> 18#include <drm/drm_mipi_dsi.h>
18#include <drm/drm_panel.h> 19#include <drm/drm_panel.h>
19#include <drm/drm_atomic_helper.h> 20#include <drm/drm_atomic_helper.h>
@@ -1474,12 +1475,12 @@ static int exynos_dsi_create_connector(struct drm_encoder *encoder)
1474{ 1475{
1475 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1476 struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1476 struct drm_connector *connector = &dsi->connector; 1477 struct drm_connector *connector = &dsi->connector;
1478 struct drm_device *drm = encoder->dev;
1477 int ret; 1479 int ret;
1478 1480
1479 connector->polled = DRM_CONNECTOR_POLL_HPD; 1481 connector->polled = DRM_CONNECTOR_POLL_HPD;
1480 1482
1481 ret = drm_connector_init(encoder->dev, connector, 1483 ret = drm_connector_init(drm, connector, &exynos_dsi_connector_funcs,
1482 &exynos_dsi_connector_funcs,
1483 DRM_MODE_CONNECTOR_DSI); 1484 DRM_MODE_CONNECTOR_DSI);
1484 if (ret) { 1485 if (ret) {
1485 DRM_ERROR("Failed to initialize connector with drm\n"); 1486 DRM_ERROR("Failed to initialize connector with drm\n");
@@ -1489,7 +1490,12 @@ static int exynos_dsi_create_connector(struct drm_encoder *encoder)
1489 connector->status = connector_status_disconnected; 1490 connector->status = connector_status_disconnected;
1490 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs); 1491 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1491 drm_connector_attach_encoder(connector, encoder); 1492 drm_connector_attach_encoder(connector, encoder);
1493 if (!drm->registered)
1494 return 0;
1492 1495
1496 connector->funcs->reset(connector);
1497 drm_fb_helper_add_one_connector(drm->fb_helper, connector);
1498 drm_connector_register(connector);
1493 return 0; 1499 return 0;
1494} 1500}
1495 1501
@@ -1527,7 +1533,9 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
1527 } 1533 }
1528 1534
1529 dsi->panel = of_drm_find_panel(device->dev.of_node); 1535 dsi->panel = of_drm_find_panel(device->dev.of_node);
1530 if (dsi->panel) { 1536 if (IS_ERR(dsi->panel)) {
1537 dsi->panel = NULL;
1538 } else {
1531 drm_panel_attach(dsi->panel, &dsi->connector); 1539 drm_panel_attach(dsi->panel, &dsi->connector);
1532 dsi->connector.status = connector_status_connected; 1540 dsi->connector.status = connector_status_connected;
1533 } 1541 }
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
index 918dd2c82209..01d182289efa 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
@@ -192,7 +192,7 @@ int exynos_drm_fbdev_init(struct drm_device *dev)
192 struct drm_fb_helper *helper; 192 struct drm_fb_helper *helper;
193 int ret; 193 int ret;
194 194
195 if (!dev->mode_config.num_crtc || !dev->mode_config.num_connector) 195 if (!dev->mode_config.num_crtc)
196 return 0; 196 return 0;
197 197
198 fbdev = kzalloc(sizeof(*fbdev), GFP_KERNEL); 198 fbdev = kzalloc(sizeof(*fbdev), GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 2402395a068d..58e166effa45 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1905,7 +1905,6 @@ static struct intel_vgpu_mm *intel_vgpu_create_ggtt_mm(struct intel_vgpu *vgpu)
1905 vgpu_free_mm(mm); 1905 vgpu_free_mm(mm);
1906 return ERR_PTR(-ENOMEM); 1906 return ERR_PTR(-ENOMEM);
1907 } 1907 }
1908 mm->ggtt_mm.last_partial_off = -1UL;
1909 1908
1910 return mm; 1909 return mm;
1911} 1910}
@@ -1930,7 +1929,6 @@ void _intel_vgpu_mm_release(struct kref *mm_ref)
1930 invalidate_ppgtt_mm(mm); 1929 invalidate_ppgtt_mm(mm);
1931 } else { 1930 } else {
1932 vfree(mm->ggtt_mm.virtual_ggtt); 1931 vfree(mm->ggtt_mm.virtual_ggtt);
1933 mm->ggtt_mm.last_partial_off = -1UL;
1934 } 1932 }
1935 1933
1936 vgpu_free_mm(mm); 1934 vgpu_free_mm(mm);
@@ -2168,6 +2166,8 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
2168 struct intel_gvt_gtt_entry e, m; 2166 struct intel_gvt_gtt_entry e, m;
2169 dma_addr_t dma_addr; 2167 dma_addr_t dma_addr;
2170 int ret; 2168 int ret;
2169 struct intel_gvt_partial_pte *partial_pte, *pos, *n;
2170 bool partial_update = false;
2171 2171
2172 if (bytes != 4 && bytes != 8) 2172 if (bytes != 4 && bytes != 8)
2173 return -EINVAL; 2173 return -EINVAL;
@@ -2178,68 +2178,57 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
2178 if (!vgpu_gmadr_is_valid(vgpu, gma)) 2178 if (!vgpu_gmadr_is_valid(vgpu, gma))
2179 return 0; 2179 return 0;
2180 2180
2181 ggtt_get_guest_entry(ggtt_mm, &e, g_gtt_index); 2181 e.type = GTT_TYPE_GGTT_PTE;
2182
2183 memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data, 2182 memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data,
2184 bytes); 2183 bytes);
2185 2184
2186 /* If ggtt entry size is 8 bytes, and it's split into two 4 bytes 2185 /* If ggtt entry size is 8 bytes, and it's split into two 4 bytes
2187 * write, we assume the two 4 bytes writes are consecutive. 2186 * write, save the first 4 bytes in a list and update virtual
2188 * Otherwise, we abort and report error 2187 * PTE. Only update shadow PTE when the second 4 bytes comes.
2189 */ 2188 */
2190 if (bytes < info->gtt_entry_size) { 2189 if (bytes < info->gtt_entry_size) {
2191 if (ggtt_mm->ggtt_mm.last_partial_off == -1UL) { 2190 bool found = false;
2192 /* the first partial part*/ 2191
2193 ggtt_mm->ggtt_mm.last_partial_off = off; 2192 list_for_each_entry_safe(pos, n,
2194 ggtt_mm->ggtt_mm.last_partial_data = e.val64; 2193 &ggtt_mm->ggtt_mm.partial_pte_list, list) {
2195 return 0; 2194 if (g_gtt_index == pos->offset >>
2196 } else if ((g_gtt_index == 2195 info->gtt_entry_size_shift) {
2197 (ggtt_mm->ggtt_mm.last_partial_off >> 2196 if (off != pos->offset) {
2198 info->gtt_entry_size_shift)) && 2197 /* the second partial part*/
2199 (off != ggtt_mm->ggtt_mm.last_partial_off)) { 2198 int last_off = pos->offset &
2200 /* the second partial part */ 2199 (info->gtt_entry_size - 1);
2201 2200
2202 int last_off = ggtt_mm->ggtt_mm.last_partial_off & 2201 memcpy((void *)&e.val64 + last_off,
2203 (info->gtt_entry_size - 1); 2202 (void *)&pos->data + last_off,
2204 2203 bytes);
2205 memcpy((void *)&e.val64 + last_off, 2204
2206 (void *)&ggtt_mm->ggtt_mm.last_partial_data + 2205 list_del(&pos->list);
2207 last_off, bytes); 2206 kfree(pos);
2208 2207 found = true;
2209 ggtt_mm->ggtt_mm.last_partial_off = -1UL; 2208 break;
2210 } else { 2209 }
2211 int last_offset; 2210
2212 2211 /* update of the first partial part */
2213 gvt_vgpu_err("failed to populate guest ggtt entry: abnormal ggtt entry write sequence, last_partial_off=%lx, offset=%x, bytes=%d, ggtt entry size=%d\n", 2212 pos->data = e.val64;
2214 ggtt_mm->ggtt_mm.last_partial_off, off, 2213 ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2215 bytes, info->gtt_entry_size); 2214 return 0;
2216 2215 }
2217 /* set host ggtt entry to scratch page and clear 2216 }
2218 * virtual ggtt entry as not present for last
2219 * partially write offset
2220 */
2221 last_offset = ggtt_mm->ggtt_mm.last_partial_off &
2222 (~(info->gtt_entry_size - 1));
2223
2224 ggtt_get_host_entry(ggtt_mm, &m, last_offset);
2225 ggtt_invalidate_pte(vgpu, &m);
2226 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2227 ops->clear_present(&m);
2228 ggtt_set_host_entry(ggtt_mm, &m, last_offset);
2229 ggtt_invalidate(gvt->dev_priv);
2230
2231 ggtt_get_guest_entry(ggtt_mm, &e, last_offset);
2232 ops->clear_present(&e);
2233 ggtt_set_guest_entry(ggtt_mm, &e, last_offset);
2234
2235 ggtt_mm->ggtt_mm.last_partial_off = off;
2236 ggtt_mm->ggtt_mm.last_partial_data = e.val64;
2237 2217
2238 return 0; 2218 if (!found) {
2219 /* the first partial part */
2220 partial_pte = kzalloc(sizeof(*partial_pte), GFP_KERNEL);
2221 if (!partial_pte)
2222 return -ENOMEM;
2223 partial_pte->offset = off;
2224 partial_pte->data = e.val64;
2225 list_add_tail(&partial_pte->list,
2226 &ggtt_mm->ggtt_mm.partial_pte_list);
2227 partial_update = true;
2239 } 2228 }
2240 } 2229 }
2241 2230
2242 if (ops->test_present(&e)) { 2231 if (!partial_update && (ops->test_present(&e))) {
2243 gfn = ops->get_pfn(&e); 2232 gfn = ops->get_pfn(&e);
2244 m = e; 2233 m = e;
2245 2234
@@ -2263,16 +2252,18 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
2263 } else 2252 } else
2264 ops->set_pfn(&m, dma_addr >> PAGE_SHIFT); 2253 ops->set_pfn(&m, dma_addr >> PAGE_SHIFT);
2265 } else { 2254 } else {
2266 ggtt_get_host_entry(ggtt_mm, &m, g_gtt_index);
2267 ggtt_invalidate_pte(vgpu, &m);
2268 ops->set_pfn(&m, gvt->gtt.scratch_mfn); 2255 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2269 ops->clear_present(&m); 2256 ops->clear_present(&m);
2270 } 2257 }
2271 2258
2272out: 2259out:
2260 ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2261
2262 ggtt_get_host_entry(ggtt_mm, &e, g_gtt_index);
2263 ggtt_invalidate_pte(vgpu, &e);
2264
2273 ggtt_set_host_entry(ggtt_mm, &m, g_gtt_index); 2265 ggtt_set_host_entry(ggtt_mm, &m, g_gtt_index);
2274 ggtt_invalidate(gvt->dev_priv); 2266 ggtt_invalidate(gvt->dev_priv);
2275 ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2276 return 0; 2267 return 0;
2277} 2268}
2278 2269
@@ -2430,6 +2421,8 @@ int intel_vgpu_init_gtt(struct intel_vgpu *vgpu)
2430 2421
2431 intel_vgpu_reset_ggtt(vgpu, false); 2422 intel_vgpu_reset_ggtt(vgpu, false);
2432 2423
2424 INIT_LIST_HEAD(&gtt->ggtt_mm->ggtt_mm.partial_pte_list);
2425
2433 return create_scratch_page_tree(vgpu); 2426 return create_scratch_page_tree(vgpu);
2434} 2427}
2435 2428
@@ -2454,6 +2447,14 @@ static void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu)
2454 2447
2455static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu) 2448static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu)
2456{ 2449{
2450 struct intel_gvt_partial_pte *pos;
2451
2452 list_for_each_entry(pos,
2453 &vgpu->gtt.ggtt_mm->ggtt_mm.partial_pte_list, list) {
2454 gvt_dbg_mm("partial PTE update on hold 0x%lx : 0x%llx\n",
2455 pos->offset, pos->data);
2456 kfree(pos);
2457 }
2457 intel_vgpu_destroy_mm(vgpu->gtt.ggtt_mm); 2458 intel_vgpu_destroy_mm(vgpu->gtt.ggtt_mm);
2458 vgpu->gtt.ggtt_mm = NULL; 2459 vgpu->gtt.ggtt_mm = NULL;
2459} 2460}
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index 7a9b36176efb..d8cb04cc946d 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -35,7 +35,6 @@
35#define _GVT_GTT_H_ 35#define _GVT_GTT_H_
36 36
37#define I915_GTT_PAGE_SHIFT 12 37#define I915_GTT_PAGE_SHIFT 12
38#define I915_GTT_PAGE_MASK (~(I915_GTT_PAGE_SIZE - 1))
39 38
40struct intel_vgpu_mm; 39struct intel_vgpu_mm;
41 40
@@ -133,6 +132,12 @@ enum intel_gvt_mm_type {
133 132
134#define GVT_RING_CTX_NR_PDPS GEN8_3LVL_PDPES 133#define GVT_RING_CTX_NR_PDPS GEN8_3LVL_PDPES
135 134
135struct intel_gvt_partial_pte {
136 unsigned long offset;
137 u64 data;
138 struct list_head list;
139};
140
136struct intel_vgpu_mm { 141struct intel_vgpu_mm {
137 enum intel_gvt_mm_type type; 142 enum intel_gvt_mm_type type;
138 struct intel_vgpu *vgpu; 143 struct intel_vgpu *vgpu;
@@ -157,8 +162,7 @@ struct intel_vgpu_mm {
157 } ppgtt_mm; 162 } ppgtt_mm;
158 struct { 163 struct {
159 void *virtual_ggtt; 164 void *virtual_ggtt;
160 unsigned long last_partial_off; 165 struct list_head partial_pte_list;
161 u64 last_partial_data;
162 } ggtt_mm; 166 } ggtt_mm;
163 }; 167 };
164}; 168};
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 90f50f67909a..aa280bb07125 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1609,7 +1609,7 @@ static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu,
1609 return 0; 1609 return 0;
1610} 1610}
1611 1611
1612static int bxt_edp_psr_imr_iir_write(struct intel_vgpu *vgpu, 1612static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
1613 unsigned int offset, void *p_data, unsigned int bytes) 1613 unsigned int offset, void *p_data, unsigned int bytes)
1614{ 1614{
1615 vgpu_vreg(vgpu, offset) = 0; 1615 vgpu_vreg(vgpu, offset) = 0;
@@ -2607,6 +2607,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
2607 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2607 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2608 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2608 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2609 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2609 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2610
2611 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2612 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2610 return 0; 2613 return 0;
2611} 2614}
2612 2615
@@ -3205,9 +3208,6 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
3205 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT); 3208 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
3206 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT); 3209 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
3207 3210
3208 MMIO_DH(EDP_PSR_IMR, D_BXT, NULL, bxt_edp_psr_imr_iir_write);
3209 MMIO_DH(EDP_PSR_IIR, D_BXT, NULL, bxt_edp_psr_imr_iir_write);
3210
3211 MMIO_D(RC6_CTX_BASE, D_BXT); 3211 MMIO_D(RC6_CTX_BASE, D_BXT);
3212 3212
3213 MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT); 3213 MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 10e63eea5492..36a5147cd01e 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -131,7 +131,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
131 {RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */ 131 {RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
132 132
133 {RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */ 133 {RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
134 {RCS, GEN9_CSFE_CHICKEN1_RCS, 0x0, false}, /* 0x20d4 */ 134 {RCS, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
135 135
136 {RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */ 136 {RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
137 {RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */ 137 {RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 44e2c0f5ec50..ffdbbac4400e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1175,8 +1175,6 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
1175 return -EINVAL; 1175 return -EINVAL;
1176 } 1176 }
1177 1177
1178 dram_info->valid_dimm = true;
1179
1180 /* 1178 /*
1181 * If any of the channel is single rank channel, worst case output 1179 * If any of the channel is single rank channel, worst case output
1182 * will be same as if single rank memory, so consider single rank 1180 * will be same as if single rank memory, so consider single rank
@@ -1193,8 +1191,7 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
1193 return -EINVAL; 1191 return -EINVAL;
1194 } 1192 }
1195 1193
1196 if (ch0.is_16gb_dimm || ch1.is_16gb_dimm) 1194 dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
1197 dram_info->is_16gb_dimm = true;
1198 1195
1199 dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0, 1196 dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,
1200 val_ch1, 1197 val_ch1,
@@ -1314,7 +1311,6 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
1314 return -EINVAL; 1311 return -EINVAL;
1315 } 1312 }
1316 1313
1317 dram_info->valid_dimm = true;
1318 dram_info->valid = true; 1314 dram_info->valid = true;
1319 return 0; 1315 return 0;
1320} 1316}
@@ -1327,12 +1323,17 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
1327 int ret; 1323 int ret;
1328 1324
1329 dram_info->valid = false; 1325 dram_info->valid = false;
1330 dram_info->valid_dimm = false;
1331 dram_info->is_16gb_dimm = false;
1332 dram_info->rank = I915_DRAM_RANK_INVALID; 1326 dram_info->rank = I915_DRAM_RANK_INVALID;
1333 dram_info->bandwidth_kbps = 0; 1327 dram_info->bandwidth_kbps = 0;
1334 dram_info->num_channels = 0; 1328 dram_info->num_channels = 0;
1335 1329
1330 /*
1331 * Assume 16Gb DIMMs are present until proven otherwise.
1332 * This is only used for the level 0 watermark latency
1333 * w/a which does not apply to bxt/glk.
1334 */
1335 dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1336
1336 if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv)) 1337 if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))
1337 return; 1338 return;
1338 1339
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8624b4bdc242..9102571e9692 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1948,7 +1948,6 @@ struct drm_i915_private {
1948 1948
1949 struct dram_info { 1949 struct dram_info {
1950 bool valid; 1950 bool valid;
1951 bool valid_dimm;
1952 bool is_16gb_dimm; 1951 bool is_16gb_dimm;
1953 u8 num_channels; 1952 u8 num_channels;
1954 enum dram_rank { 1953 enum dram_rank {
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 09187286d346..1aaccbe7e1de 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -460,7 +460,7 @@ eb_validate_vma(struct i915_execbuffer *eb,
460 * any non-page-aligned or non-canonical addresses. 460 * any non-page-aligned or non-canonical addresses.
461 */ 461 */
462 if (unlikely(entry->flags & EXEC_OBJECT_PINNED && 462 if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
463 entry->offset != gen8_canonical_addr(entry->offset & PAGE_MASK))) 463 entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
464 return -EINVAL; 464 return -EINVAL;
465 465
466 /* pad_to_size was once a reserved field, so sanitize it */ 466 /* pad_to_size was once a reserved field, so sanitize it */
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 56c7f8637311..47c302543799 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1757,7 +1757,7 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base, struct seq_file *m)
1757 if (i == 4) 1757 if (i == 4)
1758 continue; 1758 continue;
1759 1759
1760 seq_printf(m, "\t\t(%03d, %04d) %08lx: ", 1760 seq_printf(m, "\t\t(%03d, %04d) %08llx: ",
1761 pde, pte, 1761 pde, pte,
1762 (pde * GEN6_PTES + pte) * I915_GTT_PAGE_SIZE); 1762 (pde * GEN6_PTES + pte) * I915_GTT_PAGE_SIZE);
1763 for (i = 0; i < 4; i++) { 1763 for (i = 0; i < 4; i++) {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 7e2af5f4f39b..28039290655c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -42,13 +42,15 @@
42#include "i915_selftest.h" 42#include "i915_selftest.h"
43#include "i915_timeline.h" 43#include "i915_timeline.h"
44 44
45#define I915_GTT_PAGE_SIZE_4K BIT(12) 45#define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
46#define I915_GTT_PAGE_SIZE_64K BIT(16) 46#define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
47#define I915_GTT_PAGE_SIZE_2M BIT(21) 47#define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
48 48
49#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K 49#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
50#define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M 50#define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
51 51
52#define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
53
52#define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE 54#define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
53 55
54#define I915_FENCE_REG_NONE -1 56#define I915_FENCE_REG_NONE -1
@@ -659,20 +661,20 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
659 u64 start, u64 end, unsigned int flags); 661 u64 start, u64 end, unsigned int flags);
660 662
661/* Flags used by pin/bind&friends. */ 663/* Flags used by pin/bind&friends. */
662#define PIN_NONBLOCK BIT(0) 664#define PIN_NONBLOCK BIT_ULL(0)
663#define PIN_MAPPABLE BIT(1) 665#define PIN_MAPPABLE BIT_ULL(1)
664#define PIN_ZONE_4G BIT(2) 666#define PIN_ZONE_4G BIT_ULL(2)
665#define PIN_NONFAULT BIT(3) 667#define PIN_NONFAULT BIT_ULL(3)
666#define PIN_NOEVICT BIT(4) 668#define PIN_NOEVICT BIT_ULL(4)
667 669
668#define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */ 670#define PIN_MBZ BIT_ULL(5) /* I915_VMA_PIN_OVERFLOW */
669#define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */ 671#define PIN_GLOBAL BIT_ULL(6) /* I915_VMA_GLOBAL_BIND */
670#define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */ 672#define PIN_USER BIT_ULL(7) /* I915_VMA_LOCAL_BIND */
671#define PIN_UPDATE BIT(8) 673#define PIN_UPDATE BIT_ULL(8)
672 674
673#define PIN_HIGH BIT(9) 675#define PIN_HIGH BIT_ULL(9)
674#define PIN_OFFSET_BIAS BIT(10) 676#define PIN_OFFSET_BIAS BIT_ULL(10)
675#define PIN_OFFSET_FIXED BIT(11) 677#define PIN_OFFSET_FIXED BIT_ULL(11)
676#define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE) 678#define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE)
677 679
678#endif 680#endif
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c491ea3d052..e31c27e45734 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2095,8 +2095,12 @@ enum i915_power_well_id {
2095 2095
2096/* ICL PHY DFLEX registers */ 2096/* ICL PHY DFLEX registers */
2097#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0) 2097#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
2098#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n))) 2098#define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
2099#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n))) 2099#define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
2100#define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
2101#define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
2102#define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port)))
2103#define DFLEXDPMLE1_DPMLETC_ML3_0(tc_port) (15 << (4 * (tc_port)))
2100 2104
2101/* BXT PHY Ref registers */ 2105/* BXT PHY Ref registers */
2102#define _PORT_REF_DW3_A 0x16218C 2106#define _PORT_REF_DW3_A 0x16218C
@@ -4593,12 +4597,12 @@ enum {
4593 4597
4594#define DRM_DIP_ENABLE (1 << 28) 4598#define DRM_DIP_ENABLE (1 << 28)
4595#define PSR_VSC_BIT_7_SET (1 << 27) 4599#define PSR_VSC_BIT_7_SET (1 << 27)
4596#define VSC_SELECT_MASK (0x3 << 26) 4600#define VSC_SELECT_MASK (0x3 << 25)
4597#define VSC_SELECT_SHIFT 26 4601#define VSC_SELECT_SHIFT 25
4598#define VSC_DIP_HW_HEA_DATA (0 << 26) 4602#define VSC_DIP_HW_HEA_DATA (0 << 25)
4599#define VSC_DIP_HW_HEA_SW_DATA (1 << 26) 4603#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
4600#define VSC_DIP_HW_DATA_SW_HEA (2 << 26) 4604#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
4601#define VSC_DIP_SW_HEA_DATA (3 << 26) 4605#define VSC_DIP_SW_HEA_DATA (3 << 25)
4602#define VDIP_ENABLE_PPS (1 << 24) 4606#define VDIP_ENABLE_PPS (1 << 24)
4603 4607
4604/* Panel power sequencing */ 4608/* Panel power sequencing */
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 769f3f586661..ee3ca2de983b 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -144,6 +144,9 @@ static const struct {
144/* HDMI N/CTS table */ 144/* HDMI N/CTS table */
145#define TMDS_297M 297000 145#define TMDS_297M 297000
146#define TMDS_296M 296703 146#define TMDS_296M 296703
147#define TMDS_594M 594000
148#define TMDS_593M 593407
149
147static const struct { 150static const struct {
148 int sample_rate; 151 int sample_rate;
149 int clock; 152 int clock;
@@ -164,6 +167,20 @@ static const struct {
164 { 176400, TMDS_297M, 18816, 247500 }, 167 { 176400, TMDS_297M, 18816, 247500 },
165 { 192000, TMDS_296M, 23296, 281250 }, 168 { 192000, TMDS_296M, 23296, 281250 },
166 { 192000, TMDS_297M, 20480, 247500 }, 169 { 192000, TMDS_297M, 20480, 247500 },
170 { 44100, TMDS_593M, 8918, 937500 },
171 { 44100, TMDS_594M, 9408, 990000 },
172 { 48000, TMDS_593M, 5824, 562500 },
173 { 48000, TMDS_594M, 6144, 594000 },
174 { 32000, TMDS_593M, 5824, 843750 },
175 { 32000, TMDS_594M, 3072, 445500 },
176 { 88200, TMDS_593M, 17836, 937500 },
177 { 88200, TMDS_594M, 18816, 990000 },
178 { 96000, TMDS_593M, 11648, 562500 },
179 { 96000, TMDS_594M, 12288, 594000 },
180 { 176400, TMDS_593M, 35672, 937500 },
181 { 176400, TMDS_594M, 37632, 990000 },
182 { 192000, TMDS_593M, 23296, 562500 },
183 { 192000, TMDS_594M, 24576, 594000 },
167}; 184};
168 185
169/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 186/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 29075c763428..8d74276029e6 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2138,16 +2138,8 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv,
2138static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv, 2138static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
2139 int pixel_rate) 2139 int pixel_rate)
2140{ 2140{
2141 if (INTEL_GEN(dev_priv) >= 10) 2141 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2142 return DIV_ROUND_UP(pixel_rate, 2); 2142 return DIV_ROUND_UP(pixel_rate, 2);
2143 else if (IS_GEMINILAKE(dev_priv))
2144 /*
2145 * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
2146 * as a temporary workaround. Use a higher cdclk instead. (Note that
2147 * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
2148 * cdclk.)
2149 */
2150 return DIV_ROUND_UP(pixel_rate * 100, 2 * 99);
2151 else if (IS_GEN9(dev_priv) || 2143 else if (IS_GEN9(dev_priv) ||
2152 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2144 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2153 return pixel_rate; 2145 return pixel_rate;
@@ -2543,14 +2535,8 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2543{ 2535{
2544 int max_cdclk_freq = dev_priv->max_cdclk_freq; 2536 int max_cdclk_freq = dev_priv->max_cdclk_freq;
2545 2537
2546 if (INTEL_GEN(dev_priv) >= 10) 2538 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2547 return 2 * max_cdclk_freq; 2539 return 2 * max_cdclk_freq;
2548 else if (IS_GEMINILAKE(dev_priv))
2549 /*
2550 * FIXME: Limiting to 99% as a temporary workaround. See
2551 * intel_min_cdclk() for details.
2552 */
2553 return 2 * max_cdclk_freq * 99 / 100;
2554 else if (IS_GEN9(dev_priv) || 2540 else if (IS_GEN9(dev_priv) ||
2555 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2541 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2556 return max_cdclk_freq; 2542 return max_cdclk_freq;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9741cc419e1b..23d8008a93bb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12768,17 +12768,12 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12768 intel_check_cpu_fifo_underruns(dev_priv); 12768 intel_check_cpu_fifo_underruns(dev_priv);
12769 intel_check_pch_fifo_underruns(dev_priv); 12769 intel_check_pch_fifo_underruns(dev_priv);
12770 12770
12771 if (!new_crtc_state->active) { 12771 /* FIXME unify this for all platforms */
12772 /* 12772 if (!new_crtc_state->active &&
12773 * Make sure we don't call initial_watermarks 12773 !HAS_GMCH_DISPLAY(dev_priv) &&
12774 * for ILK-style watermark updates. 12774 dev_priv->display.initial_watermarks)
12775 * 12775 dev_priv->display.initial_watermarks(intel_state,
12776 * No clue what this is supposed to achieve. 12776 to_intel_crtc_state(new_crtc_state));
12777 */
12778 if (INTEL_GEN(dev_priv) >= 9)
12779 dev_priv->display.initial_watermarks(intel_state,
12780 to_intel_crtc_state(new_crtc_state));
12781 }
12782 } 12777 }
12783 } 12778 }
12784 12779
@@ -14646,7 +14641,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14646 fb->height < SKL_MIN_YUV_420_SRC_H || 14641 fb->height < SKL_MIN_YUV_420_SRC_H ||
14647 (fb->width % 4) != 0 || (fb->height % 4) != 0)) { 14642 (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
14648 DRM_DEBUG_KMS("src dimensions not correct for NV12\n"); 14643 DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
14649 return -EINVAL; 14644 goto err;
14650 } 14645 }
14651 14646
14652 for (i = 0; i < fb->format->num_planes; i++) { 14647 for (i = 0; i < fb->format->num_planes; i++) {
diff --git a/drivers/gpu/drm/i915/intel_lpe_audio.c b/drivers/gpu/drm/i915/intel_lpe_audio.c
index cdf19553ffac..5d5336fbe7b0 100644
--- a/drivers/gpu/drm/i915/intel_lpe_audio.c
+++ b/drivers/gpu/drm/i915/intel_lpe_audio.c
@@ -297,8 +297,10 @@ void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv)
297 lpe_audio_platdev_destroy(dev_priv); 297 lpe_audio_platdev_destroy(dev_priv);
298 298
299 irq_free_desc(dev_priv->lpe_audio.irq); 299 irq_free_desc(dev_priv->lpe_audio.irq);
300}
301 300
301 dev_priv->lpe_audio.irq = -1;
302 dev_priv->lpe_audio.platdev = NULL;
303}
302 304
303/** 305/**
304 * intel_lpe_audio_notify() - notify lpe audio event 306 * intel_lpe_audio_notify() - notify lpe audio event
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1db9b8328275..245f0022bcfd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2881,8 +2881,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2881 * any underrun. If not able to get Dimm info assume 16GB dimm 2881 * any underrun. If not able to get Dimm info assume 16GB dimm
2882 * to avoid any underrun. 2882 * to avoid any underrun.
2883 */ 2883 */
2884 if (!dev_priv->dram_info.valid_dimm || 2884 if (dev_priv->dram_info.is_16gb_dimm)
2885 dev_priv->dram_info.is_16gb_dimm)
2886 wm[0] += 1; 2885 wm[0] += 1;
2887 2886
2888 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 2887 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 8d03f64eabd7..5c22f2c8d4cf 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -551,7 +551,7 @@ static int igt_mock_ppgtt_misaligned_dma(void *arg)
551 err = igt_check_page_sizes(vma); 551 err = igt_check_page_sizes(vma);
552 552
553 if (vma->page_sizes.gtt != I915_GTT_PAGE_SIZE_4K) { 553 if (vma->page_sizes.gtt != I915_GTT_PAGE_SIZE_4K) {
554 pr_err("page_sizes.gtt=%u, expected %lu\n", 554 pr_err("page_sizes.gtt=%u, expected %llu\n",
555 vma->page_sizes.gtt, I915_GTT_PAGE_SIZE_4K); 555 vma->page_sizes.gtt, I915_GTT_PAGE_SIZE_4K);
556 err = -EINVAL; 556 err = -EINVAL;
557 } 557 }
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 8e2e269db97e..127d81513671 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1337,7 +1337,7 @@ static int igt_gtt_reserve(void *arg)
1337 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); 1337 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1338 if (vma->node.start != total || 1338 if (vma->node.start != total ||
1339 vma->node.size != 2*I915_GTT_PAGE_SIZE) { 1339 vma->node.size != 2*I915_GTT_PAGE_SIZE) {
1340 pr_err("i915_gem_gtt_reserve (pass 1) placement failed, found (%llx + %llx), expected (%llx + %lx)\n", 1340 pr_err("i915_gem_gtt_reserve (pass 1) placement failed, found (%llx + %llx), expected (%llx + %llx)\n",
1341 vma->node.start, vma->node.size, 1341 vma->node.start, vma->node.size,
1342 total, 2*I915_GTT_PAGE_SIZE); 1342 total, 2*I915_GTT_PAGE_SIZE);
1343 err = -EINVAL; 1343 err = -EINVAL;
@@ -1386,7 +1386,7 @@ static int igt_gtt_reserve(void *arg)
1386 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); 1386 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1387 if (vma->node.start != total || 1387 if (vma->node.start != total ||
1388 vma->node.size != 2*I915_GTT_PAGE_SIZE) { 1388 vma->node.size != 2*I915_GTT_PAGE_SIZE) {
1389 pr_err("i915_gem_gtt_reserve (pass 2) placement failed, found (%llx + %llx), expected (%llx + %lx)\n", 1389 pr_err("i915_gem_gtt_reserve (pass 2) placement failed, found (%llx + %llx), expected (%llx + %llx)\n",
1390 vma->node.start, vma->node.size, 1390 vma->node.start, vma->node.size,
1391 total, 2*I915_GTT_PAGE_SIZE); 1391 total, 2*I915_GTT_PAGE_SIZE);
1392 err = -EINVAL; 1392 err = -EINVAL;
@@ -1430,7 +1430,7 @@ static int igt_gtt_reserve(void *arg)
1430 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); 1430 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1431 if (vma->node.start != offset || 1431 if (vma->node.start != offset ||
1432 vma->node.size != 2*I915_GTT_PAGE_SIZE) { 1432 vma->node.size != 2*I915_GTT_PAGE_SIZE) {
1433 pr_err("i915_gem_gtt_reserve (pass 3) placement failed, found (%llx + %llx), expected (%llx + %lx)\n", 1433 pr_err("i915_gem_gtt_reserve (pass 3) placement failed, found (%llx + %llx), expected (%llx + %llx)\n",
1434 vma->node.start, vma->node.size, 1434 vma->node.start, vma->node.size,
1435 offset, 2*I915_GTT_PAGE_SIZE); 1435 offset, 2*I915_GTT_PAGE_SIZE);
1436 err = -EINVAL; 1436 err = -EINVAL;
diff --git a/drivers/gpu/drm/sun4i/sun4i_lvds.c b/drivers/gpu/drm/sun4i/sun4i_lvds.c
index af7dcb6da351..e7eb0d1e17be 100644
--- a/drivers/gpu/drm/sun4i/sun4i_lvds.c
+++ b/drivers/gpu/drm/sun4i/sun4i_lvds.c
@@ -75,7 +75,7 @@ static void sun4i_lvds_encoder_enable(struct drm_encoder *encoder)
75 75
76 DRM_DEBUG_DRIVER("Enabling LVDS output\n"); 76 DRM_DEBUG_DRIVER("Enabling LVDS output\n");
77 77
78 if (!IS_ERR(tcon->panel)) { 78 if (tcon->panel) {
79 drm_panel_prepare(tcon->panel); 79 drm_panel_prepare(tcon->panel);
80 drm_panel_enable(tcon->panel); 80 drm_panel_enable(tcon->panel);
81 } 81 }
@@ -88,7 +88,7 @@ static void sun4i_lvds_encoder_disable(struct drm_encoder *encoder)
88 88
89 DRM_DEBUG_DRIVER("Disabling LVDS output\n"); 89 DRM_DEBUG_DRIVER("Disabling LVDS output\n");
90 90
91 if (!IS_ERR(tcon->panel)) { 91 if (tcon->panel) {
92 drm_panel_disable(tcon->panel); 92 drm_panel_disable(tcon->panel);
93 drm_panel_unprepare(tcon->panel); 93 drm_panel_unprepare(tcon->panel);
94 } 94 }
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c b/drivers/gpu/drm/sun4i/sun4i_rgb.c
index bf068da6b12e..f4a22689eb54 100644
--- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
@@ -135,7 +135,7 @@ static void sun4i_rgb_encoder_enable(struct drm_encoder *encoder)
135 135
136 DRM_DEBUG_DRIVER("Enabling RGB output\n"); 136 DRM_DEBUG_DRIVER("Enabling RGB output\n");
137 137
138 if (!IS_ERR(tcon->panel)) { 138 if (tcon->panel) {
139 drm_panel_prepare(tcon->panel); 139 drm_panel_prepare(tcon->panel);
140 drm_panel_enable(tcon->panel); 140 drm_panel_enable(tcon->panel);
141 } 141 }
@@ -148,7 +148,7 @@ static void sun4i_rgb_encoder_disable(struct drm_encoder *encoder)
148 148
149 DRM_DEBUG_DRIVER("Disabling RGB output\n"); 149 DRM_DEBUG_DRIVER("Disabling RGB output\n");
150 150
151 if (!IS_ERR(tcon->panel)) { 151 if (tcon->panel) {
152 drm_panel_disable(tcon->panel); 152 drm_panel_disable(tcon->panel);
153 drm_panel_unprepare(tcon->panel); 153 drm_panel_unprepare(tcon->panel);
154 } 154 }
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index c78cd35a1294..f949287d926c 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -491,7 +491,8 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
491 sun4i_tcon0_mode_set_common(tcon, mode); 491 sun4i_tcon0_mode_set_common(tcon, mode);
492 492
493 /* Set dithering if needed */ 493 /* Set dithering if needed */
494 sun4i_tcon0_mode_set_dithering(tcon, tcon->panel->connector); 494 if (tcon->panel)
495 sun4i_tcon0_mode_set_dithering(tcon, tcon->panel->connector);
495 496
496 /* Adjust clock delay */ 497 /* Adjust clock delay */
497 clk_delay = sun4i_tcon_get_clk_delay(mode, 0); 498 clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
@@ -555,7 +556,7 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
555 * Following code is a way to avoid quirks all around TCON 556 * Following code is a way to avoid quirks all around TCON
556 * and DOTCLOCK drivers. 557 * and DOTCLOCK drivers.
557 */ 558 */
558 if (!IS_ERR(tcon->panel)) { 559 if (tcon->panel) {
559 struct drm_panel *panel = tcon->panel; 560 struct drm_panel *panel = tcon->panel;
560 struct drm_connector *connector = panel->connector; 561 struct drm_connector *connector = panel->connector;
561 struct drm_display_info display_info = connector->display_info; 562 struct drm_display_info display_info = connector->display_info;
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index f5ff8a76e208..b01eb502d49c 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -83,11 +83,11 @@ struct kfd_ioctl_set_cu_mask_args {
83}; 83};
84 84
85struct kfd_ioctl_get_queue_wave_state_args { 85struct kfd_ioctl_get_queue_wave_state_args {
86 uint64_t ctl_stack_address; /* to KFD */ 86 __u64 ctl_stack_address; /* to KFD */
87 uint32_t ctl_stack_used_size; /* from KFD */ 87 __u32 ctl_stack_used_size; /* from KFD */
88 uint32_t save_area_used_size; /* from KFD */ 88 __u32 save_area_used_size; /* from KFD */
89 uint32_t queue_id; /* to KFD */ 89 __u32 queue_id; /* to KFD */
90 uint32_t pad; 90 __u32 pad;
91}; 91};
92 92
93/* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */ 93/* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
@@ -255,10 +255,10 @@ struct kfd_hsa_memory_exception_data {
255 255
256/* hw exception data */ 256/* hw exception data */
257struct kfd_hsa_hw_exception_data { 257struct kfd_hsa_hw_exception_data {
258 uint32_t reset_type; 258 __u32 reset_type;
259 uint32_t reset_cause; 259 __u32 reset_cause;
260 uint32_t memory_lost; 260 __u32 memory_lost;
261 uint32_t gpu_id; 261 __u32 gpu_id;
262}; 262};
263 263
264/* Event data */ 264/* Event data */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-29 21:31:11 -0500