aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/spi/Kconfig8
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/spi-bcm53xx.c299
-rw-r--r--drivers/spi/spi-bcm53xx.h72
-rw-r--r--drivers/spi/spi-cadence.c1
-rw-r--r--drivers/spi/spi-clps711x.c34
-rw-r--r--drivers/spi/spi-davinci.c8
-rw-r--r--drivers/spi/spi-dw.c16
-rw-r--r--drivers/spi/spi-ep93xx.c1
-rw-r--r--drivers/spi/spi-mxs.c4
-rw-r--r--drivers/spi/spi-orion.c5
-rw-r--r--drivers/spi/spi-tegra114.c9
-rw-r--r--drivers/spi/spi-tegra20-sflash.c3
-rw-r--r--drivers/spi/spi-txx9.c2
-rw-r--r--drivers/spi/spi-xtensa-xtfpga.c1
15 files changed, 418 insertions, 46 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index db2a50b53f5b..a862a1c8eb29 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -113,6 +113,14 @@ config SPI_AU1550
113 If you say yes to this option, support will be included for the 113 If you say yes to this option, support will be included for the
114 PSC SPI controller found on Au1550, Au1200 and Au1300 series. 114 PSC SPI controller found on Au1550, Au1200 and Au1300 series.
115 115
116config SPI_BCM53XX
117 tristate "Broadcom BCM53xx SPI controller"
118 depends on ARCH_BCM_5301X
119 depends on BCMA_POSSIBLE
120 select BCMA
121 help
122 Enable support for the SPI controller on Broadcom BCM53xx ARM SoCs.
123
116config SPI_BCM63XX 124config SPI_BCM63XX
117 tristate "Broadcom BCM63xx SPI controller" 125 tristate "Broadcom BCM63xx SPI controller"
118 depends on BCM63XX 126 depends on BCM63XX
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 762da0741148..78f24ca36fcf 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
15obj-$(CONFIG_SPI_ATH79) += spi-ath79.o 15obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
16obj-$(CONFIG_SPI_AU1550) += spi-au1550.o 16obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
17obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o 17obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o
18obj-$(CONFIG_SPI_BCM53XX) += spi-bcm53xx.o
18obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o 19obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
19obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o 20obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
20obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o 21obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
diff --git a/drivers/spi/spi-bcm53xx.c b/drivers/spi/spi-bcm53xx.c
new file mode 100644
index 000000000000..17b34cbadc03
--- /dev/null
+++ b/drivers/spi/spi-bcm53xx.c
@@ -0,0 +1,299 @@
1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
3#include <linux/kernel.h>
4#include <linux/module.h>
5#include <linux/slab.h>
6#include <linux/delay.h>
7#include <linux/bcma/bcma.h>
8#include <linux/spi/spi.h>
9
10#include "spi-bcm53xx.h"
11
12#define BCM53XXSPI_MAX_SPI_BAUD 13500000 /* 216 MHz? */
13
14/* The longest observed required wait was 19 ms */
15#define BCM53XXSPI_SPE_TIMEOUT_MS 80
16
17struct bcm53xxspi {
18 struct bcma_device *core;
19 struct spi_master *master;
20
21 size_t read_offset;
22};
23
24static inline u32 bcm53xxspi_read(struct bcm53xxspi *b53spi, u16 offset)
25{
26 return bcma_read32(b53spi->core, offset);
27}
28
29static inline void bcm53xxspi_write(struct bcm53xxspi *b53spi, u16 offset,
30 u32 value)
31{
32 bcma_write32(b53spi->core, offset, value);
33}
34
35static inline unsigned int bcm53xxspi_calc_timeout(size_t len)
36{
37 /* Do some magic calculation based on length and buad. Add 10% and 1. */
38 return (len * 9000 / BCM53XXSPI_MAX_SPI_BAUD * 110 / 100) + 1;
39}
40
41static int bcm53xxspi_wait(struct bcm53xxspi *b53spi, unsigned int timeout_ms)
42{
43 unsigned long deadline;
44 u32 tmp;
45
46 /* SPE bit has to be 0 before we read MSPI STATUS */
47 deadline = jiffies + BCM53XXSPI_SPE_TIMEOUT_MS * HZ / 1000;
48 do {
49 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
50 if (!(tmp & B53SPI_MSPI_SPCR2_SPE))
51 break;
52 udelay(5);
53 } while (!time_after_eq(jiffies, deadline));
54
55 if (tmp & B53SPI_MSPI_SPCR2_SPE)
56 goto spi_timeout;
57
58 /* Check status */
59 deadline = jiffies + timeout_ms * HZ / 1000;
60 do {
61 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_MSPI_STATUS);
62 if (tmp & B53SPI_MSPI_MSPI_STATUS_SPIF) {
63 bcm53xxspi_write(b53spi, B53SPI_MSPI_MSPI_STATUS, 0);
64 return 0;
65 }
66
67 cpu_relax();
68 udelay(100);
69 } while (!time_after_eq(jiffies, deadline));
70
71spi_timeout:
72 bcm53xxspi_write(b53spi, B53SPI_MSPI_MSPI_STATUS, 0);
73
74 pr_err("Timeout waiting for SPI to be ready!\n");
75
76 return -EBUSY;
77}
78
79static void bcm53xxspi_buf_write(struct bcm53xxspi *b53spi, u8 *w_buf,
80 size_t len, bool cont)
81{
82 u32 tmp;
83 int i;
84
85 for (i = 0; i < len; i++) {
86 /* Transmit Register File MSB */
87 bcm53xxspi_write(b53spi, B53SPI_MSPI_TXRAM + 4 * (i * 2),
88 (unsigned int)w_buf[i]);
89 }
90
91 for (i = 0; i < len; i++) {
92 tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL |
93 B53SPI_CDRAM_PCS_DSCK;
94 if (!cont && i == len - 1)
95 tmp &= ~B53SPI_CDRAM_CONT;
96 tmp &= ~0x1;
97 /* Command Register File */
98 bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp);
99 }
100
101 /* Set queue pointers */
102 bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0);
103 bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP, len - 1);
104
105 if (cont)
106 bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1);
107
108 /* Start SPI transfer */
109 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
110 tmp |= B53SPI_MSPI_SPCR2_SPE;
111 if (cont)
112 tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD;
113 bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp);
114
115 /* Wait for SPI to finish */
116 bcm53xxspi_wait(b53spi, bcm53xxspi_calc_timeout(len));
117
118 if (!cont)
119 bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
120
121 b53spi->read_offset = len;
122}
123
124static void bcm53xxspi_buf_read(struct bcm53xxspi *b53spi, u8 *r_buf,
125 size_t len, bool cont)
126{
127 u32 tmp;
128 int i;
129
130 for (i = 0; i < b53spi->read_offset + len; i++) {
131 tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL |
132 B53SPI_CDRAM_PCS_DSCK;
133 if (!cont && i == b53spi->read_offset + len - 1)
134 tmp &= ~B53SPI_CDRAM_CONT;
135 tmp &= ~0x1;
136 /* Command Register File */
137 bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp);
138 }
139
140 /* Set queue pointers */
141 bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0);
142 bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP,
143 b53spi->read_offset + len - 1);
144
145 if (cont)
146 bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1);
147
148 /* Start SPI transfer */
149 tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
150 tmp |= B53SPI_MSPI_SPCR2_SPE;
151 if (cont)
152 tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD;
153 bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp);
154
155 /* Wait for SPI to finish */
156 bcm53xxspi_wait(b53spi, bcm53xxspi_calc_timeout(len));
157
158 if (!cont)
159 bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
160
161 for (i = 0; i < len; ++i) {
162 int offset = b53spi->read_offset + i;
163
164 /* Data stored in the transmit register file LSB */
165 r_buf[i] = (u8)bcm53xxspi_read(b53spi, B53SPI_MSPI_RXRAM + 4 * (1 + offset * 2));
166 }
167
168 b53spi->read_offset = 0;
169}
170
171static int bcm53xxspi_transfer_one(struct spi_master *master,
172 struct spi_device *spi,
173 struct spi_transfer *t)
174{
175 struct bcm53xxspi *b53spi = spi_master_get_devdata(master);
176 u8 *buf;
177 size_t left;
178
179 if (t->tx_buf) {
180 buf = (u8 *)t->tx_buf;
181 left = t->len;
182 while (left) {
183 size_t to_write = min_t(size_t, 16, left);
184 bool cont = left - to_write > 0;
185
186 bcm53xxspi_buf_write(b53spi, buf, to_write, cont);
187 left -= to_write;
188 buf += to_write;
189 }
190 }
191
192 if (t->rx_buf) {
193 buf = (u8 *)t->rx_buf;
194 left = t->len;
195 while (left) {
196 size_t to_read = min_t(size_t, 16 - b53spi->read_offset,
197 left);
198 bool cont = left - to_read > 0;
199
200 bcm53xxspi_buf_read(b53spi, buf, to_read, cont);
201 left -= to_read;
202 buf += to_read;
203 }
204 }
205
206 return 0;
207}
208
209/**************************************************
210 * BCMA
211 **************************************************/
212
213static struct spi_board_info bcm53xx_info = {
214 .modalias = "bcm53xxspiflash",
215};
216
217static const struct bcma_device_id bcm53xxspi_bcma_tbl[] = {
218 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_QSPI, BCMA_ANY_REV, BCMA_ANY_CLASS),
219 BCMA_CORETABLE_END
220};
221MODULE_DEVICE_TABLE(bcma, bcm53xxspi_bcma_tbl);
222
223static int bcm53xxspi_bcma_probe(struct bcma_device *core)
224{
225 struct bcm53xxspi *b53spi;
226 struct spi_master *master;
227 int err;
228
229 if (core->bus->drv_cc.core->id.rev != 42) {
230 pr_err("SPI on SoC with unsupported ChipCommon rev\n");
231 return -ENOTSUPP;
232 }
233
234 master = spi_alloc_master(&core->dev, sizeof(*b53spi));
235 if (!master)
236 return -ENOMEM;
237
238 b53spi = spi_master_get_devdata(master);
239 b53spi->master = master;
240 b53spi->core = core;
241
242 master->transfer_one = bcm53xxspi_transfer_one;
243
244 bcma_set_drvdata(core, b53spi);
245
246 err = devm_spi_register_master(&core->dev, master);
247 if (err) {
248 spi_master_put(master);
249 bcma_set_drvdata(core, NULL);
250 goto out;
251 }
252
253 /* Broadcom SoCs (at least with the CC rev 42) use SPI for flash only */
254 spi_new_device(master, &bcm53xx_info);
255
256out:
257 return err;
258}
259
260static void bcm53xxspi_bcma_remove(struct bcma_device *core)
261{
262 struct bcm53xxspi *b53spi = bcma_get_drvdata(core);
263
264 spi_unregister_master(b53spi->master);
265}
266
267static struct bcma_driver bcm53xxspi_bcma_driver = {
268 .name = KBUILD_MODNAME,
269 .id_table = bcm53xxspi_bcma_tbl,
270 .probe = bcm53xxspi_bcma_probe,
271 .remove = bcm53xxspi_bcma_remove,
272};
273
274/**************************************************
275 * Init & exit
276 **************************************************/
277
278static int __init bcm53xxspi_module_init(void)
279{
280 int err = 0;
281
282 err = bcma_driver_register(&bcm53xxspi_bcma_driver);
283 if (err)
284 pr_err("Failed to register bcma driver: %d\n", err);
285
286 return err;
287}
288
289static void __exit bcm53xxspi_module_exit(void)
290{
291 bcma_driver_unregister(&bcm53xxspi_bcma_driver);
292}
293
294module_init(bcm53xxspi_module_init);
295module_exit(bcm53xxspi_module_exit);
296
297MODULE_DESCRIPTION("Broadcom BCM53xx SPI Controller driver");
298MODULE_AUTHOR("Rafał Miłecki <zajec5@gmail.com>");
299MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi-bcm53xx.h b/drivers/spi/spi-bcm53xx.h
new file mode 100644
index 000000000000..73575dfe6916
--- /dev/null
+++ b/drivers/spi/spi-bcm53xx.h
@@ -0,0 +1,72 @@
1#ifndef SPI_BCM53XX_H
2#define SPI_BCM53XX_H
3
4#define B53SPI_BSPI_REVISION_ID 0x000
5#define B53SPI_BSPI_SCRATCH 0x004
6#define B53SPI_BSPI_MAST_N_BOOT_CTRL 0x008
7#define B53SPI_BSPI_BUSY_STATUS 0x00c
8#define B53SPI_BSPI_INTR_STATUS 0x010
9#define B53SPI_BSPI_B0_STATUS 0x014
10#define B53SPI_BSPI_B0_CTRL 0x018
11#define B53SPI_BSPI_B1_STATUS 0x01c
12#define B53SPI_BSPI_B1_CTRL 0x020
13#define B53SPI_BSPI_STRAP_OVERRIDE_CTRL 0x024
14#define B53SPI_BSPI_FLEX_MODE_ENABLE 0x028
15#define B53SPI_BSPI_BITS_PER_CYCLE 0x02c
16#define B53SPI_BSPI_BITS_PER_PHASE 0x030
17#define B53SPI_BSPI_CMD_AND_MODE_BYTE 0x034
18#define B53SPI_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038
19#define B53SPI_BSPI_BSPI_XOR_VALUE 0x03c
20#define B53SPI_BSPI_BSPI_XOR_ENABLE 0x040
21#define B53SPI_BSPI_BSPI_PIO_MODE_ENABLE 0x044
22#define B53SPI_BSPI_BSPI_PIO_IODIR 0x048
23#define B53SPI_BSPI_BSPI_PIO_DATA 0x04c
24
25/* RAF */
26#define B53SPI_RAF_START_ADDR 0x100
27#define B53SPI_RAF_NUM_WORDS 0x104
28#define B53SPI_RAF_CTRL 0x108
29#define B53SPI_RAF_FULLNESS 0x10c
30#define B53SPI_RAF_WATERMARK 0x110
31#define B53SPI_RAF_STATUS 0x114
32#define B53SPI_RAF_READ_DATA 0x118
33#define B53SPI_RAF_WORD_CNT 0x11c
34#define B53SPI_RAF_CURR_ADDR 0x120
35
36/* MSPI */
37#define B53SPI_MSPI_SPCR0_LSB 0x200
38#define B53SPI_MSPI_SPCR0_MSB 0x204
39#define B53SPI_MSPI_SPCR1_LSB 0x208
40#define B53SPI_MSPI_SPCR1_MSB 0x20c
41#define B53SPI_MSPI_NEWQP 0x210
42#define B53SPI_MSPI_ENDQP 0x214
43#define B53SPI_MSPI_SPCR2 0x218
44#define B53SPI_MSPI_SPCR2_SPE 0x00000040
45#define B53SPI_MSPI_SPCR2_CONT_AFTER_CMD 0x00000080
46#define B53SPI_MSPI_MSPI_STATUS 0x220
47#define B53SPI_MSPI_MSPI_STATUS_SPIF 0x00000001
48#define B53SPI_MSPI_CPTQP 0x224
49#define B53SPI_MSPI_TXRAM 0x240 /* 32 registers, up to 0x2b8 */
50#define B53SPI_MSPI_RXRAM 0x2c0 /* 32 registers, up to 0x33c */
51#define B53SPI_MSPI_CDRAM 0x340 /* 16 registers, up to 0x37c */
52#define B53SPI_CDRAM_PCS_PCS0 0x00000001
53#define B53SPI_CDRAM_PCS_PCS1 0x00000002
54#define B53SPI_CDRAM_PCS_PCS2 0x00000004
55#define B53SPI_CDRAM_PCS_PCS3 0x00000008
56#define B53SPI_CDRAM_PCS_DISABLE_ALL 0x0000000f
57#define B53SPI_CDRAM_PCS_DSCK 0x00000010
58#define B53SPI_CDRAM_BITSE 0x00000040
59#define B53SPI_CDRAM_CONT 0x00000080
60#define B53SPI_MSPI_WRITE_LOCK 0x380
61#define B53SPI_MSPI_DISABLE_FLUSH_GEN 0x384
62
63/* Interrupt */
64#define B53SPI_INTR_RAF_LR_FULLNESS_REACHED 0x3a0
65#define B53SPI_INTR_RAF_LR_TRUNCATED 0x3a4
66#define B53SPI_INTR_RAF_LR_IMPATIENT 0x3a8
67#define B53SPI_INTR_RAF_LR_SESSION_DONE 0x3ac
68#define B53SPI_INTR_RAF_LR_OVERREAD 0x3b0
69#define B53SPI_INTR_MSPI_DONE 0x3b4
70#define B53SPI_INTR_MSPI_HALT_SET_TRANSACTION_DONE 0x3b8
71
72#endif /* SPI_BCM53XX_H */
diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index 562ff83debd9..7b811e38c7ad 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -677,7 +677,6 @@ static struct platform_driver cdns_spi_driver = {
677 .remove = cdns_spi_remove, 677 .remove = cdns_spi_remove,
678 .driver = { 678 .driver = {
679 .name = CDNS_SPI_NAME, 679 .name = CDNS_SPI_NAME,
680 .owner = THIS_MODULE,
681 .of_match_table = cdns_spi_of_match, 680 .of_match_table = cdns_spi_of_match,
682 .pm = &cdns_spi_dev_pm_ops, 681 .pm = &cdns_spi_dev_pm_ops,
683 }, 682 },
diff --git a/drivers/spi/spi-clps711x.c b/drivers/spi/spi-clps711x.c
index ce538dad526b..181cf2262006 100644
--- a/drivers/spi/spi-clps711x.c
+++ b/drivers/spi/spi-clps711x.c
@@ -30,7 +30,6 @@
30struct spi_clps711x_data { 30struct spi_clps711x_data {
31 void __iomem *syncio; 31 void __iomem *syncio;
32 struct regmap *syscon; 32 struct regmap *syscon;
33 struct regmap *syscon1;
34 struct clk *spi_clk; 33 struct clk *spi_clk;
35 34
36 u8 *tx_buf; 35 u8 *tx_buf;
@@ -47,27 +46,6 @@ static int spi_clps711x_setup(struct spi_device *spi)
47 return 0; 46 return 0;
48} 47}
49 48
50static void spi_clps711x_setup_xfer(struct spi_device *spi,
51 struct spi_transfer *xfer)
52{
53 struct spi_master *master = spi->master;
54 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
55
56 /* Setup SPI frequency divider */
57 if (xfer->speed_hz >= master->max_speed_hz)
58 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
59 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(3));
60 else if (xfer->speed_hz >= (master->max_speed_hz / 2))
61 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
62 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(2));
63 else if (xfer->speed_hz >= (master->max_speed_hz / 8))
64 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
65 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(1));
66 else
67 regmap_update_bits(hw->syscon1, SYSCON_OFFSET,
68 SYSCON1_ADCKSEL_MASK, SYSCON1_ADCKSEL(0));
69}
70
71static int spi_clps711x_prepare_message(struct spi_master *master, 49static int spi_clps711x_prepare_message(struct spi_master *master,
72 struct spi_message *msg) 50 struct spi_message *msg)
73{ 51{
@@ -87,7 +65,7 @@ static int spi_clps711x_transfer_one(struct spi_master *master,
87 struct spi_clps711x_data *hw = spi_master_get_devdata(master); 65 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
88 u8 data; 66 u8 data;
89 67
90 spi_clps711x_setup_xfer(spi, xfer); 68 clk_set_rate(hw->spi_clk, xfer->speed_hz ? : spi->max_speed_hz);
91 69
92 hw->len = xfer->len; 70 hw->len = xfer->len;
93 hw->bpw = xfer->bits_per_word; 71 hw->bpw = xfer->bits_per_word;
@@ -176,13 +154,11 @@ static int spi_clps711x_probe(struct platform_device *pdev)
176 } 154 }
177 } 155 }
178 156
179 hw->spi_clk = devm_clk_get(&pdev->dev, "spi"); 157 hw->spi_clk = devm_clk_get(&pdev->dev, NULL);
180 if (IS_ERR(hw->spi_clk)) { 158 if (IS_ERR(hw->spi_clk)) {
181 dev_err(&pdev->dev, "Can't get clocks\n");
182 ret = PTR_ERR(hw->spi_clk); 159 ret = PTR_ERR(hw->spi_clk);
183 goto err_out; 160 goto err_out;
184 } 161 }
185 master->max_speed_hz = clk_get_rate(hw->spi_clk);
186 162
187 hw->syscon = syscon_regmap_lookup_by_pdevname("syscon.3"); 163 hw->syscon = syscon_regmap_lookup_by_pdevname("syscon.3");
188 if (IS_ERR(hw->syscon)) { 164 if (IS_ERR(hw->syscon)) {
@@ -190,12 +166,6 @@ static int spi_clps711x_probe(struct platform_device *pdev)
190 goto err_out; 166 goto err_out;
191 } 167 }
192 168
193 hw->syscon1 = syscon_regmap_lookup_by_pdevname("syscon.1");
194 if (IS_ERR(hw->syscon1)) {
195 ret = PTR_ERR(hw->syscon1);
196 goto err_out;
197 }
198
199 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 169 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
200 hw->syncio = devm_ioremap_resource(&pdev->dev, res); 170 hw->syncio = devm_ioremap_resource(&pdev->dev, res);
201 if (IS_ERR(hw->syncio)) { 171 if (IS_ERR(hw->syncio)) {
diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c
index 134fb6eb7b19..63c82a61c975 100644
--- a/drivers/spi/spi-davinci.c
+++ b/drivers/spi/spi-davinci.c
@@ -167,8 +167,10 @@ static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
167static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) 167static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
168{ 168{
169 u32 data = 0; 169 u32 data = 0;
170
170 if (dspi->tx) { 171 if (dspi->tx) {
171 const u8 *tx = dspi->tx; 172 const u8 *tx = dspi->tx;
173
172 data = *tx++; 174 data = *tx++;
173 dspi->tx = tx; 175 dspi->tx = tx;
174 } 176 }
@@ -178,8 +180,10 @@ static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
178static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) 180static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
179{ 181{
180 u32 data = 0; 182 u32 data = 0;
183
181 if (dspi->tx) { 184 if (dspi->tx) {
182 const u16 *tx = dspi->tx; 185 const u16 *tx = dspi->tx;
186
183 data = *tx++; 187 data = *tx++;
184 dspi->tx = tx; 188 dspi->tx = tx;
185 } 189 }
@@ -996,8 +1000,8 @@ static int davinci_spi_probe(struct platform_device *pdev)
996 goto free_clk; 1000 goto free_clk;
997 1001
998 dev_info(&pdev->dev, "DMA: supported\n"); 1002 dev_info(&pdev->dev, "DMA: supported\n");
999 dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, " 1003 dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, event queue: %d\n",
1000 "event queue: %d\n", &dma_rx_chan, &dma_tx_chan, 1004 &dma_rx_chan, &dma_tx_chan,
1001 pdata->dma_event_q); 1005 pdata->dma_event_q);
1002 } 1006 }
1003 1007
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index 0dd0623319b0..33117fbbf689 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -135,8 +135,7 @@ static int mrst_spi_debugfs_init(struct dw_spi *dws)
135 135
136static void mrst_spi_debugfs_remove(struct dw_spi *dws) 136static void mrst_spi_debugfs_remove(struct dw_spi *dws)
137{ 137{
138 if (dws->debugfs) 138 debugfs_remove_recursive(dws->debugfs);
139 debugfs_remove_recursive(dws->debugfs);
140} 139}
141 140
142#else 141#else
@@ -177,7 +176,7 @@ static inline u32 rx_max(struct dw_spi *dws)
177{ 176{
178 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes; 177 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
179 178
180 return min(rx_left, (u32)dw_readw(dws, DW_SPI_RXFLR)); 179 return min_t(u32, rx_left, dw_readw(dws, DW_SPI_RXFLR));
181} 180}
182 181
183static void dw_writer(struct dw_spi *dws) 182static void dw_writer(struct dw_spi *dws)
@@ -228,8 +227,9 @@ static void *next_transfer(struct dw_spi *dws)
228 struct spi_transfer, 227 struct spi_transfer,
229 transfer_list); 228 transfer_list);
230 return RUNNING_STATE; 229 return RUNNING_STATE;
231 } else 230 }
232 return DONE_STATE; 231
232 return DONE_STATE;
233} 233}
234 234
235/* 235/*
@@ -471,10 +471,12 @@ static void pump_transfers(unsigned long data)
471 */ 471 */
472 if (!dws->dma_mapped && !chip->poll_mode) { 472 if (!dws->dma_mapped && !chip->poll_mode) {
473 int templen = dws->len / dws->n_bytes; 473 int templen = dws->len / dws->n_bytes;
474
474 txint_level = dws->fifo_len / 2; 475 txint_level = dws->fifo_len / 2;
475 txint_level = (templen > txint_level) ? txint_level : templen; 476 txint_level = (templen > txint_level) ? txint_level : templen;
476 477
477 imask |= SPI_INT_TXEI | SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI; 478 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
479 SPI_INT_RXUI | SPI_INT_RXOI;
478 dws->transfer_handler = interrupt_transfer; 480 dws->transfer_handler = interrupt_transfer;
479 } 481 }
480 482
@@ -515,7 +517,6 @@ static void pump_transfers(unsigned long data)
515 517
516early_exit: 518early_exit:
517 giveback(dws); 519 giveback(dws);
518 return;
519} 520}
520 521
521static int dw_spi_transfer_one_message(struct spi_master *master, 522static int dw_spi_transfer_one_message(struct spi_master *master,
@@ -626,6 +627,7 @@ static void spi_hw_init(struct dw_spi *dws)
626 */ 627 */
627 if (!dws->fifo_len) { 628 if (!dws->fifo_len) {
628 u32 fifo; 629 u32 fifo;
630
629 for (fifo = 2; fifo <= 257; fifo++) { 631 for (fifo = 2; fifo <= 257; fifo++) {
630 dw_writew(dws, DW_SPI_TXFLTR, fifo); 632 dw_writew(dws, DW_SPI_TXFLTR, fifo);
631 if (fifo != dw_readw(dws, DW_SPI_TXFLTR)) 633 if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c
index 2f675d32df0e..bf9728773247 100644
--- a/drivers/spi/spi-ep93xx.c
+++ b/drivers/spi/spi-ep93xx.c
@@ -266,6 +266,7 @@ static int ep93xx_spi_setup(struct spi_device *spi)
266 266
267 if (chip->ops && chip->ops->setup) { 267 if (chip->ops && chip->ops->setup) {
268 int ret = chip->ops->setup(spi); 268 int ret = chip->ops->setup(spi);
269
269 if (ret) { 270 if (ret) {
270 kfree(chip); 271 kfree(chip);
271 return ret; 272 return ret;
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 2884f0c2f5f0..c3f8d3a22472 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -154,12 +154,14 @@ static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
154static void mxs_ssp_dma_irq_callback(void *param) 154static void mxs_ssp_dma_irq_callback(void *param)
155{ 155{
156 struct mxs_spi *spi = param; 156 struct mxs_spi *spi = param;
157
157 complete(&spi->c); 158 complete(&spi->c);
158} 159}
159 160
160static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id) 161static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
161{ 162{
162 struct mxs_ssp *ssp = dev_id; 163 struct mxs_ssp *ssp = dev_id;
164
163 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n", 165 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
164 __func__, __LINE__, 166 __func__, __LINE__,
165 readl(ssp->base + HW_SSP_CTRL1(ssp)), 167 readl(ssp->base + HW_SSP_CTRL1(ssp)),
@@ -189,7 +191,7 @@ static int mxs_spi_txrx_dma(struct mxs_spi *spi,
189 if (!len) 191 if (!len)
190 return -EINVAL; 192 return -EINVAL;
191 193
192 dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL); 194 dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
193 if (!dma_xfer) 195 if (!dma_xfer)
194 return -ENOMEM; 196 return -ENOMEM;
195 197
diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index c4675fa8b645..345e7d61c399 100644
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -179,8 +179,8 @@ static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
179 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) { 179 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
180 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG))) 180 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
181 return 1; 181 return 1;
182 else 182
183 udelay(1); 183 udelay(1);
184 } 184 }
185 185
186 return -1; 186 return -1;
@@ -360,6 +360,7 @@ static int orion_spi_probe(struct platform_device *pdev)
360 master->bus_num = pdev->id; 360 master->bus_num = pdev->id;
361 if (pdev->dev.of_node) { 361 if (pdev->dev.of_node) {
362 u32 cell_index; 362 u32 cell_index;
363
363 if (!of_property_read_u32(pdev->dev.of_node, "cell-index", 364 if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
364 &cell_index)) 365 &cell_index))
365 master->bus_num = cell_index; 366 master->bus_num = cell_index;
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index e4a85ada861d..795bcbc0131b 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -302,6 +302,7 @@ static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
302 max_n_32bit = DIV_ROUND_UP(nbytes, 4); 302 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
303 for (count = 0; count < max_n_32bit; count++) { 303 for (count = 0; count < max_n_32bit; count++) {
304 u32 x = 0; 304 u32 x = 0;
305
305 for (i = 0; (i < 4) && nbytes; i++, nbytes--) 306 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
306 x |= (u32)(*tx_buf++) << (i * 8); 307 x |= (u32)(*tx_buf++) << (i * 8);
307 tegra_spi_writel(tspi, x, SPI_TX_FIFO); 308 tegra_spi_writel(tspi, x, SPI_TX_FIFO);
@@ -312,6 +313,7 @@ static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
312 nbytes = written_words * tspi->bytes_per_word; 313 nbytes = written_words * tspi->bytes_per_word;
313 for (count = 0; count < max_n_32bit; count++) { 314 for (count = 0; count < max_n_32bit; count++) {
314 u32 x = 0; 315 u32 x = 0;
316
315 for (i = 0; nbytes && (i < tspi->bytes_per_word); 317 for (i = 0; nbytes && (i < tspi->bytes_per_word);
316 i++, nbytes--) 318 i++, nbytes--)
317 x |= (u32)(*tx_buf++) << (i * 8); 319 x |= (u32)(*tx_buf++) << (i * 8);
@@ -338,6 +340,7 @@ static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
338 len = tspi->curr_dma_words * tspi->bytes_per_word; 340 len = tspi->curr_dma_words * tspi->bytes_per_word;
339 for (count = 0; count < rx_full_count; count++) { 341 for (count = 0; count < rx_full_count; count++) {
340 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO); 342 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
343
341 for (i = 0; len && (i < 4); i++, len--) 344 for (i = 0; len && (i < 4); i++, len--)
342 *rx_buf++ = (x >> i*8) & 0xFF; 345 *rx_buf++ = (x >> i*8) & 0xFF;
343 } 346 }
@@ -345,8 +348,10 @@ static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
345 read_words += tspi->curr_dma_words; 348 read_words += tspi->curr_dma_words;
346 } else { 349 } else {
347 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; 350 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
351
348 for (count = 0; count < rx_full_count; count++) { 352 for (count = 0; count < rx_full_count; count++) {
349 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask; 353 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
354
350 for (i = 0; (i < tspi->bytes_per_word); i++) 355 for (i = 0; (i < tspi->bytes_per_word); i++)
351 *rx_buf++ = (x >> (i*8)) & 0xFF; 356 *rx_buf++ = (x >> (i*8)) & 0xFF;
352 } 357 }
@@ -365,6 +370,7 @@ static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
365 370
366 if (tspi->is_packed) { 371 if (tspi->is_packed) {
367 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; 372 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
373
368 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); 374 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
369 } else { 375 } else {
370 unsigned int i; 376 unsigned int i;
@@ -374,6 +380,7 @@ static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
374 380
375 for (count = 0; count < tspi->curr_dma_words; count++) { 381 for (count = 0; count < tspi->curr_dma_words; count++) {
376 u32 x = 0; 382 u32 x = 0;
383
377 for (i = 0; consume && (i < tspi->bytes_per_word); 384 for (i = 0; consume && (i < tspi->bytes_per_word);
378 i++, consume--) 385 i++, consume--)
379 x |= (u32)(*tx_buf++) << (i * 8); 386 x |= (u32)(*tx_buf++) << (i * 8);
@@ -396,6 +403,7 @@ static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
396 403
397 if (tspi->is_packed) { 404 if (tspi->is_packed) {
398 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; 405 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
406
399 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); 407 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
400 } else { 408 } else {
401 unsigned int i; 409 unsigned int i;
@@ -405,6 +413,7 @@ static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
405 413
406 for (count = 0; count < tspi->curr_dma_words; count++) { 414 for (count = 0; count < tspi->curr_dma_words; count++) {
407 u32 x = tspi->rx_dma_buf[count] & rx_mask; 415 u32 x = tspi->rx_dma_buf[count] & rx_mask;
416
408 for (i = 0; (i < tspi->bytes_per_word); i++) 417 for (i = 0; (i < tspi->bytes_per_word); i++)
409 *rx_buf++ = (x >> (i*8)) & 0xFF; 418 *rx_buf++ = (x >> (i*8)) & 0xFF;
410 } 419 }
diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c
index 3548ce25c08f..cd66fe7b78a9 100644
--- a/drivers/spi/spi-tegra20-sflash.c
+++ b/drivers/spi/spi-tegra20-sflash.c
@@ -99,7 +99,7 @@
99#define SPI_TX_TRIG_MASK (0x3 << 16) 99#define SPI_TX_TRIG_MASK (0x3 << 16)
100#define SPI_TX_TRIG_1W (0x0 << 16) 100#define SPI_TX_TRIG_1W (0x0 << 16)
101#define SPI_TX_TRIG_4W (0x1 << 16) 101#define SPI_TX_TRIG_4W (0x1 << 16)
102#define SPI_DMA_BLK_COUNT(count) (((count) - 1) & 0xFFFF); 102#define SPI_DMA_BLK_COUNT(count) (((count) - 1) & 0xFFFF)
103 103
104#define SPI_TX_FIFO 0x10 104#define SPI_TX_FIFO 0x10
105#define SPI_RX_FIFO 0x20 105#define SPI_RX_FIFO 0x20
@@ -221,6 +221,7 @@ static int tegra_sflash_read_rx_fifo_to_client_rxbuf(
221 while (!(status & SPI_RXF_EMPTY)) { 221 while (!(status & SPI_RXF_EMPTY)) {
222 int i; 222 int i;
223 u32 x = tegra_sflash_readl(tsd, SPI_RX_FIFO); 223 u32 x = tegra_sflash_readl(tsd, SPI_RX_FIFO);
224
224 for (i = 0; (i < tsd->bytes_per_word); i++) 225 for (i = 0; (i < tsd->bytes_per_word); i++)
225 *rx_buf++ = (x >> (i*8)) & 0xFF; 226 *rx_buf++ = (x >> (i*8)) & 0xFF;
226 read_words++; 227 read_words++;
diff --git a/drivers/spi/spi-txx9.c b/drivers/spi/spi-txx9.c
index 5f183baa91a9..2501a8373e89 100644
--- a/drivers/spi/spi-txx9.c
+++ b/drivers/spi/spi-txx9.c
@@ -97,6 +97,7 @@ static void txx9spi_cs_func(struct spi_device *spi, struct txx9spi *c,
97 int on, unsigned int cs_delay) 97 int on, unsigned int cs_delay)
98{ 98{
99 int val = (spi->mode & SPI_CS_HIGH) ? on : !on; 99 int val = (spi->mode & SPI_CS_HIGH) ? on : !on;
100
100 if (on) { 101 if (on) {
101 /* deselect the chip with cs_change hint in last transfer */ 102 /* deselect the chip with cs_change hint in last transfer */
102 if (c->last_chipselect >= 0) 103 if (c->last_chipselect >= 0)
@@ -188,6 +189,7 @@ static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m)
188 if (prev_speed_hz != speed_hz 189 if (prev_speed_hz != speed_hz
189 || prev_bits_per_word != bits_per_word) { 190 || prev_bits_per_word != bits_per_word) {
190 int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1; 191 int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1;
192
191 n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER); 193 n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER);
192 /* enter config mode */ 194 /* enter config mode */
193 txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, 195 txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR,
diff --git a/drivers/spi/spi-xtensa-xtfpga.c b/drivers/spi/spi-xtensa-xtfpga.c
index 41e158187f9d..0dc5df5233a9 100644
--- a/drivers/spi/spi-xtensa-xtfpga.c
+++ b/drivers/spi/spi-xtensa-xtfpga.c
@@ -46,6 +46,7 @@ static inline unsigned int xtfpga_spi_read32(const struct xtfpga_spi *spi,
46static inline void xtfpga_spi_wait_busy(struct xtfpga_spi *xspi) 46static inline void xtfpga_spi_wait_busy(struct xtfpga_spi *xspi)
47{ 47{
48 unsigned i; 48 unsigned i;
49
49 for (i = 0; xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY) && 50 for (i = 0; xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY) &&
50 i < BUSY_WAIT_US; ++i) 51 i < BUSY_WAIT_US; ++i)
51 udelay(1); 52 udelay(1);
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-11 06:03:16 -0400