diff options
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_display.c | 14 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_dma.h | 7 |
4 files changed, 9 insertions, 26 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c index e21453a94971..9ac94d4e5646 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c | |||
| @@ -494,13 +494,6 @@ nvc0_fifo_isr_subfifo_intr(struct nvc0_fifo_priv *priv, int unit) | |||
| 494 | u32 mthd = (addr & 0x00003ffc); | 494 | u32 mthd = (addr & 0x00003ffc); |
| 495 | u32 show = stat; | 495 | u32 show = stat; |
| 496 | 496 | ||
| 497 | if (stat & 0x00200000) { | ||
| 498 | if (mthd == 0x0054) { | ||
| 499 | if (!nvc0_fifo_swmthd(priv, chid, 0x0500, 0x00000000)) | ||
| 500 | show &= ~0x00200000; | ||
| 501 | } | ||
| 502 | } | ||
| 503 | |||
| 504 | if (stat & 0x00800000) { | 497 | if (stat & 0x00800000) { |
| 505 | if (!nvc0_fifo_swmthd(priv, chid, mthd, data)) | 498 | if (!nvc0_fifo_swmthd(priv, chid, mthd, data)) |
| 506 | show &= ~0x00800000; | 499 | show &= ~0x00800000; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c index fcd449e5aba7..04f412922d2d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | |||
| @@ -481,13 +481,6 @@ nve0_fifo_isr_subfifo_intr(struct nve0_fifo_priv *priv, int unit) | |||
| 481 | u32 mthd = (addr & 0x00003ffc); | 481 | u32 mthd = (addr & 0x00003ffc); |
| 482 | u32 show = stat; | 482 | u32 show = stat; |
| 483 | 483 | ||
| 484 | if (stat & 0x00200000) { | ||
| 485 | if (mthd == 0x0054) { | ||
| 486 | if (!nve0_fifo_swmthd(priv, chid, 0x0500, 0x00000000)) | ||
| 487 | show &= ~0x00200000; | ||
| 488 | } | ||
| 489 | } | ||
| 490 | |||
| 491 | if (stat & 0x00800000) { | 484 | if (stat & 0x00800000) { |
| 492 | if (!nve0_fifo_swmthd(priv, chid, mthd, data)) | 485 | if (!nve0_fifo_swmthd(priv, chid, mthd, data)) |
| 493 | show &= ~0x00800000; | 486 | show &= ~0x00800000; |
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 4b124a67fc04..17422bc19529 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c | |||
| @@ -554,19 +554,15 @@ nouveau_page_flip_emit(struct nouveau_channel *chan, | |||
| 554 | goto fail; | 554 | goto fail; |
| 555 | 555 | ||
| 556 | /* Emit the pageflip */ | 556 | /* Emit the pageflip */ |
| 557 | ret = RING_SPACE(chan, 3); | 557 | ret = RING_SPACE(chan, 2); |
| 558 | if (ret) | 558 | if (ret) |
| 559 | goto fail; | 559 | goto fail; |
| 560 | 560 | ||
| 561 | if (nv_device(drm->device)->card_type < NV_C0) { | 561 | if (nv_device(drm->device)->card_type < NV_C0) |
| 562 | BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1); | 562 | BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1); |
| 563 | OUT_RING (chan, 0x00000000); | 563 | else |
| 564 | OUT_RING (chan, 0x00000000); | 564 | BEGIN_NVC0(chan, FermiSw, NV_SW_PAGE_FLIP, 1); |
| 565 | } else { | 565 | OUT_RING (chan, 0x00000000); |
| 566 | BEGIN_NVC0(chan, 0, NV10_SUBCHAN_REF_CNT, 1); | ||
| 567 | OUT_RING (chan, 0); | ||
| 568 | BEGIN_IMC0(chan, 0, NVSW_SUBCHAN_PAGE_FLIP, 0x0000); | ||
| 569 | } | ||
| 570 | FIRE_RING (chan); | 566 | FIRE_RING (chan); |
| 571 | 567 | ||
| 572 | ret = nouveau_fence_new(chan, false, pfence); | 568 | ret = nouveau_fence_new(chan, false, pfence); |
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index 690d5930ce32..984004d66a6d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h | |||
| @@ -51,9 +51,11 @@ enum { | |||
| 51 | NvSubCtxSurf2D = 0, | 51 | NvSubCtxSurf2D = 0, |
| 52 | NvSubSw = 1, | 52 | NvSubSw = 1, |
| 53 | NvSubImageBlit = 2, | 53 | NvSubImageBlit = 2, |
| 54 | NvSub2D = 3, | ||
| 55 | NvSubGdiRect = 3, | 54 | NvSubGdiRect = 3, |
| 56 | NvSubCopy = 4, | 55 | |
| 56 | NvSub2D = 3, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ | ||
| 57 | NvSubCopy = 4, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ | ||
| 58 | FermiSw = 5, /* DO NOT CHANGE (well.. 6/7 will work...) */ | ||
| 57 | }; | 59 | }; |
| 58 | 60 | ||
| 59 | /* Object handles. */ | 61 | /* Object handles. */ |
| @@ -194,7 +196,6 @@ WIND_RING(struct nouveau_channel *chan) | |||
| 194 | #define NV84_SUBCHAN_UEVENT 0x00000020 | 196 | #define NV84_SUBCHAN_UEVENT 0x00000020 |
| 195 | #define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024 | 197 | #define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024 |
| 196 | #define NV10_SUBCHAN_REF_CNT 0x00000050 | 198 | #define NV10_SUBCHAN_REF_CNT 0x00000050 |
| 197 | #define NVSW_SUBCHAN_PAGE_FLIP 0x00000054 | ||
| 198 | #define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060 | 199 | #define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060 |
| 199 | #define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064 | 200 | #define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064 |
| 200 | #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068 | 201 | #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068 |
