3 files changed, 698 insertions, 158 deletions

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 24e8597b2c3e..67ab15aa98c3 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -62,8 +62,10 @@ config AMBA_PL08X
         select DMA_ENGINE
         select DMA_VIRTUAL_CHANNELS
         help
-          Platform has a PL08x DMAC device
-          which can provide DMA engine support
+          Say yes if your platform has a PL08x DMAC device which can
+          provide DMA engine support. This includes the original ARM
+          PL080 and PL081, Samsungs PL080 derivative and Faraday
+          Technology's FTDMAC020 PL080 derivative.
 
 config AMCC_PPC440SPE_ADMA
         tristate "AMCC PPC440SPe ADMA support"
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 6ddb029dac50..13cc95c0474c 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -1,9 +1,10 @@
 /*
  * Copyright (c) 2006 ARM Ltd.
  * Copyright (c) 2010 ST-Ericsson SA
+ * Copyirght (c) 2017 Linaro Ltd.
  *
  * Author: Peter Pearse <peter.pearse@arm.com>
- * Author: Linus Walleij <linus.walleij@stericsson.com>
+ * Author: Linus Walleij <linus.walleij@linaro.org>
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the Free
@@ -110,11 +111,12 @@ struct pl08x_driver_data;
  * @channels: the number of channels available in this variant
  * @signals: the number of request signals available from the hardware
  * @dualmaster: whether this version supports dual AHB masters or not.
- * @nomadik: whether the channels have Nomadik security extension bits
- *      that need to be checked for permission before use and some registers are
- *      missing
- * @pl080s: whether this version is a PL080S, which has separate register and
- *      LLI word for transfer size.
+ * @nomadik: whether this variant is a ST Microelectronics Nomadik, where the
+ *      channels have Nomadik security extension bits that need to be checked
+ *      for permission before use and some registers are missing
+ * @pl080s: whether this variant is a Samsung PL080S, which has separate
+ *      register and LLI word for transfer size.
+ * @ftdmac020: whether this variant is a Faraday Technology FTDMAC020
  * @max_transfer_size: the maximum single element transfer size for this
  *      PL08x variant.
  */
@@ -125,6 +127,7 @@ struct vendor_data {
         bool dualmaster;
         bool nomadik;
         bool pl080s;
+        bool ftdmac020;
         u32 max_transfer_size;
 };
 
@@ -148,19 +151,34 @@ struct pl08x_bus_data {
  * @id: physical index to this channel
  * @base: memory base address for this physical channel
  * @reg_config: configuration address for this physical channel
+ * @reg_control: control address for this physical channel
+ * @reg_src: transfer source address register
+ * @reg_dst: transfer destination address register
+ * @reg_lli: transfer LLI address register
+ * @reg_busy: if the variant has a special per-channel busy register,
+ * this contains a pointer to it
  * @lock: a lock to use when altering an instance of this struct
  * @serving: the virtual channel currently being served by this physical
  * channel
  * @locked: channel unavailable for the system, e.g. dedicated to secure
  * world
+ * @ftdmac020: channel is on a FTDMAC020
+ * @pl080s: channel is on a PL08s
  */
 struct pl08x_phy_chan {
         unsigned int id;
         void __iomem *base;
         void __iomem *reg_config;
+        void __iomem *reg_control;
+        void __iomem *reg_src;
+        void __iomem *reg_dst;
+        void __iomem *reg_lli;
+        void __iomem *reg_busy;
         spinlock_t lock;
         struct pl08x_dma_chan *serving;
         bool locked;
+        bool ftdmac020;
+        bool pl080s;
 };
 
 /**
@@ -362,10 +380,24 @@ static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
 {
         unsigned int val;
 
+        /* If we have a special busy register, take a shortcut */
+        if (ch->reg_busy) {
+                val = readl(ch->reg_busy);
+                return !!(val & BIT(ch->id));
+        }
         val = readl(ch->reg_config);
         return val & PL080_CONFIG_ACTIVE;
 }
 
+/*
+ * pl08x_write_lli() - Write an LLI into the DMA controller.
+ *
+ * The PL08x derivatives support linked lists, but the first item of the
+ * list containing the source, destination, control word and next LLI is
+ * ignored. Instead the driver has to write those values directly into the
+ * SRC, DST, LLI and control registers. On FTDMAC020 also the SIZE
+ * register need to be set up for the first transfer.
+ */
 static void pl08x_write_lli(struct pl08x_driver_data *pl08x,
                 struct pl08x_phy_chan *phychan, const u32 *lli, u32 ccfg)
 {
@@ -383,11 +415,112 @@ static void pl08x_write_lli(struct pl08x_driver_data *pl08x,
                         phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST],
                         lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], ccfg);
 
-        writel_relaxed(lli[PL080_LLI_SRC], phychan->base + PL080_CH_SRC_ADDR);
-        writel_relaxed(lli[PL080_LLI_DST], phychan->base + PL080_CH_DST_ADDR);
-        writel_relaxed(lli[PL080_LLI_LLI], phychan->base + PL080_CH_LLI);
-        writel_relaxed(lli[PL080_LLI_CCTL], phychan->base + PL080_CH_CONTROL);
+        writel_relaxed(lli[PL080_LLI_SRC], phychan->reg_src);
+        writel_relaxed(lli[PL080_LLI_DST], phychan->reg_dst);
+        writel_relaxed(lli[PL080_LLI_LLI], phychan->reg_lli);
 
+        /*
+         * The FTMAC020 has a different layout in the CCTL word of the LLI
+         * and the CCTL register which is split in CSR and SIZE registers.
+         * Convert the LLI item CCTL into the proper values to write into
+         * the CSR and SIZE registers.
+         */
+        if (phychan->ftdmac020) {
+                u32 llictl = lli[PL080_LLI_CCTL];
+                u32 val = 0;
+
+                /* Write the transfer size (12 bits) to the size register */
+                writel_relaxed(llictl & FTDMAC020_LLI_TRANSFER_SIZE_MASK,
+                               phychan->base + FTDMAC020_CH_SIZE);
+                /*
+                 * Then write the control bits 28..16 to the control register
+                 * by shuffleing the bits around to where they are in the
+                 * main register. The mapping is as follows:
+                 * Bit 28: TC_MSK - mask on all except last LLI
+                 * Bit 27..25: SRC_WIDTH
+                 * Bit 24..22: DST_WIDTH
+                 * Bit 21..20: SRCAD_CTRL
+                 * Bit 19..17: DSTAD_CTRL
+                 * Bit 17: SRC_SEL
+                 * Bit 16: DST_SEL
+                 */
+                if (llictl & FTDMAC020_LLI_TC_MSK)
+                        val |= FTDMAC020_CH_CSR_TC_MSK;
+                val |= ((llictl  & FTDMAC020_LLI_SRC_WIDTH_MSK) >>
+                        (FTDMAC020_LLI_SRC_WIDTH_SHIFT -
+                         FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT));
+                val |= ((llictl  & FTDMAC020_LLI_DST_WIDTH_MSK) >>
+                        (FTDMAC020_LLI_DST_WIDTH_SHIFT -
+                         FTDMAC020_CH_CSR_DST_WIDTH_SHIFT));
+                val |= ((llictl  & FTDMAC020_LLI_SRCAD_CTL_MSK) >>
+                        (FTDMAC020_LLI_SRCAD_CTL_SHIFT -
+                         FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT));
+                val |= ((llictl  & FTDMAC020_LLI_DSTAD_CTL_MSK) >>
+                        (FTDMAC020_LLI_DSTAD_CTL_SHIFT -
+                         FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT));
+                if (llictl & FTDMAC020_LLI_SRC_SEL)
+                        val |= FTDMAC020_CH_CSR_SRC_SEL;
+                if (llictl & FTDMAC020_LLI_DST_SEL)
+                        val |= FTDMAC020_CH_CSR_DST_SEL;
+
+                /*
+                 * Set up the bits that exist in the CSR but are not
+                 * part the LLI, i.e. only gets written to the control
+                 * register right here.
+                 *
+                 * FIXME: do not just handle memcpy, also handle slave DMA.
+                 */
+                switch (pl08x->pd->memcpy_burst_size) {
+                default:
+                case PL08X_BURST_SZ_1:
+                        val |= PL080_BSIZE_1 <<
+                                FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
+                        break;
+                case PL08X_BURST_SZ_4: