4 files changed, 38 insertions, 19 deletions

diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
index b690e65d55fe..79ce2eea44db 100644
--- a/drivers/fpga/fpga-mgr.c
+++ b/drivers/fpga/fpga-mgr.c
@@ -32,7 +32,7 @@ static struct class *fpga_mgr_class;
 /**
  * fpga_mgr_buf_load - load fpga from image in buffer
  * @mgr:        fpga manager
- * @flags:      flags setting fpga confuration modes
+ * @info:       fpga image specific information
  * @buf:        buffer contain fpga image
  * @count:      byte count of buf
  *
@@ -44,8 +44,8 @@ static struct class *fpga_mgr_class;
  *
  * Return: 0 on success, negative error code otherwise.
  */
-int fpga_mgr_buf_load(struct fpga_manager *mgr, u32 flags, const char *buf,
-                      size_t count)
+int fpga_mgr_buf_load(struct fpga_manager *mgr, struct fpga_image_info *info,
+                      const char *buf, size_t count)
 {
         struct device *dev = &mgr->dev;
         int ret;
@@ -56,7 +56,7 @@ int fpga_mgr_buf_load(struct fpga_manager *mgr, u32 flags, const char *buf,
          * ready to receive an FPGA image.
          */
         mgr->state = FPGA_MGR_STATE_WRITE_INIT;
-        ret = mgr->mops->write_init(mgr, flags, buf, count);
+        ret = mgr->mops->write_init(mgr, info, buf, count);
         if (ret) {
                 dev_err(dev, "Error preparing FPGA for writing\n");
                 mgr->state = FPGA_MGR_STATE_WRITE_INIT_ERR;
@@ -79,7 +79,7 @@ int fpga_mgr_buf_load(struct fpga_manager *mgr, u32 flags, const char *buf,
          * steps to finish and set the FPGA into operating mode.
          */
         mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE;
-        ret = mgr->mops->write_complete(mgr, flags);
+        ret = mgr->mops->write_complete(mgr, info);
         if (ret) {
                 dev_err(dev, "Error after writing image data to FPGA\n");
                 mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE_ERR;
@@ -94,7 +94,7 @@ EXPORT_SYMBOL_GPL(fpga_mgr_buf_load);
 /**
  * fpga_mgr_firmware_load - request firmware and load to fpga
  * @mgr:        fpga manager
- * @flags:      flags setting fpga confuration modes
+ * @info:       fpga image specific information
  * @image_name: name of image file on the firmware search path
  *
  * Request an FPGA image using the firmware class, then write out to the FPGA.
@@ -105,7 +105,8 @@ EXPORT_SYMBOL_GPL(fpga_mgr_buf_load);
  *
  * Return: 0 on success, negative error code otherwise.
  */
-int fpga_mgr_firmware_load(struct fpga_manager *mgr, u32 flags,
+int fpga_mgr_firmware_load(struct fpga_manager *mgr,
+                           struct fpga_image_info *info,
                            const char *image_name)
 {
         struct device *dev = &mgr->dev;
@@ -123,7 +124,7 @@ int fpga_mgr_firmware_load(struct fpga_manager *mgr, u32 flags,
                 return ret;
         }
 
-        ret = fpga_mgr_buf_load(mgr, flags, fw->data, fw->size);
+        ret = fpga_mgr_buf_load(mgr, info, fw->data, fw->size);
 
         release_firmware(fw);
 
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index 27d2ff28132c..b6672e66cda6 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -407,13 +407,14 @@ static int socfpga_fpga_reset(struct fpga_manager *mgr)
 /*
  * Prepare the FPGA to receive the configuration data.
  */
-static int socfpga_fpga_ops_configure_init(struct fpga_manager *mgr, u32 flags,
+static int socfpga_fpga_ops_configure_init(struct fpga_manager *mgr,
+                                           struct fpga_image_info *info,
                                            const char *buf, size_t count)
 {
         struct socfpga_fpga_priv *priv = mgr->priv;
         int ret;
 
-        if (flags & FPGA_MGR_PARTIAL_RECONFIG) {
+        if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
                 dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
                 return -EINVAL;
         }
@@ -478,7 +479,7 @@ static int socfpga_fpga_ops_configure_write(struct fpga_manager *mgr,
 }
 
 static int socfpga_fpga_ops_configure_complete(struct fpga_manager *mgr,
-                                               u32 flags)
+                                               struct fpga_image_info *info)
 {
         struct socfpga_fpga_priv *priv = mgr->priv;
         u32 status;
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
index c2fb4120bd62..249682e92502 100644
--- a/drivers/fpga/zynq-fpga.c
+++ b/drivers/fpga/zynq-fpga.c
@@ -175,7 +175,8 @@ static irqreturn_t zynq_fpga_isr(int irq, void *data)
         return IRQ_HANDLED;
 }
 
-static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
+static int zynq_fpga_ops_write_init(struct fpga_manager *mgr,
+                                    struct fpga_image_info *info,
                                     const char *buf, size_t count)
 {
         struct zynq_fpga_priv *priv;
@@ -189,7 +190,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags,
                 return err;
 
         /* don't globally reset PL if we're doing partial reconfig */
-        if (!(flags & FPGA_MGR_PARTIAL_RECONFIG)) {
+        if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
                 /* assert AXI interface resets */
                 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
                              FPGA_RST_ALL_MASK);
@@ -343,7 +344,8 @@ out_free:
         return err;
 }
 
-static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, u32 flags)
+static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
+                                        struct fpga_image_info *info)
 {
         struct zynq_fpga_priv *priv = mgr->priv;
         int err;
@@ -364,7 +366,7 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, u32 flags)
                 return err;
 
         /* for the partial reconfig case we didn't touch the level shifters */
-        if (!(flags & FPGA_MGR_PARTIAL_RECONFIG)) {
+        if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
                 /* enable level shifters from PL to PS */
                 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
                              LVL_SHFTR_ENABLE_PL_TO_PS);
diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
index 957b5ac9428a..55803186e0ea 100644
--- a/include/linux/fpga/fpga-mgr.h
+++ b/include/linux/fpga/fpga-mgr.h
@@ -69,6 +69,18 @@ enum fpga_mgr_states {
 #define FPGA_MGR_PARTIAL_RECONFIG       BIT(0)
 
 /**
+ * struct fpga_image_info - information specific to a FPGA image
+ * @flags: boolean flags as defined above
+ * @enable_timeout_us: maximum time to enable traffic through bridge (uSec)
+ * @disable_timeout_us: maximum time to disable traffic through bridge (uSec)
+ */
+struct fpga_image_info {
+        u32 flags;
+        u32 enable_timeout_us;
+        u32 disable_timeout_us;
+};
+
+/**
  * struct fpga_manager_ops - ops for low level fpga manager drivers
  * @state: returns an enum value of the FPGA's state
  * @write_init: prepare the FPGA to receive confuration data
@@ -82,10 +94,12 @@ enum fpga_mgr_states {
  */
 struct fpga_manager_ops {
         enum fpga_mgr_states (*state)(struct fpga_manager *mgr);
-        int (*write_init)(struct fpga_manager *mgr, u32 flags,
+        int (*write_init)(struct fpga_manager *mgr,
+                          struct fpga_image_info *info,
                           const char *buf, size_t count);
         int (*write)(struct fpga_manager *mgr, const char *buf, size_t count);
-        int (*write_complete)(struct fpga_manager *mgr, u32 flags);
+        int (*write_complete)(struct fpga_manager *mgr,
+                              struct fpga_image_info *info);
         void (*fpga_remove)(struct fpga_manager *mgr);
 };
 
@@ -109,10 +123,11 @@ struct fpga_manager {
 
 #define to_fpga_manager(d) container_of(d, struct fpga_manager, dev)
 
-int fpga_mgr_buf_load(struct fpga_manager *mgr, u32 flags,
+int fpga_mgr_buf_load(struct fpga_manager *mgr, struct fpga_image_info *info,
                       const char *buf, size_t count);
 
-int fpga_mgr_firmware_load(struct fpga_manager *mgr, u32 flags,
+int fpga_mgr_firmware_load(struct fpga_manager *mgr,
+                           struct fpga_image_info *info,
                            const char *image_name);
 
 struct fpga_manager *of_fpga_mgr_get(struct device_node *node);