27 files changed, 146 insertions, 159 deletions

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index a07956a08936..97c59fd60702 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -117,7 +117,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
                 void (*f_vide)(void);
                 u64 d, d2;
 
-                printk(KERN_INFO "AMD K6 stepping B detected - ");
+                pr_info("AMD K6 stepping B detected - ");
 
                 /*
                  * It looks like AMD fixed the 2.6.2 bug and improved indirect
@@ -133,10 +133,9 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
                 d = d2-d;
 
                 if (d > 20*K6_BUG_LOOP)
-                        printk(KERN_CONT
-                                "system stability may be impaired when more than 32 MB are used.\n");
+                        pr_cont("system stability may be impaired when more than 32 MB are used.\n");
                 else
-                        printk(KERN_CONT "probably OK (after B9730xxxx).\n");
+                        pr_cont("probably OK (after B9730xxxx).\n");
         }
 
         /* K6 with old style WHCR */
@@ -154,7 +153,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
                         wbinvd();
                         wrmsr(MSR_K6_WHCR, l, h);
                         local_irq_restore(flags);
-                        printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
+                        pr_info("Enabling old style K6 write allocation for %d Mb\n",
                                 mbytes);
                 }
                 return;
@@ -175,7 +174,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
                         wbinvd();
                         wrmsr(MSR_K6_WHCR, l, h);
                         local_irq_restore(flags);
-                        printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
+                        pr_info("Enabling new style K6 write allocation for %d Mb\n",
                                 mbytes);
                 }
 
@@ -202,7 +201,7 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
          */
         if (c->x86_model >= 6 && c->x86_model <= 10) {
                 if (!cpu_has(c, X86_FEATURE_XMM)) {
-                        printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
+                        pr_info("Enabling disabled K7/SSE Support.\n");
                         msr_clear_bit(MSR_K7_HWCR, 15);
                         set_cpu_cap(c, X86_FEATURE_XMM);
                 }
@@ -216,9 +215,8 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
         if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
                 rdmsr(MSR_K7_CLK_CTL, l, h);
                 if ((l & 0xfff00000) != 0x20000000) {
-                        printk(KERN_INFO
-                            "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
-                                        l, ((l & 0x000fffff)|0x20000000));
+                        pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
+                                l, ((l & 0x000fffff)|0x20000000));
                         wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
                 }
         }
@@ -485,7 +483,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
                 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
                         unsigned long pfn = tseg >> PAGE_SHIFT;
 
-                        printk(KERN_DEBUG "tseg: %010llx\n", tseg);
+                        pr_debug("tseg: %010llx\n", tseg);
                         if (pfn_range_is_mapped(pfn, pfn + 1))
                                 set_memory_4k((unsigned long)__va(tseg), 1);
                 }
@@ -500,8 +498,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
 
                         rdmsrl(MSR_K7_HWCR, val);
                         if (!(val & BIT(24)))
-                                printk(KERN_WARNING FW_BUG "TSC doesn't count "
-                                        "with P0 frequency!\n");
+                                pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
                 }
         }
 
diff --git a/arch/x86/kernel/cpu/bugs_64.c b/arch/x86/kernel/cpu/bugs_64.c
index 04f0fe5af83e..a972ac4c7e7d 100644
--- a/arch/x86/kernel/cpu/bugs_64.c
+++ b/arch/x86/kernel/cpu/bugs_64.c
@@ -15,7 +15,7 @@ void __init check_bugs(void)
 {
         identify_boot_cpu();
 #if !defined(CONFIG_SMP)
-        printk(KERN_INFO "CPU: ");
+        pr_info("CPU: ");
         print_cpu_info(&boot_cpu_data);
 #endif
         alternative_instructions();
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index ae20be6e483c..ce197bb7c129 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -29,7 +29,7 @@ static void init_c3(struct cpuinfo_x86 *c)
                         rdmsr(MSR_VIA_FCR, lo, hi);
                         lo |= ACE_FCR;          /* enable ACE unit */
                         wrmsr(MSR_VIA_FCR, lo, hi);
-                        printk(KERN_INFO "CPU: Enabled ACE h/w crypto\n");
+                        pr_info("CPU: Enabled ACE h/w crypto\n");
                 }
 
                 /* enable RNG unit, if present and disabled */
@@ -37,7 +37,7 @@ static void init_c3(struct cpuinfo_x86 *c)
                         rdmsr(MSR_VIA_RNG, lo, hi);
                         lo |= RNG_ENABLE;       /* enable RNG unit */
                         wrmsr(MSR_VIA_RNG, lo, hi);
-                        printk(KERN_INFO "CPU: Enabled h/w RNG\n");
+                        pr_info("CPU: Enabled h/w RNG\n");
                 }
 
                 /* store Centaur Extended Feature Flags as
@@ -130,7 +130,7 @@ static void init_centaur(struct cpuinfo_x86 *c)
                         name = "C6";
                         fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
                         fcr_clr = DPDC;
-                        printk(KERN_NOTICE "Disabling bugged TSC.\n");
+                        pr_notice("Disabling bugged TSC.\n");
                         clear_cpu_cap(c, X86_FEATURE_TSC);
                         break;
                 case 8:
@@ -163,11 +163,11 @@ static void init_centaur(struct cpuinfo_x86 *c)
                 newlo = (lo|fcr_set) & (~fcr_clr);
 
                 if (newlo != lo) {
-                        printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n",
+                        pr_info("Centaur FCR was 0x%X now 0x%X\n",
                                 lo, newlo);
                         wrmsr(MSR_IDT_FCR1, newlo, hi);
                 } else {