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-rw-r--r--drivers/gpu/drm/bridge/dw-hdmi.c27
1 files changed, 5 insertions, 22 deletions
diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c
index 107fea49c4c6..b4fb0bd78910 100644
--- a/drivers/gpu/drm/bridge/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/dw-hdmi.c
@@ -930,31 +930,14 @@ static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
930 HDMI_PHY_CONF0_SELDIPIF_MASK); 930 HDMI_PHY_CONF0_SELDIPIF_MASK);
931} 931}
932 932
933static int hdmi_phy_configure(struct dw_hdmi *hdmi, 933static int hdmi_phy_configure(struct dw_hdmi *hdmi, int cscon)
934 unsigned char res, int cscon)
935{ 934{
936 unsigned res_idx;
937 u8 val, msec; 935 u8 val, msec;
938 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 936 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
939 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 937 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
940 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 938 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
941 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 939 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
942 940
943 switch (res) {
944 case 0: /* color resolution 0 is 8 bit colour depth */
945 case 8:
946 res_idx = DW_HDMI_RES_8;
947 break;
948 case 10:
949 res_idx = DW_HDMI_RES_10;
950 break;
951 case 12:
952 res_idx = DW_HDMI_RES_12;
953 break;
954 default:
955 return -EINVAL;
956 }
957
958 /* PLL/MPLL Cfg - always match on final entry */ 941 /* PLL/MPLL Cfg - always match on final entry */
959 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 942 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
960 if (hdmi->hdmi_data.video_mode.mpixelclock <= 943 if (hdmi->hdmi_data.video_mode.mpixelclock <=
@@ -1004,11 +987,11 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi,
1004 HDMI_PHY_I2CM_SLAVE_ADDR); 987 HDMI_PHY_I2CM_SLAVE_ADDR);
1005 hdmi_phy_test_clear(hdmi, 0); 988 hdmi_phy_test_clear(hdmi, 0);
1006 989
1007 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06); 990 hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 0x06);
1008 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15); 991 hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 0x15);
1009 992
1010 /* CURRCTRL */ 993 /* CURRCTRL */
1011 hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10); 994 hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 0x10);
1012 995
1013 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */ 996 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
1014 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17); 997 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
@@ -1068,7 +1051,7 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1068 dw_hdmi_phy_enable_powerdown(hdmi, true); 1051 dw_hdmi_phy_enable_powerdown(hdmi, true);
1069 1052
1070 /* Enable CSC */ 1053 /* Enable CSC */
1071 ret = hdmi_phy_configure(hdmi, 8, cscon); 1054 ret = hdmi_phy_configure(hdmi, cscon);
1072 if (ret) 1055 if (ret)
1073 return ret; 1056 return ret;
1074 } 1057 }