diff options
| -rw-r--r-- | arch/mips/kernel/perf_event_mipsxx.c | 4 | ||||
| -rw-r--r-- | arch/mips/mti-malta/malta-int.c | 9 | ||||
| -rw-r--r-- | arch/mips/ralink/timer.c | 2 |
3 files changed, 8 insertions, 7 deletions
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 45f1ffcf1a4b..24cdf64789c3 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c | |||
| @@ -971,11 +971,11 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map | |||
| 971 | [C(LL)] = { | 971 | [C(LL)] = { |
| 972 | [C(OP_READ)] = { | 972 | [C(OP_READ)] = { |
| 973 | [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, | 973 | [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, |
| 974 | [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P }, | 974 | [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P }, |
| 975 | }, | 975 | }, |
| 976 | [C(OP_WRITE)] = { | 976 | [C(OP_WRITE)] = { |
| 977 | [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, | 977 | [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, |
| 978 | [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P }, | 978 | [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P }, |
| 979 | }, | 979 | }, |
| 980 | }, | 980 | }, |
| 981 | [C(ITLB)] = { | 981 | [C(ITLB)] = { |
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index c69da3734699..5b28e81d94a0 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c | |||
| @@ -473,7 +473,7 @@ static void __init fill_ipi_map(void) | |||
| 473 | { | 473 | { |
| 474 | int cpu; | 474 | int cpu; |
| 475 | 475 | ||
| 476 | for (cpu = 0; cpu < NR_CPUS; cpu++) { | 476 | for (cpu = 0; cpu < nr_cpu_ids; cpu++) { |
| 477 | fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1); | 477 | fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1); |
| 478 | fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2); | 478 | fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2); |
| 479 | } | 479 | } |
| @@ -574,8 +574,9 @@ void __init arch_init_irq(void) | |||
| 574 | /* FIXME */ | 574 | /* FIXME */ |
| 575 | int i; | 575 | int i; |
| 576 | #if defined(CONFIG_MIPS_MT_SMP) | 576 | #if defined(CONFIG_MIPS_MT_SMP) |
| 577 | gic_call_int_base = GIC_NUM_INTRS - NR_CPUS; | 577 | gic_call_int_base = GIC_NUM_INTRS - |
| 578 | gic_resched_int_base = gic_call_int_base - NR_CPUS; | 578 | (NR_CPUS - nr_cpu_ids) * 2 - nr_cpu_ids; |
| 579 | gic_resched_int_base = gic_call_int_base - nr_cpu_ids; | ||
| 579 | fill_ipi_map(); | 580 | fill_ipi_map(); |
| 580 | #endif | 581 | #endif |
| 581 | gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, | 582 | gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, |
| @@ -599,7 +600,7 @@ void __init arch_init_irq(void) | |||
| 599 | printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status()); | 600 | printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status()); |
| 600 | write_c0_status(0x1100dc00); | 601 | write_c0_status(0x1100dc00); |
| 601 | printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); | 602 | printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); |
| 602 | for (i = 0; i < NR_CPUS; i++) { | 603 | for (i = 0; i < nr_cpu_ids; i++) { |
| 603 | arch_init_ipiirq(MIPS_GIC_IRQ_BASE + | 604 | arch_init_ipiirq(MIPS_GIC_IRQ_BASE + |
| 604 | GIC_RESCHED_INT(i), &irq_resched); | 605 | GIC_RESCHED_INT(i), &irq_resched); |
| 605 | arch_init_ipiirq(MIPS_GIC_IRQ_BASE + | 606 | arch_init_ipiirq(MIPS_GIC_IRQ_BASE + |
diff --git a/arch/mips/ralink/timer.c b/arch/mips/ralink/timer.c index e49241a2c39a..202785709441 100644 --- a/arch/mips/ralink/timer.c +++ b/arch/mips/ralink/timer.c | |||
| @@ -126,7 +126,7 @@ static int rt_timer_probe(struct platform_device *pdev) | |||
| 126 | return -ENOENT; | 126 | return -ENOENT; |
| 127 | } | 127 | } |
| 128 | 128 | ||
| 129 | rt->membase = devm_request_and_ioremap(&pdev->dev, res); | 129 | rt->membase = devm_ioremap_resource(&pdev->dev, res); |
| 130 | if (IS_ERR(rt->membase)) | 130 | if (IS_ERR(rt->membase)) |
| 131 | return PTR_ERR(rt->membase); | 131 | return PTR_ERR(rt->membase); |
| 132 | 132 | ||
