diff options
| -rw-r--r-- | sound/soc/codecs/tlv320aic32x4.h | 152 |
1 files changed, 77 insertions, 75 deletions
diff --git a/sound/soc/codecs/tlv320aic32x4.h b/sound/soc/codecs/tlv320aic32x4.h index da7cec482bcb..936bb7a1b5c8 100644 --- a/sound/soc/codecs/tlv320aic32x4.h +++ b/sound/soc/codecs/tlv320aic32x4.h | |||
| @@ -19,81 +19,83 @@ int aic32x4_remove(struct device *dev); | |||
| 19 | 19 | ||
| 20 | /* tlv320aic32x4 register space (in decimal to match datasheet) */ | 20 | /* tlv320aic32x4 register space (in decimal to match datasheet) */ |
| 21 | 21 | ||
| 22 | #define AIC32X4_PAGE1 128 | 22 | #define AIC32X4_REG(page, reg) ((page * 128) + reg) |
| 23 | 23 | ||
| 24 | #define AIC32X4_PSEL 0 | 24 | #define AIC32X4_PSEL AIC32X4_REG(0, 0) |
| 25 | #define AIC32X4_RESET 1 | 25 | |
| 26 | #define AIC32X4_CLKMUX 4 | 26 | #define AIC32X4_RESET AIC32X4_REG(0, 1) |
| 27 | #define AIC32X4_PLLPR 5 | 27 | #define AIC32X4_CLKMUX AIC32X4_REG(0, 4) |
| 28 | #define AIC32X4_PLLJ 6 | 28 | #define AIC32X4_PLLPR AIC32X4_REG(0, 5) |
| 29 | #define AIC32X4_PLLDMSB 7 | 29 | #define AIC32X4_PLLJ AIC32X4_REG(0, 6) |
| 30 | #define AIC32X4_PLLDLSB 8 | 30 | #define AIC32X4_PLLDMSB AIC32X4_REG(0, 7) |
| 31 | #define AIC32X4_NDAC 11 | 31 | #define AIC32X4_PLLDLSB AIC32X4_REG(0, 8) |
| 32 | #define AIC32X4_MDAC 12 | 32 | #define AIC32X4_NDAC AIC32X4_REG(0, 11) |
| 33 | #define AIC32X4_DOSRMSB 13 | 33 | #define AIC32X4_MDAC AIC32X4_REG(0, 12) |
| 34 | #define AIC32X4_DOSRLSB 14 | 34 | #define AIC32X4_DOSRMSB AIC32X4_REG(0, 13) |
| 35 | #define AIC32X4_NADC 18 | 35 | #define AIC32X4_DOSRLSB AIC32X4_REG(0, 14) |
| 36 | #define AIC32X4_MADC 19 | 36 | #define AIC32X4_NADC AIC32X4_REG(0, 18) |
| 37 | #define AIC32X4_AOSR 20 | 37 | #define AIC32X4_MADC AIC32X4_REG(0, 19) |
| 38 | #define AIC32X4_CLKMUX2 25 | 38 | #define AIC32X4_AOSR AIC32X4_REG(0, 20) |
| 39 | #define AIC32X4_CLKOUTM 26 | 39 | #define AIC32X4_CLKMUX2 AIC32X4_REG(0, 25) |
| 40 | #define AIC32X4_IFACE1 27 | 40 | #define AIC32X4_CLKOUTM AIC32X4_REG(0, 26) |
| 41 | #define AIC32X4_IFACE2 28 | 41 | #define AIC32X4_IFACE1 AIC32X4_REG(0, 27) |
| 42 | #define AIC32X4_IFACE3 29 | 42 | #define AIC32X4_IFACE2 AIC32X4_REG(0, 28) |
| 43 | #define AIC32X4_BCLKN 30 | 43 | #define AIC32X4_IFACE3 AIC32X4_REG(0, 29) |
| 44 | #define AIC32X4_IFACE4 31 | 44 | #define AIC32X4_BCLKN AIC32X4_REG(0, 30) |
| 45 | #define AIC32X4_IFACE5 32 | 45 | #define AIC32X4_IFACE4 AIC32X4_REG(0, 31) |
| 46 | #define AIC32X4_IFACE6 33 | 46 | #define AIC32X4_IFACE5 AIC32X4_REG(0, 32) |
| 47 | #define AIC32X4_GPIOCTL 52 | 47 | #define AIC32X4_IFACE6 AIC32X4_REG(0, 33) |
| 48 | #define AIC32X4_DOUTCTL 53 | 48 | #define AIC32X4_GPIOCTL AIC32X4_REG(0, 52) |
| 49 | #define AIC32X4_DINCTL 54 | 49 | #define AIC32X4_DOUTCTL AIC32X4_REG(0, 53) |
| 50 | #define AIC32X4_MISOCTL 55 | 50 | #define AIC32X4_DINCTL AIC32X4_REG(0, 54) |
| 51 | #define AIC32X4_SCLKCTL 56 | 51 | #define AIC32X4_MISOCTL AIC32X4_REG(0, 55) |
| 52 | #define AIC32X4_DACSPB 60 | 52 | #define AIC32X4_SCLKCTL AIC32X4_REG(0, 56) |
| 53 | #define AIC32X4_ADCSPB 61 | 53 | #define AIC32X4_DACSPB AIC32X4_REG(0, 60) |
| 54 | #define AIC32X4_DACSETUP 63 | 54 | #define AIC32X4_ADCSPB AIC32X4_REG(0, 61) |
| 55 | #define AIC32X4_DACMUTE 64 | 55 | #define AIC32X4_DACSETUP AIC32X4_REG(0, 63) |
| 56 | #define AIC32X4_LDACVOL 65 | 56 | #define AIC32X4_DACMUTE AIC32X4_REG(0, 64) |
| 57 | #define AIC32X4_RDACVOL 66 | 57 | #define AIC32X4_LDACVOL AIC32X4_REG(0, 65) |
| 58 | #define AIC32X4_ADCSETUP 81 | 58 | #define AIC32X4_RDACVOL AIC32X4_REG(0, 66) |
| 59 | #define AIC32X4_ADCFGA 82 | 59 | #define AIC32X4_ADCSETUP AIC32X4_REG(0, 81) |
| 60 | #define AIC32X4_LADCVOL 83 | 60 | #define AIC32X4_ADCFGA AIC32X4_REG(0, 82) |
| 61 | #define AIC32X4_RADCVOL 84 | 61 | #define AIC32X4_LADCVOL AIC32X4_REG(0, 83) |
| 62 | #define AIC32X4_LAGC1 86 | 62 | #define AIC32X4_RADCVOL AIC32X4_REG(0, 84) |
| 63 | #define AIC32X4_LAGC2 87 | 63 | #define AIC32X4_LAGC1 AIC32X4_REG(0, 86) |
| 64 | #define AIC32X4_LAGC3 88 | 64 | #define AIC32X4_LAGC2 AIC32X4_REG(0, 87) |
| 65 | #define AIC32X4_LAGC4 89 | 65 | #define AIC32X4_LAGC3 AIC32X4_REG(0, 88) |
| 66 | #define AIC32X4_LAGC5 90 | 66 | #define AIC32X4_LAGC4 AIC32X4_REG(0, 89) |
| 67 | #define AIC32X4_LAGC6 91 | 67 | #define AIC32X4_LAGC5 AIC32X4_REG(0, 90) |
| 68 | #define AIC32X4_LAGC7 92 | 68 | #define AIC32X4_LAGC6 AIC32X4_REG(0, 91) |
| 69 | #define AIC32X4_RAGC1 94 | 69 | #define AIC32X4_LAGC7 AIC32X4_REG(0, 92) |
| 70 | #define AIC32X4_RAGC2 95 | 70 | #define AIC32X4_RAGC1 AIC32X4_REG(0, 94) |
| 71 | #define AIC32X4_RAGC3 96 | 71 | #define AIC32X4_RAGC2 AIC32X4_REG(0, 95) |
| 72 | #define AIC32X4_RAGC4 97 | 72 | #define AIC32X4_RAGC3 AIC32X4_REG(0, 96) |
| 73 | #define AIC32X4_RAGC5 98 | 73 | #define AIC32X4_RAGC4 AIC32X4_REG(0, 97) |
| 74 | #define AIC32X4_RAGC6 99 | 74 | #define AIC32X4_RAGC5 AIC32X4_REG(0, 98) |
| 75 | #define AIC32X4_RAGC7 100 | 75 | #define AIC32X4_RAGC6 AIC32X4_REG(0, 99) |
| 76 | #define AIC32X4_PWRCFG (AIC32X4_PAGE1 + 1) | 76 | #define AIC32X4_RAGC7 AIC32X4_REG(0, 100) |
| 77 | #define AIC32X4_LDOCTL (AIC32X4_PAGE1 + 2) | 77 | |
| 78 | #define AIC32X4_OUTPWRCTL (AIC32X4_PAGE1 + 9) | 78 | #define AIC32X4_PWRCFG AIC32X4_REG(1, 1) |
| 79 | #define AIC32X4_CMMODE (AIC32X4_PAGE1 + 10) | 79 | #define AIC32X4_LDOCTL AIC32X4_REG(1, 2) |
| 80 | #define AIC32X4_HPLROUTE (AIC32X4_PAGE1 + 12) | 80 | #define AIC32X4_OUTPWRCTL AIC32X4_REG(1, 9) |
| 81 | #define AIC32X4_HPRROUTE (AIC32X4_PAGE1 + 13) | 81 | #define AIC32X4_CMMODE AIC32X4_REG(1, 10) |
| 82 | #define AIC32X4_LOLROUTE (AIC32X4_PAGE1 + 14) | 82 | #define AIC32X4_HPLROUTE AIC32X4_REG(1, 12) |
| 83 | #define AIC32X4_LORROUTE (AIC32X4_PAGE1 + 15) | 83 | #define AIC32X4_HPRROUTE AIC32X4_REG(1, 13) |
| 84 | #define AIC32X4_HPLGAIN (AIC32X4_PAGE1 + 16) | 84 | #define AIC32X4_LOLROUTE AIC32X4_REG(1, 14) |
| 85 | #define AIC32X4_HPRGAIN (AIC32X4_PAGE1 + 17) | 85 | #define AIC32X4_LORROUTE AIC32X4_REG(1, 15) |
| 86 | #define AIC32X4_LOLGAIN (AIC32X4_PAGE1 + 18) | 86 | #define AIC32X4_HPLGAIN AIC32X4_REG(1, 16) |
| 87 | #define AIC32X4_LORGAIN (AIC32X4_PAGE1 + 19) | 87 | #define AIC32X4_HPRGAIN AIC32X4_REG(1, 17) |
| 88 | #define AIC32X4_HEADSTART (AIC32X4_PAGE1 + 20) | 88 | #define AIC32X4_LOLGAIN AIC32X4_REG(1, 18) |
| 89 | #define AIC32X4_MICBIAS (AIC32X4_PAGE1 + 51) | 89 | #define AIC32X4_LORGAIN AIC32X4_REG(1, 19) |
| 90 | #define AIC32X4_LMICPGAPIN (AIC32X4_PAGE1 + 52) | 90 | #define AIC32X4_HEADSTART AIC32X4_REG(1, 20) |
| 91 | #define AIC32X4_LMICPGANIN (AIC32X4_PAGE1 + 54) | 91 | #define AIC32X4_MICBIAS AIC32X4_REG(1, 51) |
| 92 | #define AIC32X4_RMICPGAPIN (AIC32X4_PAGE1 + 55) | 92 | #define AIC32X4_LMICPGAPIN AIC32X4_REG(1, 52) |
| 93 | #define AIC32X4_RMICPGANIN (AIC32X4_PAGE1 + 57) | 93 | #define AIC32X4_LMICPGANIN AIC32X4_REG(1, 54) |
| 94 | #define AIC32X4_FLOATINGINPUT (AIC32X4_PAGE1 + 58) | 94 | #define AIC32X4_RMICPGAPIN AIC32X4_REG(1, 55) |
| 95 | #define AIC32X4_LMICPGAVOL (AIC32X4_PAGE1 + 59) | 95 | #define AIC32X4_RMICPGANIN AIC32X4_REG(1, 57) |
| 96 | #define AIC32X4_RMICPGAVOL (AIC32X4_PAGE1 + 60) | 96 | #define AIC32X4_FLOATINGINPUT AIC32X4_REG(1, 58) |
| 97 | #define AIC32X4_LMICPGAVOL AIC32X4_REG(1, 59) | ||
| 98 | #define AIC32X4_RMICPGAVOL AIC32X4_REG(1, 60) | ||
| 97 | 99 | ||
| 98 | #define AIC32X4_FREQ_12000000 12000000 | 100 | #define AIC32X4_FREQ_12000000 12000000 |
| 99 | #define AIC32X4_FREQ_24000000 24000000 | 101 | #define AIC32X4_FREQ_24000000 24000000 |