7 files changed, 468 insertions, 46 deletions

diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
index e2c88df2cc15..5c090771c016 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
@@ -33,6 +33,11 @@ Optional properties:
                 nodes.  If unspecified, a single SPI device without a chip
                 select can be used.
 
+- dmas:         Two DMA channel specifiers following the convention outlined
+                in bindings/dma/dma.txt
+- dma-names:    Names for the dma channels, if present. There must be at
+                least one channel named "tx" for transmit and named "rx" for
+                receive.
 
 SPI slave nodes must be children of the SPI master node and can contain
 properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -51,6 +56,9 @@ Example:
                 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
                 clock-names = "core", "iface";
 
+                dmas = <&blsp1_bam 13>, <&blsp1_bam 12>;
+                dma-names = "rx", "tx";
+
                 pinctrl-names = "default";
                 pinctrl-0 = <&spi8_default>;
 
diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
index 467dec441c62..0c491bda4c65 100644
--- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt
+++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
@@ -24,6 +24,9 @@ Optional Properties:
 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
                 Documentation/devicetree/bindings/dma/dma.txt
 - dma-names: DMA request names should include "tx" and "rx" if present.
+- rx-sample-delay-ns: nanoseconds to delay after the SCLK edge before sampling
+                Rx data (may need to be fine tuned for high capacitance lines).
+                No delay (0) by default.
 
 
 Example:
@@ -33,6 +36,7 @@ Example:
                 reg = <0xff110000 0x1000>;
                 dmas = <&pdma1 11>, <&pdma1 12>;
                 dma-names = "tx", "rx";
+                rx-sample-delay-ns = <10>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 2b2c359f5a50..810a7fae3479 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -22,6 +22,8 @@
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/spi/spi.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
 
 #define QUP_CONFIG                      0x0000
 #define QUP_STATE                       0x0004
@@ -116,6 +118,8 @@
 
 #define SPI_NUM_CHIPSELECTS             4
 
+#define SPI_MAX_DMA_XFER                (SZ_64K - 64)
+
 /* high speed mode is when bus rate is greater then 26MHz */
 #define SPI_HS_MIN_RATE                 26000000
 #define SPI_MAX_RATE                    50000000
@@ -140,9 +144,14 @@ struct spi_qup {
         struct completion       done;
         int                     error;
         int                     w_size; /* bytes per SPI word */
+        int                     n_words;
         int                     tx_bytes;
         int                     rx_bytes;
         int                     qup_v1;
+
+        int                     use_dma;
+        struct dma_slave_config rx_conf;
+        struct dma_slave_config tx_conf;
 };
 
 
@@ -198,7 +207,6 @@ static int spi_qup_set_state(struct spi_qup *controller, u32 state)
         return 0;
 }
 
-
 static void spi_qup_fifo_read(struct spi_qup *controller,
                             struct spi_transfer *xfer)
 {
@@ -266,6 +274,107 @@ static void spi_qup_fifo_write(struct spi_qup *controller,
         }
 }
 
+static void spi_qup_dma_done(void *data)
+{
+        struct spi_qup *qup = data;
+
+        complete(&qup->done);
+}
+
+static int spi_qup_prep_sg(struct spi_master *master, struct spi_transfer *xfer,
+                           enum dma_transfer_direction dir,
+                           dma_async_tx_callback callback)
+{
+        struct spi_qup *qup = spi_master_get_devdata(master);
+        unsigned long flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE;
+        struct dma_async_tx_descriptor *desc;
+        struct scatterlist *sgl;
+        struct dma_chan *chan;
+        dma_cookie_t cookie;
+        unsigned int nents;
+
+        if (dir == DMA_MEM_TO_DEV) {
+                chan = master->dma_tx;
+                nents = xfer->tx_sg.nents;
+                sgl = xfer->tx_sg.sgl;
+        } else {
+                chan = master->dma_rx;
+                nents = xfer->rx_sg.nents;
+                sgl = xfer->rx_sg.sgl;
+        }
+
+        desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
+        if (!desc)
+                return -EINVAL;
+
+        desc->callback = callback;
+        desc->callback_param = qup;
+
+        cookie = dmaengine_submit(desc);
+
+        return dma_submit_error(cookie);
+}
+
+static void spi_qup_dma_terminate(struct spi_master *master,
+                                  struct spi_transfer *xfer)
+{
+        if (xfer->tx_buf)
+                dmaengine_terminate_all(master->dma_tx);
+        if (xfer->rx_buf)
+                dmaengine_terminate_all(master->dma_rx);
+}
+
+static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer)
+{
+        dma_async_tx_callback rx_done = NULL, tx_done = NULL;
+        int ret;
+
+        if (xfer->rx_buf)
+                rx_done = spi_qup_dma_done;
+        else if (xfer->tx_buf)
+                tx_done = spi_qup_dma_done;
+
+        if (xfer->rx_buf) {
+                ret = spi_qup_prep_sg(master, xfer, DMA_DEV_TO_MEM, rx_done);
+                if (ret)
+                        return ret;
+
+                dma_async_issue_pending(master->dma_rx);
+        }
+
+        if (xfer->tx_buf) {
+                ret = spi_qup_prep_sg(master, xfer, DMA_MEM_TO_DEV, tx_done);
+                if (ret)
+                        return ret;
+
+                dma_async_issue_pending(master->dma_tx);
+        }
+
+        return 0;
+}
+
+static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer)
+{
+        struct spi_qup *qup = spi_master_get_devdata(master);
+        int ret;
+
+        ret = spi_qup_set_state(qup, QUP_STATE_RUN);
+        if (ret) {
+                dev_warn(qup->dev, "cannot set RUN state\n");
+                return ret;