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-rw-r--r--arch/arm/boot/dts/socfpga.dtsi56
-rw-r--r--arch/arm/boot/dts/socfpga_arria10.dtsi51
-rw-r--r--arch/arm/boot/dts/socfpga_arria10_socdk.dtsi7
-rw-r--r--arch/arm/boot/dts/socfpga_arria5_socdk.dts2
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts2
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi2
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts1
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_socdk.dts2
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_sockit.dts2
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_socrates.dts8
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_sodia.dts23
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts2
-rw-r--r--arch/arm/boot/dts/socfpga_vt.dts2
13 files changed, 96 insertions, 64 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 2c43c4d85dee..b2674bdb8e6a 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -15,7 +15,6 @@
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */ 16 */
17 17
18#include "skeleton.dtsi"
19#include <dt-bindings/reset/altr,rst-mgr.h> 18#include <dt-bindings/reset/altr,rst-mgr.h>
20 19
21/ { 20/ {
@@ -38,13 +37,13 @@
38 #size-cells = <0>; 37 #size-cells = <0>;
39 enable-method = "altr,socfpga-smp"; 38 enable-method = "altr,socfpga-smp";
40 39
41 cpu@0 { 40 cpu0: cpu@0 {
42 compatible = "arm,cortex-a9"; 41 compatible = "arm,cortex-a9";
43 device_type = "cpu"; 42 device_type = "cpu";
44 reg = <0>; 43 reg = <0>;
45 next-level-cache = <&L2>; 44 next-level-cache = <&L2>;
46 }; 45 };
47 cpu@1 { 46 cpu1: cpu@1 {
48 compatible = "arm,cortex-a9"; 47 compatible = "arm,cortex-a9";
49 device_type = "cpu"; 48 device_type = "cpu";
50 reg = <1>; 49 reg = <1>;
@@ -52,6 +51,15 @@
52 }; 51 };
53 }; 52 };
54 53
54 pmu: pmu@ff111000 {
55 compatible = "arm,cortex-a9-pmu";
56 interrupt-parent = <&intc>;
57 interrupts = <0 176 4>, <0 177 4>;
58 interrupt-affinity = <&cpu0>, <&cpu1>;
59 reg = <0xff111000 0x1000>,
60 <0xff113000 0x1000>;
61 };
62
55 intc: intc@fffed000 { 63 intc: intc@fffed000 {
56 compatible = "arm,cortex-a9-gic"; 64 compatible = "arm,cortex-a9-gic";
57 #interrupt-cells = <3>; 65 #interrupt-cells = <3>;
@@ -145,7 +153,7 @@
145 compatible = "fixed-clock"; 153 compatible = "fixed-clock";
146 }; 154 };
147 155
148 main_pll: main_pll { 156 main_pll: main_pll@40 {
149 #address-cells = <1>; 157 #address-cells = <1>;
150 #size-cells = <0>; 158 #size-cells = <0>;
151 #clock-cells = <0>; 159 #clock-cells = <0>;
@@ -153,7 +161,7 @@
153 clocks = <&osc1>; 161 clocks = <&osc1>;
154 reg = <0x40>; 162 reg = <0x40>;
155 163
156 mpuclk: mpuclk { 164 mpuclk: mpuclk@48 {
157 #clock-cells = <0>; 165 #clock-cells = <0>;
158 compatible = "altr,socfpga-perip-clk"; 166 compatible = "altr,socfpga-perip-clk";
159 clocks = <&main_pll>; 167 clocks = <&main_pll>;
@@ -161,7 +169,7 @@
161 reg = <0x48>; 169 reg = <0x48>;
162 }; 170 };
163 171
164 mainclk: mainclk { 172 mainclk: mainclk@4c {
165 #clock-cells = <0>; 173 #clock-cells = <0>;
166 compatible = "altr,socfpga-perip-clk"; 174 compatible = "altr,socfpga-perip-clk";
167 clocks = <&main_pll>; 175 clocks = <&main_pll>;
@@ -169,7 +177,7 @@
169 reg = <0x4C>; 177 reg = <0x4C>;
170 }; 178 };
171 179
172 dbg_base_clk: dbg_base_clk { 180 dbg_base_clk: dbg_base_clk@50 {
173 #clock-cells = <0>; 181 #clock-cells = <0>;
174 compatible = "altr,socfpga-perip-clk"; 182 compatible = "altr,socfpga-perip-clk";
175 clocks = <&main_pll>, <&osc1>; 183 clocks = <&main_pll>, <&osc1>;
@@ -177,21 +185,21 @@
177 reg = <0x50>; 185 reg = <0x50>;
178 }; 186 };
179 187
180 main_qspi_clk: main_qspi_clk { 188 main_qspi_clk: main_qspi_clk@54 {
181 #clock-cells = <0>; 189 #clock-cells = <0>;
182 compatible = "altr,socfpga-perip-clk"; 190 compatible = "altr,socfpga-perip-clk";
183 clocks = <&main_pll>; 191 clocks = <&main_pll>;
184 reg = <0x54>; 192 reg = <0x54>;
185 }; 193 };
186 194
187 main_nand_sdmmc_clk: main_nand_sdmmc_clk { 195 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
188 #clock-cells = <0>; 196 #clock-cells = <0>;
189 compatible = "altr,socfpga-perip-clk"; 197 compatible = "altr,socfpga-perip-clk";
190 clocks = <&main_pll>; 198 clocks = <&main_pll>;
191 reg = <0x58>; 199 reg = <0x58>;
192 }; 200 };
193 201
194 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { 202 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
195 #clock-cells = <0>; 203 #clock-cells = <0>;
196 compatible = "altr,socfpga-perip-clk"; 204 compatible = "altr,socfpga-perip-clk";
197 clocks = <&main_pll>; 205 clocks = <&main_pll>;
@@ -199,7 +207,7 @@
199 }; 207 };
200 }; 208 };
201 209
202 periph_pll: periph_pll { 210 periph_pll: periph_pll@80 {
203 #address-cells = <1>; 211 #address-cells = <1>;
204 #size-cells = <0>; 212 #size-cells = <0>;
205 #clock-cells = <0>; 213 #clock-cells = <0>;
@@ -207,42 +215,42 @@
207 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; 215 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
208 reg = <0x80>; 216 reg = <0x80>;
209 217
210 emac0_clk: emac0_clk { 218 emac0_clk: emac0_clk@88 {
211 #clock-cells = <0>; 219 #clock-cells = <0>;
212 compatible = "altr,socfpga-perip-clk"; 220 compatible = "altr,socfpga-perip-clk";
213 clocks = <&periph_pll>; 221 clocks = <&periph_pll>;
214 reg = <0x88>; 222 reg = <0x88>;
215 }; 223 };
216 224
217 emac1_clk: emac1_clk { 225 emac1_clk: emac1_clk@8c {
218 #clock-cells = <0>; 226 #clock-cells = <0>;
219 compatible = "altr,socfpga-perip-clk"; 227 compatible = "altr,socfpga-perip-clk";
220 clocks = <&periph_pll>; 228 clocks = <&periph_pll>;
221 reg = <0x8C>; 229 reg = <0x8C>;
222 }; 230 };
223 231
224 per_qspi_clk: per_qsi_clk { 232 per_qspi_clk: per_qsi_clk@90 {
225 #clock-cells = <0>; 233 #clock-cells = <0>;
226 compatible = "altr,socfpga-perip-clk"; 234 compatible = "altr,socfpga-perip-clk";
227 clocks = <&periph_pll>; 235 clocks = <&periph_pll>;
228 reg = <0x90>; 236 reg = <0x90>;
229 }; 237 };
230 238
231 per_nand_mmc_clk: per_nand_mmc_clk { 239 per_nand_mmc_clk: per_nand_mmc_clk@94 {
232 #clock-cells = <0>; 240 #clock-cells = <0>;
233 compatible = "altr,socfpga-perip-clk"; 241 compatible = "altr,socfpga-perip-clk";
234 clocks = <&periph_pll>; 242 clocks = <&periph_pll>;
235 reg = <0x94>; 243 reg = <0x94>;
236 }; 244 };
237 245
238 per_base_clk: per_base_clk { 246 per_base_clk: per_base_clk@98 {
239 #clock-cells = <0>; 247 #clock-cells = <0>;
240 compatible = "altr,socfpga-perip-clk"; 248 compatible = "altr,socfpga-perip-clk";
241 clocks = <&periph_pll>; 249 clocks = <&periph_pll>;
242 reg = <0x98>; 250 reg = <0x98>;
243 }; 251 };
244 252
245 h2f_usr1_clk: h2f_usr1_clk { 253 h2f_usr1_clk: h2f_usr1_clk@9c {
246 #clock-cells = <0>; 254 #clock-cells = <0>;
247 compatible = "altr,socfpga-perip-clk"; 255 compatible = "altr,socfpga-perip-clk";
248 clocks = <&periph_pll>; 256 clocks = <&periph_pll>;
@@ -250,7 +258,7 @@
250 }; 258 };
251 }; 259 };
252 260
253 sdram_pll: sdram_pll { 261 sdram_pll: sdram_pll@c0 {
254 #address-cells = <1>; 262 #address-cells = <1>;
255 #size-cells = <0>; 263 #size-cells = <0>;
256 #clock-cells = <0>; 264 #clock-cells = <0>;
@@ -258,28 +266,28 @@
258 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; 266 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
259 reg = <0xC0>; 267 reg = <0xC0>;
260 268
261 ddr_dqs_clk: ddr_dqs_clk { 269 ddr_dqs_clk: ddr_dqs_clk@c8 {
262 #clock-cells = <0>; 270 #clock-cells = <0>;
263 compatible = "altr,socfpga-perip-clk"; 271 compatible = "altr,socfpga-perip-clk";
264 clocks = <&sdram_pll>; 272 clocks = <&sdram_pll>;
265 reg = <0xC8>; 273 reg = <0xC8>;
266 }; 274 };
267 275
268 ddr_2x_dqs_clk: ddr_2x_dqs_clk { 276 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
269 #clock-cells = <0>; 277 #clock-cells = <0>;
270 compatible = "altr,socfpga-perip-clk"; 278 compatible = "altr,socfpga-perip-clk";
271 clocks = <&sdram_pll>; 279 clocks = <&sdram_pll>;
272 reg = <0xCC>; 280 reg = <0xCC>;
273 }; 281 };
274 282
275 ddr_dq_clk: ddr_dq_clk { 283 ddr_dq_clk: ddr_dq_clk@d0 {
276 #clock-cells = <0>; 284 #clock-cells = <0>;
277 compatible = "altr,socfpga-perip-clk"; 285 compatible = "altr,socfpga-perip-clk";
278 clocks = <&sdram_pll>; 286 clocks = <&sdram_pll>;
279 reg = <0xD0>; 287 reg = <0xD0>;
280 }; 288 };
281 289
282 h2f_usr2_clk: h2f_usr2_clk { 290 h2f_usr2_clk: h2f_usr2_clk@d4 {
283 #clock-cells = <0>; 291 #clock-cells = <0>;
284 compatible = "altr,socfpga-perip-clk"; 292 compatible = "altr,socfpga-perip-clk";
285 clocks = <&sdram_pll>; 293 clocks = <&sdram_pll>;
@@ -678,7 +686,7 @@
678 status = "disabled"; 686 status = "disabled";
679 }; 687 };
680 688
681 eccmgr: eccmgr@ffd08140 { 689 eccmgr: eccmgr {
682 compatible = "altr,socfpga-ecc-manager"; 690 compatible = "altr,socfpga-ecc-manager";
683 #address-cells = <1>; 691 #address-cells = <1>;
684 #size-cells = <1>; 692 #size-cells = <1>;
@@ -879,7 +887,7 @@
879 dma-names = "tx", "rx"; 887 dma-names = "tx", "rx";
880 }; 888 };
881 889
882 usbphy0: usbphy@0 { 890 usbphy0: usbphy {
883 #phy-cells = <0>; 891 #phy-cells = <0>;
884 compatible = "usb-nop-xceiv"; 892 compatible = "usb-nop-xceiv";
885 status = "okay"; 893 status = "okay";
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 6b0b7463f36f..bead79e4b2aa 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -14,7 +14,6 @@
14 * this program. If not, see <http://www.gnu.org/licenses/>. 14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */ 15 */
16 16
17#include "skeleton.dtsi"
18#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h>
19#include <dt-bindings/reset/altr,rst-mgr-a10.h> 18#include <dt-bindings/reset/altr,rst-mgr-a10.h>
20 19
@@ -119,7 +118,7 @@
119 compatible = "fixed-clock"; 118 compatible = "fixed-clock";
120 }; 119 };
121 120
122 main_pll: main_pll { 121 main_pll: main_pll@40 {
123 #address-cells = <1>; 122 #address-cells = <1>;
124 #size-cells = <0>; 123 #size-cells = <0>;
125 #clock-cells = <0>; 124 #clock-cells = <0>;
@@ -142,35 +141,35 @@
142 div-reg = <0x144 0 11>; 141 div-reg = <0x144 0 11>;
143 }; 142 };
144 143
145 main_emaca_clk: main_emaca_clk { 144 main_emaca_clk: main_emaca_clk@68 {
146 #clock-cells = <0>; 145 #clock-cells = <0>;
147 compatible = "altr,socfpga-a10-perip-clk"; 146 compatible = "altr,socfpga-a10-perip-clk";
148 clocks = <&main_pll>; 147 clocks = <&main_pll>;
149 reg = <0x68>; 148 reg = <0x68>;
150 }; 149 };
151 150
152 main_emacb_clk: main_emacb_clk { 151 main_emacb_clk: main_emacb_clk@6c {
153 #clock-cells = <0>; 152 #clock-cells = <0>;
154 compatible = "altr,socfpga-a10-perip-clk"; 153 compatible = "altr,socfpga-a10-perip-clk";
155 clocks = <&main_pll>; 154 clocks = <&main_pll>;
156 reg = <0x6C>; 155 reg = <0x6C>;
157 }; 156 };
158 157
159 main_emac_ptp_clk: main_emac_ptp_clk { 158 main_emac_ptp_clk: main_emac_ptp_clk@70 {
160 #clock-cells = <0>; 159 #clock-cells = <0>;
161 compatible = "altr,socfpga-a10-perip-clk"; 160 compatible = "altr,socfpga-a10-perip-clk";
162 clocks = <&main_pll>; 161 clocks = <&main_pll>;
163 reg = <0x70>; 162 reg = <0x70>;
164 }; 163 };
165 164
166 main_gpio_db_clk: main_gpio_db_clk { 165 main_gpio_db_clk: main_gpio_db_clk@74 {
167 #clock-cells = <0>; 166 #clock-cells = <0>;
168 compatible = "altr,socfpga-a10-perip-clk"; 167 compatible = "altr,socfpga-a10-perip-clk";
169 clocks = <&main_pll>; 168 clocks = <&main_pll>;
170 reg = <0x74>; 169 reg = <0x74>;
171 }; 170 };
172 171
173 main_sdmmc_clk: main_sdmmc_clk { 172 main_sdmmc_clk: main_sdmmc_clk@78 {
174 #clock-cells = <0>; 173 #clock-cells = <0>;
175 compatible = "altr,socfpga-a10-perip-clk" 174 compatible = "altr,socfpga-a10-perip-clk"
176; 175;
@@ -178,28 +177,28 @@
178 reg = <0x78>; 177 reg = <0x78>;
179 }; 178 };
180 179
181 main_s2f_usr0_clk: main_s2f_usr0_clk { 180 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
182 #clock-cells = <0>; 181 #clock-cells = <0>;
183 compatible = "altr,socfpga-a10-perip-clk"; 182 compatible = "altr,socfpga-a10-perip-clk";
184 clocks = <&main_pll>; 183 clocks = <&main_pll>;
185 reg = <0x7C>; 184 reg = <0x7C>;
186 }; 185 };
187 186
188 main_s2f_usr1_clk: main_s2f_usr1_clk { 187 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
189 #clock-cells = <0>; 188 #clock-cells = <0>;
190 compatible = "altr,socfpga-a10-perip-clk"; 189 compatible = "altr,socfpga-a10-perip-clk";
191 clocks = <&main_pll>; 190 clocks = <&main_pll>;
192 reg = <0x80>; 191 reg = <0x80>;
193 }; 192 };
194 193
195 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk { 194 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
196 #clock-cells = <0>; 195 #clock-cells = <0>;
197 compatible = "altr,socfpga-a10-perip-clk"; 196 compatible = "altr,socfpga-a10-perip-clk";
198 clocks = <&main_pll>; 197 clocks = <&main_pll>;
199 reg = <0x84>; 198 reg = <0x84>;
200 }; 199 };
201 200
202 main_periph_ref_clk: main_periph_ref_clk { 201 main_periph_ref_clk: main_periph_ref_clk@9c {
203 #clock-cells = <0>; 202 #clock-cells = <0>;
204 compatible = "altr,socfpga-a10-perip-clk"; 203 compatible = "altr,socfpga-a10-perip-clk";
205 clocks = <&main_pll>; 204 clocks = <&main_pll>;
@@ -207,7 +206,7 @@
207 }; 206 };
208 }; 207 };
209 208
210 periph_pll: periph_pll { 209 periph_pll: periph_pll@c0 {
211 #address-cells = <1>; 210 #address-cells = <1>;
212 #size-cells = <0>; 211 #size-cells = <0>;
213 #clock-cells = <0>; 212 #clock-cells = <0>;
@@ -230,56 +229,56 @@
230 div-reg = <0x144 16 11>; 229 div-reg = <0x144 16 11>;
231 }; 230 };
232 231
233 peri_emaca_clk: peri_emaca_clk { 232 peri_emaca_clk: peri_emaca_clk@e8 {
234 #clock-cells = <0>; 233 #clock-cells = <0>;
235 compatible = "altr,socfpga-a10-perip-clk"; 234 compatible = "altr,socfpga-a10-perip-clk";
236 clocks = <&periph_pll>; 235 clocks = <&periph_pll>;
237 reg = <0xE8>; 236 reg = <0xE8>;
238 }; 237 };
239 238
240 peri_emacb_clk: peri_emacb_clk { 239 peri_emacb_clk: peri_emacb_clk@ec {
241 #clock-cells = <0>; 240 #clock-cells = <0>;
242 compatible = "altr,socfpga-a10-perip-clk"; 241 compatible = "altr,socfpga-a10-perip-clk";
243 clocks = <&periph_pll>; 242 clocks = <&periph_pll>;
244 reg = <0xEC>; 243 reg = <0xEC>;
245 }; 244 };
246 245
247 peri_emac_ptp_clk: peri_emac_ptp_clk { 246 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
248 #clock-cells = <0>; 247 #clock-cells = <0>;
249 compatible = "altr,socfpga-a10-perip-clk"; 248 compatible = "altr,socfpga-a10-perip-clk";
250 clocks = <&periph_pll>; 249 clocks = <&periph_pll>;
251 reg = <0xF0>; 250 reg = <0xF0>;
252 }; 251 };
253 252
254 peri_gpio_db_clk: peri_gpio_db_clk { 253 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
255 #clock-cells = <0>; 254 #clock-cells = <0>;
256 compatible = "altr,socfpga-a10-perip-clk"; 255 compatible = "altr,socfpga-a10-perip-clk";
257 clocks = <&periph_pll>; 256 clocks = <&periph_pll>;
258 reg = <0xF4>; 257 reg = <0xF4>;
259 }; 258 };
260 259
261 peri_sdmmc_clk: peri_sdmmc_clk { 260 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
262 #clock-cells = <0>; 261 #clock-cells = <0>;
263 compatible = "altr,socfpga-a10-perip-clk"; 262 compatible = "altr,socfpga-a10-perip-clk";
264 clocks = <&periph_pll>; 263 clocks = <&periph_pll>;
265 reg = <0xF8>; 264 reg = <0xF8>;
266 }; 265 };
267 266
268 peri_s2f_usr0_clk: peri_s2f_usr0_clk { 267 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
269 #clock-cells = <0>; 268 #clock-cells = <0>;
270 compatible = "altr,socfpga-a10-perip-clk"; 269 compatible = "altr,socfpga-a10-perip-clk";
271 clocks = <&periph_pll>; 270 clocks = <&periph_pll>;
272 reg = <0xFC>; 271 reg = <0xFC>;
273 }; 272 };
274 273
275 peri_s2f_usr1_clk: peri_s2f_usr1_clk { 274 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
276 #clock-cells = <0>; 275 #clock-cells = <0>;
277 compatible = "altr,socfpga-a10-perip-clk"; 276 compatible = "altr,socfpga-a10-perip-clk";
278 clocks = <&periph_pll>; 277 clocks = <&periph_pll>;
279 reg = <0x100>; 278 reg = <0x100>;
280 }; 279 };
281 280
282 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk { 281 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
283 #clock-cells = <0>; 282 #clock-cells = <0>;
284 compatible = "altr,socfpga-a10-perip-clk"; 283 compatible = "altr,socfpga-a10-perip-clk";
285 clocks = <&periph_pll>; 284 clocks = <&periph_pll>;
@@ -287,7 +286,7 @@
287 }; 286 };
288 }; 287 };
289 288
290 mpu_free_clk: mpu_free_clk { 289 mpu_free_clk: mpu_free_clk@60 {
291 #clock-cells = <0>; 290 #clock-cells = <0>;
292 compatible = "altr,socfpga-a10-perip-clk"; 291 compatible = "altr,socfpga-a10-perip-clk";
293 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, 292 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
@@ -296,7 +295,7 @@
296 reg = <0x60>; 295 reg = <0x60>;
297 }; 296 };
298 297
299 noc_free_clk: noc_free_clk { 298 noc_free_clk: noc_free_clk@64 {
300 #clock-cells = <0>; 299 #clock-cells = <0>;
301 compatible = "altr,socfpga-a10-perip-clk"; 300 compatible = "altr,socfpga-a10-perip-clk";
302 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, 301 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
@@ -305,7 +304,7 @@
305 reg = <0x64>; 304 reg = <0x64>;
306 }; 305 };
307 306
308 s2f_user1_free_clk: s2f_user1_free_clk { 307 s2f_user1_free_clk: s2f_user1_free_clk@104 {
309 #clock-cells = <0>; 308 #clock-cells = <0>;
310 compatible = "altr,socfpga-a10-perip-clk"; 309 compatible = "altr,socfpga-a10-perip-clk";
311 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, 310 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
@@ -314,7 +313,7 @@
314 reg = <0x104>; 313 reg = <0x104>;
315 }; 314 };
316 315
317 sdmmc_free_clk: sdmmc_free_clk { 316 sdmmc_free_clk: sdmmc_free_clk@f8 {
318 #clock-cells = <0>; 317 #clock-cells = <0>;
319 compatible = "altr,socfpga-a10-perip-clk"; 318 compatible = "altr,socfpga-a10-perip-clk";
320 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, 319 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
@@ -649,7 +648,7 @@
649 reg = <0xffe00000 0x40000>; 648 reg = <0xffe00000 0x40000>;
650 }; 649 };
651 650
652 eccmgr: eccmgr@ffd06000 { 651 eccmgr: eccmgr {
653 compatible = "altr,socfpga-a10-ecc-manager"; 652 compatible = "altr,socfpga-a10-ecc-manager";
654 altr,sysmgr-syscon = <&sysmgr>; 653 altr,sysmgr-syscon = <&sysmgr>;
655 #address-cells = <1>; 654 #address-cells = <1>;
@@ -806,7 +805,7 @@
806 status = "disabled"; 805 status = "disabled";
807 }; 806 };
808 807
809 usbphy0: usbphy@0 { 808 usbphy0: usbphy {
810 #phy-cells = <0>; 809 #phy-cells = <0>;
811 compatible = "usb-nop-xceiv"; 810 compatible = "usb-nop-xceiv";
812 status = "okay"; 811 status = "okay";
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index c57e6cea0d83..94e088473823 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -30,7 +30,7 @@
30 stdout-path = "serial0:115200n8"; 30 stdout-path = "serial0:115200n8";
31 }; 31 };
32 32
33 memory { 33 memory@0 {
34 name = "memory"; 34 name = "memory";
35 device_type = "memory"; 35 device_type = "memory";
36 reg = <0x0 0x40000000>; /* 1GB */ 36 reg = <0x0 0x40000000>; /* 1GB */
@@ -121,6 +121,11 @@
121 gpio-controller; 121 gpio-controller;
122 #gpio-cells = <2>; 122 #gpio-cells = <2>;
123 }; 123 };
124
125 a10sr_rst: reset-controller {
126 compatible = "altr,a10sr-reset";
127 #reset-cells = <1>;
128 };
124 }; 129 };
125}; 130};
126 131
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index 8672edf9ba4e..aac4feea86f3 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -26,7 +26,7 @@
26 stdout-path = "serial0:115200n8"; 26 stdout-path = "serial0:115200n8";
27 }; 27 };
28 28
29 memory { 29 memory@0 {
30 name = "memory"; 30 name = "memory";
31 device_type = "memory"; 31 device_type = "memory";
32 reg = <0x0 0x40000000>; /* 1GB */ 32 reg = <0x0 0x40000000>; /* 1GB */
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
index 5ecd2ef405e3..7b49395452b6 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
@@ -25,7 +25,7 @@
25 stdout-path = "serial0:115200n8"; 25 stdout-path = "serial0:115200n8";
26 }; 26 };
27 27
28 memory { 28 memory@0 {
29 name = "memory"; 29 name = "memory";
30 device_type = "memory"; 30 device_type = "memory";
31 reg = <0x0 0x40000000>; /* 1GB */ 31 reg = <0x0 0x40000000>; /* 1GB */
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
index 6ad3b1eb9b86..3c03da6b8b1d 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
@@ -21,7 +21,7 @@
21 model = "Aries/DENX MCV"; 21 model = "Aries/DENX MCV";
22 compatible = "altr,socfpga-cyclone5", "altr,socfpga"; 22 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
23 23
24 memory { 24 memory@0 {
25 name = "memory"; 25 name = "memory";
26 device_type = "memory"; 26 device_type = "memory";
27 reg = <0x0 0x40000000>; /* 1 GiB */ 27 reg = <0x0 0x40000000>; /* 1 GiB */
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
index e5a98e5696ca..21e397287e29 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
@@ -71,7 +71,6 @@
71 71
72 stmpe_touchscreen { 72 stmpe_touchscreen {
73 compatible = "st,stmpe-ts"; 73 compatible = "st,stmpe-ts";
74 reg = <0>;
75 ts,sample-time = <4>; 74 ts,sample-time = <4>;
76 ts,mod-12b = <1>; 75 ts,mod-12b = <1>;
77 ts,ref-sel = <0>; 76 ts,ref-sel = <0>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 7ea32c81e720..155829f9eba1 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -26,7 +26,7 @@
26 stdout-path = "serial0:115200n8"; 26 stdout-path = "serial0:115200n8";
27 }; 27 };
28 28
29 memory { 29 memory@0 {
30 name = "memory"; 30 name = "memory";
31 device_type = "memory"; 31 device_type = "memory";
32 reg = <0x0 0x40000000>; /* 1GB */ 32 reg = <0x0 0x40000000>; /* 1GB */
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index a0c90b3bdfd1..a4a555c19d94 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -26,7 +26,7 @@
26 stdout-path = "serial0:115200n8"; 26 stdout-path = "serial0:115200n8";
27 }; 27 };
28 28
29 memory { 29 memory@0 {
30 name = "memory"; 30 name = "memory";
31 device_type = "memory"; 31 device_type = "memory";
32 reg = <0x0 0x40000000>; /* 1GB */ 32 reg = <0x0 0x40000000>; /* 1GB */
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
index c3d52f27b21e..53bf99eef66d 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
@@ -25,7 +25,7 @@
25 bootargs = "console=ttyS0,115200"; 25 bootargs = "console=ttyS0,115200";
26 }; 26 };
27 27
28 memory { 28 memory@0 {
29 name = "memory"; 29 name = "memory";
30 device_type = "memory"; 30 device_type = "memory";
31 reg = <0x0 0x40000000>; /* 1GB */ 31 reg = <0x0 0x40000000>; /* 1GB */
@@ -60,18 +60,18 @@
60&leds { 60&leds {
61 compatible = "gpio-leds"; 61 compatible = "gpio-leds";
62 62
63 led@0 { 63 led0 {
64 label = "led:green:heartbeat"; 64 label = "led:green:heartbeat";
65 gpios = <&porta 28 1>; 65 gpios = <&porta 28 1>;
66 linux,default-trigger = "heartbeat"; 66 linux,default-trigger = "heartbeat";
67 }; 67 };
68 68
69 led@1 { 69 led1 {
70 label = "led:green:D7"; 70 label = "led:green:D7";
71 gpios = <&portb 19 1>; 71 gpios = <&portb 19 1>;
72 }; 72 };
73 73
74 led@2 { 74 led2 {
75 label = "led:green:D8"; 75 label = "led:green:D8";
76 gpios = <&portb 25 1>; 76 gpios = <&portb 25 1>;
77 }; 77 };
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
index 5b7e3c27e6e9..8860dd2e242c 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
@@ -28,7 +28,7 @@
28 stdout-path = "serial0:115200n8"; 28 stdout-path = "serial0:115200n8";
29 }; 29 };
30 30
31 memory { 31 memory@0 {
32 name = "memory"; 32 name = "memory";
33 device_type = "memory"; 33 device_type = "memory";
34 reg = <0x0 0x40000000>; 34 reg = <0x0 0x40000000>;
@@ -121,3 +121,24 @@
121&usb1 { 121&usb1 {
122 status = "okay"; 122 status = "okay";
123}; 123};
124
125&qspi {
126 status = "okay";
127
128 flash0: n25q512a@0 {
129 #address-cells = <1>;
130 #size-cells = <1>;
131 compatible = "n25q512a";
132 reg = <0>;
133 spi-max-frequency = <100000000>;
134
135 m25p,fast-read;
136 cdns,page-size = <256>;
137 cdns,block-size = <16>;
138 cdns,read-delay = <4>;
139 cdns,tshsl-ns = <50>;
140 cdns,tsd2d-ns = <50>;
141 cdns,tchsh-ns = <4>;
142 cdns,tslch-ns = <4>;
143 };
144};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
index 363ee62457fe..893198049397 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
@@ -57,7 +57,7 @@
57 bootargs = "console=ttyS0,115200"; 57 bootargs = "console=ttyS0,115200";
58 }; 58 };
59 59
60 memory { 60 memory@0 {
61 name = "memory"; 61 name = "memory";
62 device_type = "memory"; 62 device_type = "memory";
63 reg = <0x0 0x40000000>; /* 1GB */ 63 reg = <0x0 0x40000000>; /* 1GB */
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index f9345e02ca49..dfe2193cd4d5 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -26,7 +26,7 @@
26 bootargs = "console=ttyS0,57600"; 26 bootargs = "console=ttyS0,57600";
27 }; 27 };
28 28
29 memory { 29 memory@0 {
30 name = "memory"; 30 name = "memory";
31 device_type = "memory"; 31 device_type = "memory";
32 reg = <0x0 0x40000000>; /* 1 GB */ 32 reg = <0x0 0x40000000>; /* 1 GB */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-30 23:17:26 -0400