2 files changed, 17 insertions, 9 deletions

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 9cdae10fd36d..0573eab0e190 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -380,14 +380,16 @@ static void mixer_cfg_scan(struct mixer_context *ctx, int width, int height)
         mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_SCAN_MASK);
 }
 
-static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height)
+static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, struct drm_display_mode *mode)
 {
+        enum hdmi_quantization_range range = drm_default_rgb_quant_range(mode);
         u32 val;
 
-        if (height < 720) {
-                val = MXR_CFG_RGB601_0_255;
+        if (mode->vdisplay < 720) {
+                val = MXR_CFG_RGB601;
         } else {
-                val = MXR_CFG_RGB709_16_235;
+                val = MXR_CFG_RGB709;
+
                 /* Configure the BT.709 CSC matrix for full range RGB. */
                 mixer_reg_write(ctx, MXR_CM_COEFF_Y,
                         MXR_CSC_CT( 0.184,  0.614,  0.063) |
@@ -398,6 +400,11 @@ static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height)
                         MXR_CSC_CT( 0.440, -0.399, -0.040));
         }
 
+        if (range == HDMI_QUANTIZATION_RANGE_FULL)
+                val |= MXR_CFG_QUANT_RANGE_FULL;
+        else
+                val |= MXR_CFG_QUANT_RANGE_LIMITED;
+
         mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
 }
 
@@ -454,7 +461,7 @@ static void mixer_commit(struct mixer_context *ctx)
         struct drm_display_mode *mode = &ctx->crtc->base.state->adjusted_mode;
 
         mixer_cfg_scan(ctx, mode->hdisplay, mode->vdisplay);
-        mixer_cfg_rgb_fmt(ctx, mode->vdisplay);
+        mixer_cfg_rgb_fmt(ctx, mode);
         mixer_run(ctx);
 }
 
diff --git a/drivers/gpu/drm/exynos/regs-mixer.h b/drivers/gpu/drm/exynos/regs-mixer.h
index d2b8194a07bf..5ff095b0c1b3 100644
--- a/drivers/gpu/drm/exynos/regs-mixer.h
+++ b/drivers/gpu/drm/exynos/regs-mixer.h
@@ -85,10 +85,11 @@
 /* bits for MXR_CFG */
 #define MXR_CFG_LAYER_UPDATE            (1 << 31)
 #define MXR_CFG_LAYER_UPDATE_COUNT_MASK (3 << 29)
-#define MXR_CFG_RGB601_0_255            (0 << 9)
-#define MXR_CFG_RGB601_16_235           (1 << 9)
-#define MXR_CFG_RGB709_0_255            (2 << 9)
-#define MXR_CFG_RGB709_16_235           (3 << 9)
+#define MXR_CFG_QUANT_RANGE_FULL        (0 << 9)
+#define MXR_CFG_QUANT_RANGE_LIMITED     (1 << 9)
+#define MXR_CFG_RGB601                  (0 << 10)
+#define MXR_CFG_RGB709                  (1 << 10)
+
 #define MXR_CFG_RGB_FMT_MASK            0x600
 #define MXR_CFG_OUT_YUV444              (0 << 8)
 #define MXR_CFG_OUT_RGB888              (1 << 8)