2 files changed, 46 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index 4b6062b631b1..23ea381d363f 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -91,6 +91,11 @@
         };
 };
 
+/* Table Table 5-79 of the TRM shows 480ab000 is reserved */
+&usb_otg_hs {
+        status = "disabled";
+};
+
 &iva {
         status = "disabled";
 };
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 69df3620eca5..1c73694c871a 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -109,6 +109,45 @@ void omap5_erratum_workaround_801819(void)
 static inline void omap5_erratum_workaround_801819(void) { }
 #endif
 
+#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
+/*
+ * Configure ACR and enable ACTLR[0] (Enable invalidates of BTB with
+ * ICIALLU) to activate the workaround for secondary Core.
+ * NOTE: it is assumed that the primary core's configuration is done
+ * by the boot loader (kernel will detect a misconfiguration and complain
+ * if this is not done).
+ *
+ * In General Purpose(GP) devices, ACR bit settings can only be done
+ * by ROM code in "secure world" using the smc call and there is no
+ * option to update the "firmware" on such devices. This also works for
+ * High security(HS) devices, as a backup option in case the
+ * "update" is not done in the "security firmware".
+ */
+static void omap5_secondary_harden_predictor(void)
+{
+        u32 acr, acr_mask;
+
+        asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
+
+        /*
+         * ACTLR[0] (Enable invalidates of BTB with ICIALLU)
+         */
+        acr_mask = BIT(0);
+
+        /* Do we already have it done.. if yes, skip expensive smc */
+        if ((acr & acr_mask) == acr_mask)
+                return;
+
+        acr |= acr_mask;
+        omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
+
+        pr_debug("%s: ARM ACR setup for CVE_2017_5715 applied on CPU%d\n",
+                 __func__, smp_processor_id());
+}
+#else
+static inline void omap5_secondary_harden_predictor(void) { }
+#endif
+
 static void omap4_secondary_init(unsigned int cpu)
 {
         /*
@@ -131,6 +170,8 @@ static void omap4_secondary_init(unsigned int cpu)
                 set_cntfreq();
                 /* Configure ACR to disable streaming WA for 801819 */
                 omap5_erratum_workaround_801819();
+                /* Enable ACR to allow for ICUALLU workaround */
+                omap5_secondary_harden_predictor();
         }
 
         /*