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-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7794.c1117
1 files changed, 529 insertions, 588 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
index c7803d67da0b..7e3ece7e97df 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
@@ -105,235 +105,279 @@ enum {
105 FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 105 FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
106 106
107 /* IPSR1 */ 107 /* IPSR1 */
108 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, FN_D7, FN_IRQ3, FN_TCLK1, 108 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D,
109 FN_PWM6_B, FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, FN_D9, FN_HSCIF2_HTX, 109 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
110 FN_I2C1_SDA_B, FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, 110 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B,
111 FN_PWM5_C, FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D, 111 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B,
112 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, FN_D13, 112 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
113 FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, FN_D14, FN_SCIFA1_RXD, 113 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
114 FN_I2C5_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, FN_A0, 114 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
115 FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD, FN_A3, FN_SCIFB0_SCK, 115 FN_D13, FN_SCIFA1_SCK, FN_PWM2_C, FN_TCLK2_B,
116 FN_A4, FN_SCIFB0_TXD, FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C, 116 FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B,
117 FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B,
118 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B,
119 FN_A1, FN_SCIFB1_TXD,
120 FN_A3, FN_SCIFB0_SCK,
121 FN_A4, FN_SCIFB0_TXD,
122 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
117 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, 123 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
118 124
119 /* IPSR2 */ 125 /* IPSR2 */
120 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, FN_A8, FN_MSIOF1_RXD, 126 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B,
121 FN_SCIFA0_RXD_B, FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, FN_A10, 127 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B,
122 FN_MSIOF1_SCK, FN_IIC0_SCL_B, FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 128 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B,
123 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, FN_A13, FN_MSIOF1_SS2, 129 FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B,
124 FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N, 130 FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B,
125 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, FN_A16, 131 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B,
126 FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_VSP, FN_CAN_CLK_C, 132 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B,
127 FN_TPUTO2_B, FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, 133 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
128 FN_AVB_AVTP_CAPTURE_B, FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, 134 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
129 FN_CAN1_TX_B, FN_AVB_AVTP_MATCH_B, FN_A19, FN_MSIOF2_SS2, FN_PWM4, 135 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C,
130 FN_TPUTO2, FN_MOUT0, FN_A20, FN_SPCLK, FN_MOUT1, 136 FN_TPUTO2_B,
137 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
138 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
139 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
140 FN_A20, FN_SPCLK,
131 141
132 /* IPSR3 */ 142 /* IPSR3 */
133 FN_A21, FN_MOSI_IO0, FN_MOUT2, FN_A22, FN_MISO_IO1, FN_MOUT5, 143 FN_A21, FN_MOSI_IO0,
134 FN_ATADIR1_N, FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, FN_A24, FN_IO3, 144 FN_A22, FN_MISO_IO1, FN_ATADIR1_N,
135 FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N, FN_CS0_N, FN_VI1_DATA8, 145 FN_A23, FN_IO2, FN_ATAWR1_N,
136 FN_CS1_N_A26, FN_VI1_DATA9, FN_EX_CS0_N, FN_VI1_DATA10, FN_EX_CS1_N, 146 FN_A24, FN_IO3, FN_EX_WAIT2,
137 FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, FN_EX_CS2_N, FN_PWM0, 147 FN_A25, FN_SSL, FN_ATARD1_N,
138 FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, 148 FN_CS0_N, FN_VI1_DATA8,
139 FN_SDATA_B, FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, 149 FN_CS1_N_A26, FN_VI1_DATA9,
140 FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, FN_EX_CS4_N, 150 FN_EX_CS0_N, FN_VI1_DATA10,
141 FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_RIF0_D0, FN_FMCLK, 151 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
142 FN_SCIFB2_CTS_N, FN_SCKZ_B, FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, 152 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3,
143 FN_TS_SPSYNC_B, FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B, 153 FN_SCIFB2_TXD,
144 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, FN_MTS_N_B, 154 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK,
145 FN_RD_N, FN_ATACS11_N, FN_RD_WR_N, FN_ATAG1_N, 155 FN_SCIFB2_SCK,
156 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK,
157 FN_SCIFB2_CTS_N,
158 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN,
159 FN_SCIFB2_RTS_N,
160 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
161 FN_RD_N, FN_ATACS11_N,
162 FN_RD_WR_N, FN_ATAG1_N,
146 163
147 /* IPSR4 */ 164 /* IPSR4 */
148 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, FN_DU0_DR0, 165 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK,
149 FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, FN_CC50_STATE0, 166 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
150 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, FN_CC50_STATE1, 167 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
151 FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, FN_DU0_DR3, FN_LCDOUT19, 168 FN_DU0_DR2, FN_LCDOUT18,
152 FN_CC50_STATE3, FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, FN_DU0_DR5, 169 FN_DU0_DR3, FN_LCDOUT19,
153 FN_LCDOUT21, FN_CC50_STATE5, FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, 170 FN_DU0_DR4, FN_LCDOUT20,
154 FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, FN_DU0_DG0, FN_LCDOUT8, 171 FN_DU0_DR5, FN_LCDOUT21,
155 FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, FN_CC50_STATE8, FN_DU0_DG1, FN_LCDOUT9, 172 FN_DU0_DR6, FN_LCDOUT22,
156 FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, FN_CC50_STATE9, FN_DU0_DG2, FN_LCDOUT10, 173 FN_DU0_DR7, FN_LCDOUT23,
157 FN_CC50_STATE10, FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, FN_DU0_DG4, 174 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
158 FN_LCDOUT12, FN_CC50_STATE12, 175 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
176 FN_DU0_DG2, FN_LCDOUT10,
177 FN_DU0_DG3, FN_LCDOUT11,
178 FN_DU0_DG4, FN_LCDOUT12,
159 179
160 /* IPSR5 */ 180 /* IPSR5 */
161 FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, FN_DU0_DG6, FN_LCDOUT14, 181 FN_DU0_DG5, FN_LCDOUT13,
162 FN_CC50_STATE14, FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, FN_DU0_DB0, 182 FN_DU0_DG6, FN_LCDOUT14,
163 FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C, 183 FN_DU0_DG7, FN_LCDOUT15,
164 FN_CC50_STATE16, FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, 184 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
165 FN_CAN0_TX_C, FN_CC50_STATE17, FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, 185 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C,
166 FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, FN_DU0_DB4, FN_LCDOUT4, 186 FN_DU0_DB2, FN_LCDOUT2,
167 FN_CC50_STATE20, FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, FN_DU0_DB6, 187 FN_DU0_DB3, FN_LCDOUT3,
168 FN_LCDOUT6, FN_CC50_STATE22, FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, 188 FN_DU0_DB4, FN_LCDOUT4,
169 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, FN_DU0_DOTCLKOUT0, 189 FN_DU0_DB5, FN_LCDOUT5,
170 FN_QCLK, FN_CC50_STATE25, FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 190 FN_DU0_DB6, FN_LCDOUT6,
171 FN_CC50_STATE26, FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, 191 FN_DU0_DB7, FN_LCDOUT7,
192 FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
193 FN_DU0_DOTCLKOUT0, FN_QCLK,
194 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
195 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
172 196
173 /* IPSR6 */ 197 /* IPSR6 */
174 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 198 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
175 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, 199 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
176 FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB, 200 FN_DU0_DISP, FN_QPOLA,
177 FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0, 201 FN_DU0_CDE, FN_QPOLB,
178 FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2, 202 FN_VI0_CLK, FN_AVB_RX_CLK,
179 FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4, 203 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
180 FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6, 204 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
181 FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB, 205 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
182 FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD, 206 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
183 FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N, 207 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
184 FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N, 208 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
185 FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 209 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
210 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
211 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7,
212 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER,
213 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL,
214 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B,
215 FN_AVB_TX_EN,
186 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK, 216 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK,
187 FN_ADIDATA, FN_AD_DI, 217 FN_ADIDATA,
188 218
189 /* IPSR7 */ 219 /* IPSR7 */
190 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0, 220 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0,
191 FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, 221 FN_ADICS_SAMP,
192 FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3, 222 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1,
193 FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 223 FN_ADICLK,
224 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2,
225 FN_ADICHS0,
194 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3, 226 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
195 FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, 227 FN_ADICHS1,
196 FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, 228 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4,
197 FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, 229 FN_ADICHS2,
198 FN_IIC0_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0, 230 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B,
199 FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B, 231 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6,
232 FN_SSI_WS5_B,
233 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7,
234 FN_SSI_SDATA5_B,
200 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B, 235 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
201 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK, 236 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
202 FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD, 237 FN_SSI_WS6_B,
238 FN_DREQ0_N, FN_SCIFB1_RXD,
203 239
204 /* IPSR8 */ 240 /* IPSR8 */
205 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC, 241 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
206 FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, 242 FN_SSI_SDATA6_B,
207 FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX, 243 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, FN_AVB_MDIO,
208 FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B, 244 FN_SSI_SCK78_B,
245 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK,
246 FN_SSI_WS78_B,
209 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, 247 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
210 FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7, 248 FN_AVB_MAGIC, FN_SSI_SDATA7_B,
211 FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 249 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
250 FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
212 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, 251 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
213 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK, 252 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
214 FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, 253 FN_CAN1_RX_D, FN_TPUTO0_B,
215 FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD, 254 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE,
216 FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 255 FN_CAN1_TX_D,
217 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B, 256 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D,
218 FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, 257 FN_TPUTO1_B,
219 FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, 258 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D,
259 FN_BPFCLK_C,
260 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D,
261 FN_FMCLK_C,
220 262
221 /* IPSR9 */ 263 /* IPSR9 */
222 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_RIF1_D1_B, 264 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D,
223 FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, FN_MSIOF0_SCK, FN_IRQ0, 265 FN_FMIN_C,
224 FN_TS_SDATA, FN_DU1_DR4, FN_RIF1_SYNC, FN_TPUTO1_C, FN_MSIOF0_SYNC, 266 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C,
225 FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_RIF1_CLK, FN_BPFCLK_B, FN_MSIOF0_SS1, 267 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B,
226 FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_RIF1_D0, FN_FMCLK_B, 268 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B,
227 FN_RDS_CLK_B, FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, 269 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B,
228 FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, FN_HSCIF1_HRX, FN_I2C4_SCL, 270 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
229 FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, 271 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
230 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B, 272 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
231 FN_SPEEDIN_B, FN_VSP_B, FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, 273 FN_SPEEDIN_B,
232 FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, 274 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B,
233 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B, 275 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
234 FN_CAN_STEP0, FN_CC50_STATE33, FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, 276 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B,
235 FN_DU1_DG5, FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34,
236 277
237 /* IPSR10 */ 278 /* IPSR10 */
238 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0, 279 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
239 FN_CC50_STATE35, FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B, 280 FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
240 FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC0_SCL, 281 FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
241 FN_DU1_DB0, FN_SSI_SDATA2_B, FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, 282 FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
242 FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, 283 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
243 FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, FN_SCIF2_SCK, FN_IRQ1, 284 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B,
244 FN_DU1_DB2, FN_SSI_WS9_B, FN_USB0_IDIN, FN_CAN_DEBUGOUT4,
245 FN_CC50_STATE39, FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
246 FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
247 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C, 285 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
248 FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, FN_SCIF3_TXD, 286 FN_SSI_SCK4_B,
249 FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 287 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C,
250 FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, 288 FN_SSI_WS4_B,
251 FN_AUDIO_CLKC_C, FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, FN_I2C2_SDA, 289 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
252 FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, FN_CAN_DEBUGOUT9, 290 FN_SSI_SDATA4_B,
253 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10, 291 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
292 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN,
254 293
255 /* IPSR11 */ 294 /* IPSR11 */
256 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, 295 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
257 FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, 296 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
258 FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B, 297 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
259 FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6, 298 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
260 FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC, 299 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
261 FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, 300 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
262 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78, 301 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
263 FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP, FN_SSI_WS78, 302 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
264 FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7, 303 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
265 FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
266 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, 304 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
267 FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, 305 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
268 FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, 306 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
269 FN_ADICLK_B, FN_AD_CLK_B,
270 307
271 /* IPSR12 */ 308 /* IPSR12 */
272 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, 309 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
273 FN_AD_NCS_N_B, FN_DREQ1_N_B, FN_SSI_WS34, FN_MSIOF1_SS1_B, 310 FN_DREQ1_N_B,
274 FN_SCIFA1_RXD_C, FN_ADICHS1_B, FN_CAN1_RX_C, FN_DACK1_B, FN_SSI_SDATA3, 311 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
275 FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, FN_CAN1_TX_C, 312 FN_CAN1_RX_C, FN_DACK1_B,
276 FN_DREQ2_N, FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, FN_SSI_WS4, 313 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
277 FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, FN_SSI_SDATA4, FN_MLB_DAT, 314 FN_CAN1_TX_C, FN_DREQ2_N,
278 FN_IERX_B, FN_IRD_SCK, FN_SSI_SDATA8, FN_SCIF1_SCK_B, 315 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B,
279 FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1, 316 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B,
280 FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D, 317 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON,
281 FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B, 318 FN_DACK2, FN_ETH_MDIO_B,
282 FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, 319 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
283 FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1, 320 FN_ETH_CRS_DV_B,
284 FN_ATAWR0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 321 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D,
285 FN_MDATA, FN_ATAG0_N, FN_ETH_RXD1_B, 322 FN_ETH_RX_ER_B,
323 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_ATAWR0_N,
324 FN_ETH_RXD0_B,
325 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_ATAG0_N, FN_ETH_RXD1_B,
286 326
287 /* IPSR13 */ 327 /* IPSR13 */
288 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ, 328 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
289 FN_ATACS00_N, FN_ETH_LINK_B, FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, 329 FN_ATACS00_N, FN_ETH_LINK_B,
290 FN_SCIFA0_TXD_D, FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, 330 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4,
291 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_MTS_N, 331 FN_ATACS10_N, FN_ETH_REFCLK_B,
292 FN_EX_WAIT1, FN_ETH_TXD1_B, FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, 332 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_EX_WAIT1,
293 FN_VI1_DATA6, FN_ATARD0_N, FN_ETH_TX_EN_B, FN_SSI_SDATA9, 333 FN_ETH_TXD1_B,
294 FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N, 334 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N,
295 FN_ETH_MAGIC_B, FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, 335 FN_ETH_TX_EN_B,
296 FN_VI1_CLKENB, FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, 336 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
337 FN_ATADIR0_N, FN_ETH_MAGIC_B,
338 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
339 FN_TS_SDATA_C, FN_ETH_TXD0_B,
297 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, 340 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
298 FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, FN_AUDIO_CLKC, 341 FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B,
299 FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, FN_TS_SDEN_C, 342 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
300 FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, 343 FN_TS_SDEN_C, FN_FMCLK_E,
301 FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, FN_TS_SPSYNC_C, FN_RIF0_D1_B, 344 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
302 FN_FMIN_E, FN_RDS_DATA_D, 345 FN_TS_SPSYNC_C, FN_FMIN_E,
303 346
304 /* MOD_SEL */ 347 /* MOD_SEL */
305 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, 348 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
306 FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1, 349 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
307 FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1, 350 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
308 FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0, 351 FN_SEL_DARC_4,
309 FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1, 352 FN_SEL_ETH_0, FN_SEL_ETH_1,
310 FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0, 353 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
311 FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, 354 FN_SEL_I2C00_4,
312 FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1, 355 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
313 FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0, 356 FN_SEL_I2C01_4,
314 FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4, 357 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
358 FN_SEL_I2C02_4,
315 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, 359 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
316 FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, 360 FN_SEL_I2C03_4,
317 FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_I2C05_0, FN_SEL_I2C05_1, 361 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
318 FN_SEL_I2C05_2, FN_SEL_I2C05_3, FN_SEL_AVB_0, FN_SEL_AVB_1, 362 FN_SEL_I2C04_4,
363 FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
319 364
320 /* MOD_SEL2 */ 365 /* MOD_SEL2 */
321 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC0_0, 366 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
322 FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3, FN_SEL_LBS_0, 367 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
323 FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0, 368 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1,
324 FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0, 369 FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1,
325 FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0, 370 FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1,
326 FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0, 371 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3,
327 FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, 372 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
328 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, 373 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
329 FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, 374 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3,
330 FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1, 375 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3,
331 FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, 376 FN_SEL_TMU_0, FN_SEL_TMU_1,
332 FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1, 377 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
333 FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1, 378 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
334 FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, 379 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
335 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1, 380 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
336 FN_SEL_RDS_2, FN_SEL_RDS_3,
337 381
338 /* MOD_SEL3 */ 382 /* MOD_SEL3 */
339 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 383 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
@@ -372,117 +416,141 @@ enum {
372 SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK, 416 SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
373 417
374 /* IPSR1 */ 418 /* IPSR1 */
375 D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK, D7_MARK, IRQ3_MARK, 419 D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK,
376 TCLK1_MARK, PWM6_B_MARK, D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK, 420 D7_MARK, IRQ3_MARK, TCLK1_MARK, PWM6_B_MARK,
377 D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK, D10_MARK, 421 D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
378 HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK, 422 D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK,
423 D10_MARK, HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
379 D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK, 424 D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
380 D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK, 425 D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
381 D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK, PWM2_C_MARK, TCLK2_B_MARK, 426 D13_MARK, SCIFA1_SCK_MARK, PWM2_C_MARK, TCLK2_B_MARK,
382 D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK, 427 D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK,
383 I2C5_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK, 428 D15_MARK, SCIFA1_TXD_MARK, I2C5_SDA_B_MARK,
384 SCIFB1_TXD_MARK, A3_MARK, SCIFB0_SCK_MARK, A4_MARK, SCIFB0_TXD_MARK, 429 A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK,
385 A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, A6_MARK, 430 A1_MARK, SCIFB1_TXD_MARK,
386 SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK, 431 A3_MARK, SCIFB0_SCK_MARK,
432 A4_MARK, SCIFB0_TXD_MARK,
433 A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK,
434 A6_MARK, SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
387 435
388 /* IPSR2 */ 436 /* IPSR2 */
389 A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, A8_MARK, MSIOF1_RXD_MARK, 437 A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK,
390 SCIFA0_RXD_B_MARK, A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK, 438 A8_MARK, MSIOF1_RXD_MARK, SCIFA0_RXD_B_MARK,
391 A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK, A11_MARK, MSIOF1_SYNC_MARK, 439 A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
392 IIC0_SDA_B_MARK, A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK, 440 A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK,
393 A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK, 441 A11_MARK, MSIOF1_SYNC_MARK, IIC0_SDA_B_MARK,
394 HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK, 442 A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
395 HSCIF0_HTX_B_MARK, DACK1_MARK, A16_MARK, MSIOF2_SCK_MARK, 443 A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK,
396 HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, VSP_MARK, CAN_CLK_C_MARK, 444 A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK,
397 TPUTO2_B_MARK, A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, 445 A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK,
398 CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_B_MARK, A18_MARK, MSIOF2_SS1_MARK, 446 A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK,
399 SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, AVB_AVTP_MATCH_B_MARK, A19_MARK, 447 CAN_CLK_C_MARK, TPUTO2_B_MARK,
400 MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, MOUT0_MARK, A20_MARK, 448 A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK,
401 SPCLK_MARK, MOUT1_MARK, 449 A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK,
450 A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK,
451 A20_MARK, SPCLK_MARK,
402 452
403 /* IPSR3 */ 453 /* IPSR3 */
404 A21_MARK, MOSI_IO0_MARK, MOUT2_MARK, A22_MARK, MISO_IO1_MARK, 454 A21_MARK, MOSI_IO0_MARK,
405 MOUT5_MARK, ATADIR1_N_MARK, A23_MARK, IO2_MARK, MOUT6_MARK, 455 A22_MARK, MISO_IO1_MARK, ATADIR1_N_MARK,
406 ATAWR1_N_MARK, A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK, 456 A23_MARK, IO2_MARK, ATAWR1_N_MARK,
407 ATARD1_N_MARK, CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK, 457 A24_MARK, IO3_MARK, EX_WAIT2_MARK,
408 VI1_DATA9_MARK, EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK, 458 A25_MARK, SSL_MARK, ATARD1_N_MARK,
409 TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, EX_CS2_N_MARK, 459 CS0_N_MARK, VI1_DATA8_MARK,
410 PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, RIF0_SYNC_MARK, 460 CS1_N_A26_MARK, VI1_DATA9_MARK,
411 TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK, EX_CS3_N_MARK, 461 EX_CS0_N_MARK, VI1_DATA10_MARK,
412 SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, RIF0_CLK_MARK, 462 EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK,
413 BPFCLK_MARK, SCIFB2_SCK_MARK, MDATA_B_MARK, EX_CS4_N_MARK, 463 EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK,
414 SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, RIF0_D0_MARK, 464 TPUTO3_MARK, SCIFB2_TXD_MARK,
415 FMCLK_MARK, SCIFB2_CTS_N_MARK, SCKZ_B_MARK, EX_CS5_N_MARK, 465 EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK,
416 SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, RIF0_D1_MARK, 466 BPFCLK_MARK, SCIFB2_SCK_MARK,
417 FMIN_MARK, SCIFB2_RTS_N_MARK, STM_N_B_MARK, BS_N_MARK, DRACK0_MARK, 467 EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK,
418 PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK, RD_N_MARK, 468 FMCLK_MARK, SCIFB2_CTS_N_MARK,
419 ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK, 469 EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK,
470 FMIN_MARK, SCIFB2_RTS_N_MARK,
471 BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK,
472 RD_N_MARK, ATACS11_N_MARK,
473 RD_WR_N_MARK, ATAG1_N_MARK,
420 474
421 /* IPSR4 */ 475 /* IPSR4 */
422 EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, PWMFSW0_MARK, 476 EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK,
423 DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK, 477 DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
424 CC50_STATE0_MARK, DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, 478 DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK,
425 I2C2_SDA_D_MARK, CC50_STATE1_MARK, DU0_DR2_MARK, LCDOUT18_MARK, 479 DU0_DR2_MARK, LCDOUT18_MARK,
426 CC50_STATE2_MARK, DU0_DR3_MARK, LCDOUT19_MARK, CC50_STATE3_MARK, 480 DU0_DR3_MARK, LCDOUT19_MARK,
427 DU0_DR4_MARK, LCDOUT20_MARK, CC50_STATE4_MARK, DU0_DR5_MARK, 481 DU0_DR4_MARK, LCDOUT20_MARK,
428 LCDOUT21_MARK, CC50_STATE5_MARK, DU0_DR6_MARK, LCDOUT22_MARK, 482 DU0_DR5_MARK, LCDOUT21_MARK,
429 CC50_STATE6_MARK, DU0_DR7_MARK, LCDOUT23_MARK, CC50_STATE7_MARK, 483 DU0_DR6_MARK, LCDOUT22_MARK,
484 DU0_DR7_MARK, LCDOUT23_MARK,
430 DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK, 485 DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
431 CC50_STATE8_MARK, DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, 486 DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK,
432 I2C3_SDA_D_MARK, CC50_STATE9_MARK, DU0_DG2_MARK, LCDOUT10_MARK, 487 DU0_DG2_MARK, LCDOUT10_MARK,
433 CC50_STATE10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, CC50_STATE11_MARK, 488 DU0_DG3_MARK, LCDOUT11_MARK,
434 DU0_DG4_MARK, LCDOUT12_MARK, CC50_STATE12_MARK, 489 DU0_DG4_MARK, LCDOUT12_MARK,
435 490
436 /* IPSR5 */ 491 /* IPSR5 */
437 DU0_DG5_MARK, LCDOUT13_MARK, CC50_STATE13_MARK, DU0_DG6_MARK, 492 DU0_DG5_MARK, LCDOUT13_MARK,
438 LCDOUT14_MARK, CC50_STATE14_MARK, DU0_DG7_MARK, LCDOUT15_MARK, 493 DU0_DG6_MARK, LCDOUT14_MARK,
439 CC50_STATE15_MARK, DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, 494 DU0_DG7_MARK, LCDOUT15_MARK,
440 I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK, DU0_DB1_MARK, 495 DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK,
441 LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, CAN0_TX_C_MARK, 496 CAN0_RX_C_MARK,
442 CC50_STATE17_MARK, DU0_DB2_MARK, LCDOUT2_MARK, CC50_STATE18_MARK, 497 DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK,
443 DU0_DB3_MARK, LCDOUT3_MARK, CC50_STATE19_MARK, DU0_DB4_MARK, 498 CAN0_TX_C_MARK,
444 LCDOUT4_MARK, CC50_STATE20_MARK, DU0_DB5_MARK, LCDOUT5_MARK, 499 DU0_DB2_MARK, LCDOUT2_MARK,
445 CC50_STATE21_MARK, DU0_DB6_MARK, LCDOUT6_MARK, CC50_STATE22_MARK, 500 DU0_DB3_MARK, LCDOUT3_MARK,
446 DU0_DB7_MARK, LCDOUT7_MARK, CC50_STATE23_MARK, DU0_DOTCLKIN_MARK, 501 DU0_DB4_MARK, LCDOUT4_MARK,
447 QSTVA_QVS_MARK, CC50_STATE24_MARK, DU0_DOTCLKOUT0_MARK, 502 DU0_DB5_MARK, LCDOUT5_MARK,
448 QCLK_MARK, CC50_STATE25_MARK, DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, 503 DU0_DB6_MARK, LCDOUT6_MARK,
449 CC50_STATE26_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK, 504 DU0_DB7_MARK, LCDOUT7_MARK,
450 CC50_STATE27_MARK, 505 DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
506 DU0_DOTCLKOUT0_MARK, QCLK_MARK,
507 DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
508 DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
451 509
452 /* IPSR6 */ 510 /* IPSR6 */
453 DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK, 511 DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
454 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK, 512 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
455 DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK, 513 DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK,
456 CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, 514 VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK,
457 AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK, 515 VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
458 VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK, 516 VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK,
459 AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK, 517 VI0_DATA3_VI0_B3_MARK, AVB_RXD2_MARK,
460 VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK, 518 VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
461 AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK, 519 VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK,
462 I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK, 520 VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK,
521 VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK,
522 VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK,
523 AVB_RXD7_MARK,
463 VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK, 524 VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
464 AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, 525 AVB_RX_ER_MARK,
465 IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, 526 VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK,
466 I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK, 527 AVB_COL_MARK,
467 VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK, AVB_TX_CLK_MARK, 528 VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK,
468 ADIDATA_MARK, AD_DI_MARK, 529 AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK,
530 ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK,
531 AVB_TX_CLK_MARK, ADIDATA_MARK,
469 532
470 /* IPSR7 */ 533 /* IPSR7 */
471 ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK, 534 ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK,
472 AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK, 535 AVB_TXD0_MARK, ADICS_SAMP_MARK,
473 MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK, 536 ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK,
474 AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, 537 AVB_TXD1_MARK, ADICLK_MARK,
475 CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK, 538 ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK,
539 AVB_TXD2_MARK, ADICHS0_MARK,
476 ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK, 540 ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
477 AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK, 541 AVB_TXD3_MARK, ADICHS1_MARK,
478 MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK, 542 ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK,
543 AVB_TXD4_MARK, ADICHS2_MARK,
479 ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK, 544 ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
480 SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, 545 SSI_SCK5_B_MARK,
481 IIC0_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK, 546 ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK,
482 VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK, AVB_TXD7_MARK, 547 AVB_TXD6_MARK, SSI_WS5_B_MARK,
483 SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, 548 ETH_TX_EN_MARK, VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK,
484 AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK, 549 AVB_TXD7_MARK, SSI_SDATA5_B_MARK,
485 SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK, 550 ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, AVB_TX_ER_MARK,
551 SSI_SCK6_B_MARK,
552 ETH_TXD0_MARK, VI0_R2_MARK, SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK,
553 AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
486 DREQ0_N_MARK, SCIFB1_RXD_MARK, 554 DREQ0_N_MARK, SCIFB1_RXD_MARK,
487 555
488 /* IPSR8 */ 556 /* IPSR8 */
@@ -498,103 +566,107 @@ enum {
498 I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK, 566 I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
499 AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK, 567 AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
500 SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK, 568 SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
501 CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, 569 CAN1_TX_D_MARK,
502 DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK, 570 I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK,
503 I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK, 571 TS_SDATA_D_MARK, TPUTO1_B_MARK,
504 TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK, 572 I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, TS_SCK_D_MARK,
505 I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK, 573 BPFCLK_C_MARK,
506 FMCLK_C_MARK, RDS_CLK_MARK, 574 MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK,
575 TS_SDEN_D_MARK, FMCLK_C_MARK,
507 576
508 /* IPSR9 */ 577 /* IPSR9 */
509 MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK, 578 MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
510 RIF1_D1_B_MARK, TS_SPSYNC_D_MARK, FMIN_C_MARK, RDS_DATA_MARK, 579 TS_SPSYNC_D_MARK, FMIN_C_MARK,
511 MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, RIF1_SYNC_MARK, 580 MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK,
512 TPUTO1_C_MARK, MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, 581 MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK,
513 RIF1_CLK_MARK, BPFCLK_B_MARK, MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, 582 MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK,
514 TS_SDEN_MARK, DU1_DR6_MARK, RIF1_D0_MARK, FMCLK_B_MARK, RDS_CLK_B_MARK, 583 FMCLK_B_MARK,
515 MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK, 584 MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
516 RIF1_D1_MARK, FMIN_B_MARK, RDS_DATA_B_MARK, HSCIF1_HRX_MARK, 585 FMIN_B_MARK,
517 I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, HSCIF1_HTX_MARK, 586 HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK,
518 I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, HSCIF1_HSCK_MARK, 587 HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK,
519 PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, SPEEDIN_B_MARK, 588 HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
520 VSP_B_MARK, HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, 589 SPEEDIN_B_MARK,
521 DU1_DG3_MARK, SSI_SCK1_B_MARK, CAN_DEBUG_HW_TRIGGER_MARK, 590 HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK,
522 CC50_STATE32_MARK, HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, 591 SSI_SCK1_B_MARK,
523 DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK, CC50_STATE33_MARK, 592 HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK,
593 SSI_WS1_B_MARK,
524 SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK, 594 SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
525 CAN_TXCLK_MARK, CC50_STATE34_MARK, 595 CAN_TXCLK_MARK,
526 596
527 /* IPSR10 */ 597 /* IPSR10 */
528 SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK, 598 SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
529 CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, I2C5_SDA_MARK, 599 SCIF1_TXD_MARK, I2C5_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
530 DU1_DG7_MARK, SSI_WS2_B_MARK, CAN_DEBUGOUT1_MARK, CC50_STATE36_MARK,
531 SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK, 600 SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
532 USB0_EXTLP_MARK, CAN_DEBUGOUT2_MARK, CC50_STATE37_MARK, SCIF2_TXD_MARK, 601 SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK,
533 IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK, 602 SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK,
534 CAN_DEBUGOUT3_MARK, CC50_STATE38_MARK, SCIF2_SCK_MARK, IRQ1_MARK, 603 SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK,
535 DU1_DB2_MARK, SSI_WS9_B_MARK, USB0_IDIN_MARK, CAN_DEBUGOUT4_MARK, 604 SSI_SDATA9_B_MARK,
536 CC50_STATE39_MARK, SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, 605 SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK,
537 DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK, CAN_DEBUGOUT5_MARK, 606 AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
538 CC50_OSCOUT_MARK, SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, 607 SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK,
539 DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, CAN_DEBUGOUT6_MARK, 608 AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
540 RDS_CLK_C_MARK, SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, 609 I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK,
541 DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, CAN_DEBUGOUT7_MARK, 610 SSI_SDATA4_B_MARK,
542 RDS_DATA_C_MARK, I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, 611 I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
543 AUDIO_CLKC_C_MARK, SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK, I2C2_SDA_MARK, 612 SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK,
544 SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, CAN_DEBUGOUT9_MARK,
545 SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, CAN_DEBUGOUT10_MARK,
546 613
547 /* IPSR11 */ 614 /* IPSR11 */
548 SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK, 615 SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
549 CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, 616 SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK,
550 DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK, 617 SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
551 SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
552 SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK, 618 SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
553 DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK, 619 DU1_EXVSYNC_DU1_VSYNC_MARK,
554 SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, 620 SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK,
555 CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, 621 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
556 DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, 622 SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, DU1_DISP_MARK,
557 DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, 623 SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK,
558 AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK, 624 SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK,
559 MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK, 625 CAN_CLK_D_MARK,
560 PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, 626 SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK,
561 ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, 627 SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK,
562 PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK, 628 SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK,
563 629
564 /* IPSR12 */ 630 /* IPSR12 */
565 SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK, 631 SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
566 AD_NCS_N_B_MARK, DREQ1_N_B_MARK, SSI_WS34_MARK, MSIOF1_SS1_B_MARK, 632 DREQ1_N_B_MARK,
567 SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, CAN1_RX_C_MARK, DACK1_B_MARK, 633 SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK,
634 CAN1_RX_C_MARK, DACK1_B_MARK,
568 SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK, 635 SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
569 CAN1_TX_C_MARK, DREQ2_N_MARK, SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK, 636 CAN1_TX_C_MARK, DREQ2_N_MARK,
570 IRD_TX_MARK, SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, IRD_RX_MARK, 637 SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
571 SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, IRD_SCK_MARK, 638 SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK,
639 SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK,
572 SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK, 640 SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
573 DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK, 641 DACK2_MARK, ETH_MDIO_B_MARK,
574 IIC0_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK, 642 SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK,
575 ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, 643 CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK,
576 VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK, 644 SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK,
577 SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK, 645 CAN0_TX_D_MARK, ETH_RX_ER_B_MARK,
578 ATAWR0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, 646 SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, ATAWR0_N_MARK,
579 VI1_DATA2_MARK, MDATA_MARK, ATAG0_N_MARK, ETH_RXD1_B_MARK, 647 ETH_RXD0_B_MARK,
648 SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK, ATAG0_N_MARK,
649 ETH_RXD1_B_MARK,
580 650
581 /* IPSR13 */ 651 /* IPSR13 */
582 SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK, 652 SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
583 SCKZ_MARK, ATACS00_N_MARK, ETH_LINK_B_MARK, SSI_SDATA2_MARK, 653 ATACS00_N_MARK, ETH_LINK_B_MARK,
584 HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, VI1_DATA4_MARK, STM_N_MARK, 654 SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK,
585 ATACS10_N_MARK, ETH_REFCLK_B_MARK, SSI_SCK9_MARK, SCIF2_SCK_B_MARK, 655 VI1_DATA4_MARK, ATACS10_N_MARK, ETH_REFCLK_B_MARK,
586 PWM2_B_MARK, VI1_DATA5_MARK, MTS_N_MARK, EX_WAIT1_MARK, 656 SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK,
587 ETH_TXD1_B_MARK, SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, 657 EX_WAIT1_MARK, ETH_TXD1_B_MARK,
588 VI1_DATA6_MARK, ATARD0_N_MARK, ETH_TX_EN_B_MARK, SSI_SDATA9_MARK, 658 SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK,
589 SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, ATADIR0_N_MARK, 659 ATARD0_N_MARK, ETH_TX_EN_B_MARK,
590 ETH_MAGIC_B_MARK, AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, 660 SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK,
591 VI1_CLKENB_MARK, TS_SDATA_C_MARK, RIF0_SYNC_B_MARK, ETH_TXD0_B_MARK, 661 ATADIR0_N_MARK, ETH_MAGIC_B_MARK,
662 AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK,
663 TS_SDATA_C_MARK, ETH_TXD0_B_MARK,
592 AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK, 664 AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
593 TS_SCK_C_MARK, RIF0_CLK_B_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK, 665 TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
594 AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK, 666 AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
595 TS_SDEN_C_MARK, RIF0_D0_B_MARK, FMCLK_E_MARK, RDS_CLK_D_MARK, 667 TS_SDEN_C_MARK, FMCLK_E_MARK,
596 AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK, 668 AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
597 TS_SPSYNC_C_MARK, RIF0_D1_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, 669 TS_SPSYNC_C_MARK, FMIN_E_MARK,
598 PINMUX_MARK_END, 670 PINMUX_MARK_END,
599}; 671};
600 672
@@ -700,7 +772,6 @@ static const u16 pinmux_data[] = {
700 PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3), 772 PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
701 PINMUX_IPSR_GPSR(IP1_17_15, D13), 773 PINMUX_IPSR_GPSR(IP1_17_15, D13),
702 PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0), 774 PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
703 PINMUX_IPSR_GPSR(IP1_17_15, TANS1),
704 PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C), 775 PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
705 PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1), 776 PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
706 PINMUX_IPSR_GPSR(IP1_19_18, D14), 777 PINMUX_IPSR_GPSR(IP1_19_18, D14),
@@ -761,39 +832,31 @@ static const u16 pinmux_data[] = {
761 PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0), 832 PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
762 PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1), 833 PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
763 PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0), 834 PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
764 PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0),
765 PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2), 835 PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
766 PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B), 836 PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
767 PINMUX_IPSR_GPSR(IP2_23_21, A17), 837 PINMUX_IPSR_GPSR(IP2_23_21, A17),
768 PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0), 838 PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
769 PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4), 839 PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
770 PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1), 840 PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
771 PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
772 PINMUX_IPSR_GPSR(IP2_26_24, A18), 841 PINMUX_IPSR_GPSR(IP2_26_24, A18),
773 PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0), 842 PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
774 PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4), 843 PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
775 PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1), 844 PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
776 PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1),
777 PINMUX_IPSR_GPSR(IP2_29_27, A19), 845 PINMUX_IPSR_GPSR(IP2_29_27, A19),
778 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0), 846 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
779 PINMUX_IPSR_GPSR(IP2_29_27, PWM4), 847 PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
780 PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2), 848 PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
781 PINMUX_IPSR_GPSR(IP2_29_27, MOUT0),
782 PINMUX_IPSR_GPSR(IP2_31_30, A20), 849 PINMUX_IPSR_GPSR(IP2_31_30, A20),
783 PINMUX_IPSR_GPSR(IP2_31_30, SPCLK), 850 PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
784 PINMUX_IPSR_GPSR(IP2_29_27, MOUT1),
785 851
786 /* IPSR3 */ 852 /* IPSR3 */
787 PINMUX_IPSR_GPSR(IP3_1_0, A21), 853 PINMUX_IPSR_GPSR(IP3_1_0, A21),
788 PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0), 854 PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
789 PINMUX_IPSR_GPSR(IP3_1_0, MOUT2),
790 PINMUX_IPSR_GPSR(IP3_3_2, A22), 855 PINMUX_IPSR_GPSR(IP3_3_2, A22),
791 PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1), 856 PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
792 PINMUX_IPSR_GPSR(IP3_3_2, MOUT5),
793 PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N), 857 PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
794 PINMUX_IPSR_GPSR(IP3_5_4, A23), 858 PINMUX_IPSR_GPSR(IP3_5_4, A23),
795 PINMUX_IPSR_GPSR(IP3_5_4, IO2), 859 PINMUX_IPSR_GPSR(IP3_5_4, IO2),
796 PINMUX_IPSR_GPSR(IP3_5_4, MOUT6),
797 PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N), 860 PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
798 PINMUX_IPSR_GPSR(IP3_7_6, A24), 861 PINMUX_IPSR_GPSR(IP3_7_6, A24),
799 PINMUX_IPSR_GPSR(IP3_7_6, IO3), 862 PINMUX_IPSR_GPSR(IP3_7_6, IO3),
@@ -815,40 +878,31 @@ static const u16 pinmux_data[] = {
815 PINMUX_IPSR_GPSR(IP3_17_15, PWM0), 878 PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
816 PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2), 879 PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
817 PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), 880 PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
818 PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0),
819 PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3), 881 PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
820 PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD), 882 PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
821 PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1),
822 PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N), 883 PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
823 PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0), 884 PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
824 PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2), 885 PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
825 PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), 886 PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
826 PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0),
827 PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0), 887 PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
828 PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK), 888 PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
829 PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1),
830 PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N), 889 PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
831 PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0), 890 PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
832 PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4), 891 PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
833 PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), 892 PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
834 PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0),
835 PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0), 893 PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
836 PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N), 894 PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
837 PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1),
838 PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N), 895 PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
839 PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0), 896 PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
840 PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4), 897 PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
841 PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), 898 PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
842 PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0),
843 PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0), 899 PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
844 PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N), 900 PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
845 PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1),
846 PINMUX_IPSR_GPSR(IP3_29_27, BS_N), 901 PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
847 PINMUX_IPSR_GPSR(IP3_29_27, DRACK0), 902 PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
848 PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C), 903 PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
849 PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C), 904 PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
850 PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N), 905 PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
851 PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1),
852 PINMUX_IPSR_GPSR(IP3_30, RD_N), 906 PINMUX_IPSR_GPSR(IP3_30, RD_N),
853 PINMUX_IPSR_GPSR(IP3_30, ATACS11_N), 907 PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
854 PINMUX_IPSR_GPSR(IP3_31, RD_WR_N), 908 PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
@@ -858,121 +912,88 @@ static const u16 pinmux_data[] = {
858 PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0), 912 PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
859 PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1), 913 PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
860 PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0), 914 PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
861 PINMUX_IPSR_GPSR(IP4_1_0, PWMFSW0),
862 PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0), 915 PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
863 PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16), 916 PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
864 PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2), 917 PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
865 PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3), 918 PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
866 PINMUX_IPSR_GPSR(IP4_4_2, CC50_STATE0),
867 PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1), 919 PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
868 PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17), 920 PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
869 PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2), 921 PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
870 PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3), 922 PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
871 PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE1),
872 PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2), 923 PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
873 PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18), 924 PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
874 PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE2),
875 PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3), 925 PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
876 PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19), 926 PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
877 PINMUX_IPSR_GPSR(IP4_11_10, CC50_STATE3),
878 PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4), 927 PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
879 PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20), 928 PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
880 PINMUX_IPSR_GPSR(IP4_13_12, CC50_STATE4),
881 PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5), 929 PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
882 PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21), 930 PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
883 PINMUX_IPSR_GPSR(IP4_15_14, CC50_STATE5),
884 PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6), 931 PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
885 PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22), 932 PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
886 PINMUX_IPSR_GPSR(IP4_17_16, CC50_STATE6),
887 PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7), 933 PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
888 PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23), 934 PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
889 PINMUX_IPSR_GPSR(IP4_19_18, CC50_STATE7),
890 PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0), 935 PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
891 PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8), 936 PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
892 PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2), 937 PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
893 PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3), 938 PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
894 PINMUX_IPSR_GPSR(IP4_22_20, CC50_STATE8),
895 PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1), 939 PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
896 PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9), 940 PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
897 PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2), 941 PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
898 PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3), 942 PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
899 PINMUX_IPSR_GPSR(IP4_25_23, CC50_STATE9),
900 PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2), 943 PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
901 PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10), 944 PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
902 PINMUX_IPSR_GPSR(IP4_27_26, CC50_STATE10),
903 PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3), 945 PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
904 PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11), 946 PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
905 PINMUX_IPSR_GPSR(IP4_29_28, CC50_STATE11),
906 PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4), 947 PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
907 PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12), 948 PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
908 PINMUX_IPSR_GPSR(IP4_31_30, CC50_STATE12),
909 949
910 /* IPSR5 */ 950 /* IPSR5 */
911 PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5), 951 PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
912 PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13), 952 PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
913 PINMUX_IPSR_GPSR(IP5_1_0, CC50_STATE13),
914 PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6), 953 PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
915 PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14), 954 PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
916 PINMUX_IPSR_GPSR(IP5_3_2, CC50_STATE14),
917 PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7), 955 PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
918 PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15), 956 PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
919 PINMUX_IPSR_GPSR(IP5_5_4, CC50_STATE15),
920 PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0), 957 PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
921 PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0), 958 PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
922 PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2), 959 PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
923 PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3), 960 PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
924 PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2), 961 PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
925 PINMUX_IPSR_GPSR(IP5_8_6, CC50_STATE16),
926 PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1), 962 PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
927 PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1), 963 PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
928 PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), 964 PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
929 PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3), 965 PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
930 PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2), 966 PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
931 PINMUX_IPSR_GPSR(IP5_11_9, CC50_STATE17),
932 PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2), 967 PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
933 PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2), 968 PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
934 PINMUX_IPSR_GPSR(IP5_13_12, CC50_STATE18),
935 PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3), 969 PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
936 PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3), 970 PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
937 PINMUX_IPSR_GPSR(IP5_15_14, CC50_STATE19),
938 PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4), 971 PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
939 PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4), 972 PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
940 PINMUX_IPSR_GPSR(IP5_17_16, CC50_STATE20),
941 PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5), 973 PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
942 PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5), 974 PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
943 PINMUX_IPSR_GPSR(IP5_19_18, CC50_STATE21),
944 PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6), 975 PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
945 PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6), 976 PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
946 PINMUX_IPSR_GPSR(IP5_21_20, CC50_STATE22),
947 PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7), 977 PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
948 PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7), 978 PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
949 PINMUX_IPSR_GPSR(IP5_23_22, CC50_STATE23),
950 PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN), 979 PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
951 PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS), 980 PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
952 PINMUX_IPSR_GPSR(IP5_25_24, CC50_STATE24),
953 PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0), 981 PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
954 PINMUX_IPSR_GPSR(IP5_27_26, QCLK), 982 PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
955 PINMUX_IPSR_GPSR(IP5_27_26, CC50_STATE25),
956 PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1), 983 PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
957 PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE), 984 PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
958 PINMUX_IPSR_GPSR(IP5_29_28, CC50_STATE26),
959 PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC), 985 PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
960 PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS), 986 PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
961 PINMUX_IPSR_GPSR(IP5_31_30, CC50_STATE27),
962 987
963 /* IPSR6 */ 988 /* IPSR6 */
964 PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC), 989 PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
965 PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE), 990 PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
966 PINMUX_IPSR_GPSR(IP6_1_0, CC50_STATE28),
967 PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE), 991 PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
968 PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE), 992 PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
969 PINMUX_IPSR_GPSR(IP6_3_2, CC50_STATE29),
970 PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP), 993 PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
971 PINMUX_IPSR_GPSR(IP6_5_4, QPOLA), 994 PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
972 PINMUX_IPSR_GPSR(IP6_5_4, CC50_STATE30),
973 PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE), 995 PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
974 PINMUX_IPSR_GPSR(IP6_7_6, QPOLB), 996 PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
975 PINMUX_IPSR_GPSR(IP6_7_6, CC50_STATE31),
976 PINMUX_IPSR_GPSR(IP6_8, VI0_CLK), 997 PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
977 PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK), 998 PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
978 PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0), 999 PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
@@ -1017,7 +1038,6 @@ static const u16 pinmux_data[] = {
1017 PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3), 1038 PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3),
1018 PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK), 1039 PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
1019 PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0), 1040 PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
1020 PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0),
1021 1041
1022 /* IPSR7 */ 1042 /* IPSR7 */
1023 PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), 1043 PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
@@ -1026,21 +1046,18 @@ static const u16 pinmux_data[] = {
1026 PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3), 1046 PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3),
1027 PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0), 1047 PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
1028 PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0), 1048 PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
1029 PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0),
1030 PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0), 1049 PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
1031 PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2), 1050 PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
1032 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), 1051 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
1033 PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), 1052 PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
1034 PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1), 1053 PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
1035 PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0), 1054 PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
1036 PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0),
1037 PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0), 1055 PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
1038 PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3), 1056 PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
1039 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), 1057 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
1040 PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), 1058 PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
1041 PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2), 1059 PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
1042 PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0), 1060 PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
1043 PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0),
1044 PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0), 1061 PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
1045 PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4), 1062 PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
1046 PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), 1063 PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
@@ -1136,60 +1153,48 @@ static const u16 pinmux_data[] = {
1136 PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), 1153 PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
1137 PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B), 1154 PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
1138 PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0), 1155 PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
1139 PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
1140 PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), 1156 PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
1141 PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B), 1157 PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
1142 PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0), 1158 PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
1143 PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), 1159 PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
1144 PINMUX_IPSR_GPSR(IP8_28_26, IRQ5), 1160 PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
1145 PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1), 1161 PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
1146 PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
1147 PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), 1162 PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
1148 PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2), 1163 PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
1149 PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD), 1164 PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
1150 PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), 1165 PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
1151 PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), 1166 PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
1152 PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2), 1167 PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
1153 PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
1154 PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), 1168 PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
1155 PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2), 1169 PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
1156 PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0),
1157 1170
1158 /* IPSR9 */ 1171 /* IPSR9 */
1159 PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD), 1172 PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
1160 PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0), 1173 PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
1161 PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2), 1174 PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
1162 PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3), 1175 PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
1163 PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1),
1164 PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), 1176 PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
1165 PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2), 1177 PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
1166 PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0),
1167 PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK), 1178 PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
1168 PINMUX_IPSR_GPSR(IP9_5_3, IRQ0), 1179 PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
1169 PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0), 1180 PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
1170 PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4), 1181 PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
1171 PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0),
1172 PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C), 1182 PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
1173 PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC), 1183 PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
1174 PINMUX_IPSR_GPSR(IP9_8_6, PWM1), 1184 PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
1175 PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0), 1185 PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
1176 PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5), 1186 PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
1177 PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0),
1178 PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1), 1187 PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
1179 PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1), 1188 PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
1180 PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0), 1189 PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
1181 PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0), 1190 PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
1182 PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6), 1191 PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
1183 PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0),
1184 PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1), 1192 PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
1185 PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1),
1186 PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2), 1193 PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
1187 PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0), 1194 PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
1188 PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), 1195 PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
1189 PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7), 1196 PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
1190 PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0),
1191 PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1), 1197 PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
1192 PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1),
1193 PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0), 1198 PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
1194 PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0), 1199 PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
1195 PINMUX_IPSR_GPSR(IP9_16_15, PWM6), 1200 PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
@@ -1204,128 +1209,93 @@ static const u16 pinmux_data[] = {
1204 PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2), 1209 PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
1205 PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1), 1210 PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
1206 PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1), 1211 PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
1207 PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1),
1208 PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0), 1212 PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
1209 PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0), 1213 PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
1210 PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0), 1214 PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
1211 PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3), 1215 PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
1212 PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1), 1216 PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
1213 PINMUX_IPSR_GPSR(IP9_24_22, CAN_DEBUG_HW_TRIGGER),
1214 PINMUX_IPSR_GPSR(IP9_24_22, CC50_STATE32),
1215 PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0), 1217 PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
1216 PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0), 1218 PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
1217 PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0), 1219 PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
1218 PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4), 1220 PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
1219 PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1), 1221 PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
1220 PINMUX_IPSR_GPSR(IP9_27_25, CAN_STEP0),
1221 PINMUX_IPSR_GPSR(IP9_27_25, CC50_STATE33),
1222 PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0), 1222 PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
1223 PINMUX_IPSR_GPSR(IP9_30_28, PWM3), 1223 PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
1224 PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0), 1224 PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
1225 PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5), 1225 PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
1226 PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1), 1226 PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
1227 PINMUX_IPSR_GPSR(IP9_30_28, CAN_TXCLK),
1228 PINMUX_IPSR_GPSR(IP9_30_28, CC50_STATE34),
1229 1227
1230 /* IPSR10 */ 1228 /* IPSR10 */
1231 PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0), 1229 PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
1232 PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0), 1230 PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0),
1233 PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6), 1231 PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
1234 PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1), 1232 PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
1235 PINMUX_IPSR_GPSR(IP10_2_0, CAN_DEBUGOUT0),
1236 PINMUX_IPSR_GPSR(IP10_2_0, CC50_STATE35),
1237 PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0), 1233 PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
1238 PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0), 1234 PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0),
1239 PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7), 1235 PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
1240 PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1), 1236 PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
1241 PINMUX_IPSR_GPSR(IP10_5_3, CAN_DEBUGOUT1),
1242 PINMUX_IPSR_GPSR(IP10_5_3, CC50_STATE36),
1243 PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0), 1237 PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
1244 PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0), 1238 PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0),
1245 PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0), 1239 PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
1246 PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1), 1240 PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
1247 PINMUX_IPSR_GPSR(IP10_8_6, USB0_EXTLP),
1248 PINMUX_IPSR_GPSR(IP10_8_6, CAN_DEBUGOUT2),
1249 PINMUX_IPSR_GPSR(IP10_8_6, CC50_STATE37),
1250 PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0), 1241 PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
1251 PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0), 1242 PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0),
1252 PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1), 1243 PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
1253 PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1), 1244 PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
1254 PINMUX_IPSR_GPSR(IP10_11_9, USB0_OVC1),
1255 PINMUX_IPSR_GPSR(IP10_11_9, CAN_DEBUGOUT3),
1256 PINMUX_IPSR_GPSR(IP10_11_9, CC50_STATE38),
1257 PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0), 1245 PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
1258 PINMUX_IPSR_GPSR(IP10_14_12, IRQ1), 1246 PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
1259 PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2), 1247 PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
1260 PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1), 1248 PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
1261 PINMUX_IPSR_GPSR(IP10_14_12, USB0_IDIN),
1262 PINMUX_IPSR_GPSR(IP10_14_12, CAN_DEBUGOUT4),
1263 PINMUX_IPSR_GPSR(IP10_14_12, CC50_STATE39),
1264 PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0), 1249 PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
1265 PINMUX_IPSR_GPSR(IP10_17_15, IRQ2), 1250 PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
1266 PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3), 1251 PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
1267 PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3), 1252 PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
1268 PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1), 1253 PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
1269 PINMUX_IPSR_GPSR(IP10_17_15, TANS2),
1270 PINMUX_IPSR_GPSR(IP10_17_15, CAN_DEBUGOUT5),
1271 PINMUX_IPSR_GPSR(IP10_17_15, CC50_OSCOUT),
1272 PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0), 1254 PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
1273 PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4), 1255 PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
1274 PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3), 1256 PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
1275 PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4), 1257 PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
1276 PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2), 1258 PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
1277 PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1), 1259 PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
1278 PINMUX_IPSR_GPSR(IP10_20_18, CAN_DEBUGOUT6),
1279 PINMUX_IPSR_MSEL(IP10_20_18, RDS_CLK_C, SEL_RDS_2),
1280 PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0), 1260 PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
1281 PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4), 1261 PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
1282 PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3), 1262 PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
1283 PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5), 1263 PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
1284 PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2), 1264 PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
1285 PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1), 1265 PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
1286 PINMUX_IPSR_GPSR(IP10_23_21, CAN_DEBUGOUT7),
1287 PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2),
1288 PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0), 1266 PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
1289 PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0), 1267 PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
1290 PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6), 1268 PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
1291 PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2), 1269 PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
1292 PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1), 1270 PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
1293 PINMUX_IPSR_GPSR(IP10_26_24, CAN_DEBUGOUT8),
1294 PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0), 1271 PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
1295 PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0), 1272 PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
1296 PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7), 1273 PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
1297 PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2), 1274 PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
1298 PINMUX_IPSR_GPSR(IP10_29_27, CAN_DEBUGOUT9),
1299 PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0), 1275 PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
1300 PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0), 1276 PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
1301 PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN), 1277 PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
1302 PINMUX_IPSR_GPSR(IP10_31_30, CAN_DEBUGOUT10),
1303 1278
1304 /* IPSR11 */ 1279 /* IPSR11 */
1305 PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0), 1280 PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
1306 PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), 1281 PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1307 PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), 1282 PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
1308 PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0), 1283 PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
1309 PINMUX_IPSR_GPSR(IP11_2_0, CAN_DEBUGOUT11),
1310 PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), 1284 PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
1311 PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), 1285 PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
1312 PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), 1286 PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
1313 PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1), 1287 PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
1314 PINMUX_IPSR_GPSR(IP11_5_3, CAN_DEBUGOUT12),
1315 PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0), 1288 PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
1316 PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), 1289 PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
1317 PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC), 1290 PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
1318 PINMUX_IPSR_GPSR(IP11_7_6, CAN_DEBUGOUT13),
1319 PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0), 1291 PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
1320 PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), 1292 PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
1321 PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), 1293 PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
1322 PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC), 1294 PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
1323 PINMUX_IPSR_GPSR(IP11_10_8, CAN_DEBUGOUT14),
1324 PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), 1295 PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
1325 PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), 1296 PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
1326 PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), 1297 PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
1327 PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE), 1298 PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1328 PINMUX_IPSR_GPSR(IP11_13_11, CAN_DEBUGOUT15),
1329 PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0), 1299 PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
1330 PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), 1300 PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
1331 PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2), 1301 PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2),
@@ -1339,30 +1309,24 @@ static const u16 pinmux_data[] = {
1339 PINMUX_IPSR_GPSR(IP11_20_18, IRQ8), 1309 PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
1340 PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), 1310 PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
1341 PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3), 1311 PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
1342 PINMUX_IPSR_GPSR(IP11_20_18, PCMOE_N),
1343 PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129), 1312 PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
1344 PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), 1313 PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
1345 PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), 1314 PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
1346 PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1), 1315 PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
1347 PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1),
1348 PINMUX_IPSR_GPSR(IP11_23_21, PCMWE_N),
1349 PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129), 1316 PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
1350 PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), 1317 PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
1351 PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), 1318 PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
1352 PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), 1319 PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
1353 PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1),
1354 PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0), 1320 PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
1355 PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), 1321 PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
1356 PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B), 1322 PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
1357 PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1), 1323 PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
1358 PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1),
1359 1324
1360 /* IPSR12 */ 1325 /* IPSR12 */
1361 PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34), 1326 PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
1362 PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1), 1327 PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
1363 PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2), 1328 PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
1364 PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1), 1329 PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
1365 PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1),
1366 PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1), 1330 PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
1367 PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34), 1331 PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
1368 PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1), 1332 PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
@@ -1379,15 +1343,12 @@ static const u16 pinmux_data[] = {
1379 PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0), 1343 PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
1380 PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK), 1344 PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
1381 PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1), 1345 PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
1382 PINMUX_IPSR_GPSR(IP12_10_9, IRD_TX),
1383 PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0), 1346 PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
1384 PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG), 1347 PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
1385 PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1), 1348 PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
1386 PINMUX_IPSR_GPSR(IP12_12_11, IRD_RX),
1387 PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0), 1349 PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
1388 PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT), 1350 PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
1389 PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1), 1351 PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
1390 PINMUX_IPSR_GPSR(IP12_14_13, IRD_SCK),
1391 PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0), 1352 PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
1392 PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1), 1353 PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
1393 PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B), 1354 PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
@@ -1400,25 +1361,21 @@ static const u16 pinmux_data[] = {
1400 PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2), 1361 PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2),
1401 PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK), 1362 PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
1402 PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3), 1363 PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
1403 PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0),
1404 PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1), 1364 PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
1405 PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0), 1365 PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
1406 PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1), 1366 PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
1407 PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2), 1367 PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2),
1408 PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0), 1368 PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
1409 PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3), 1369 PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
1410 PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0),
1411 PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1), 1370 PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
1412 PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0), 1371 PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
1413 PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1), 1372 PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
1414 PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1), 1373 PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
1415 PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0),
1416 PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N), 1374 PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
1417 PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1), 1375 PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
1418 PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0), 1376 PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
1419 PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1), 1377 PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
1420 PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2), 1378 PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
1421 PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0),
1422 PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N), 1379 PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
1423 PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1), 1380 PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
1424 1381
@@ -1427,21 +1384,18 @@ static const u16 pinmux_data[] = {
1427 PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1), 1384 PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
1428 PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3), 1385 PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
1429 PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3), 1386 PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
1430 PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0),
1431 PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N), 1387 PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
1432 PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1), 1388 PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
1433 PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0), 1389 PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
1434 PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1), 1390 PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
1435 PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3), 1391 PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
1436 PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4), 1392 PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
1437 PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0),
1438 PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N), 1393 PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
1439 PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1), 1394 PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
1440 PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0), 1395 PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
1441 PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1), 1396 PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
1442 PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B), 1397 PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
1443 PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5), 1398 PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
1444 PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0),
1445 PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1), 1399 PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
1446 PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1), 1400 PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
1447 PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0), 1401 PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
@@ -1461,14 +1415,12 @@ static const u16 pinmux_data[] = {
1461 PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3), 1415 PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
1462 PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB), 1416 PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
1463 PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), 1417 PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
1464 PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1),
1465 PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1), 1418 PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
1466 PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0), 1419 PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
1467 PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1), 1420 PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
1468 PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3), 1421 PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
1469 PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD), 1422 PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
1470 PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), 1423 PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
1471 PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1),
1472 PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4), 1424 PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
1473 PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1), 1425 PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
1474 PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0), 1426 PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
@@ -1476,17 +1428,13 @@ static const u16 pinmux_data[] = {
1476 PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3), 1428 PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
1477 PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N), 1429 PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
1478 PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), 1430 PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
1479 PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1),
1480 PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4), 1431 PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
1481 PINMUX_IPSR_MSEL(IP13_23_21, RDS_CLK_D, SEL_RDS_3),
1482 PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0), 1432 PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
1483 PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1), 1433 PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
1484 PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3), 1434 PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
1485 PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N), 1435 PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
1486 PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), 1436 PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
1487 PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1),
1488 PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4), 1437 PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
1489 PINMUX_IPSR_MSEL(IP13_26_24, RDS_DATA_D, SEL_RDS_3),
1490}; 1438};
1491 1439
1492static const struct sh_pfc_pin pinmux_pins[] = { 1440static const struct sh_pfc_pin pinmux_pins[] = {
@@ -4512,7 +4460,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4512 /* IP1_19_18 [2] */ 4460 /* IP1_19_18 [2] */
4513 FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0, 4461 FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0,
4514 /* IP1_17_15 [3] */ 4462 /* IP1_17_15 [3] */
4515 FN_D13, FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, 4463 FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B,
4516 0, 0, 0, 4464 0, 0, 0,
4517 /* IP1_14_13 [2] */ 4465 /* IP1_14_13 [2] */
4518 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, 4466 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
@@ -4533,19 +4481,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4533 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, 4481 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4534 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) { 4482 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
4535 /* IP2_31_30 [2] */ 4483 /* IP2_31_30 [2] */
4536 FN_A20, FN_SPCLK, FN_MOUT1, 0, 4484 FN_A20, FN_SPCLK, 0, 0,
4537 /* IP2_29_27 [3] */ 4485 /* IP2_29_27 [3] */
4538 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2, 4486 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
4539 FN_MOUT0, 0, 0, 0, 4487 0, 0, 0, 0,
4540 /* IP2_26_24 [3] */ 4488 /* IP2_26_24 [3] */
4541 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B, 4489 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
4542 FN_AVB_AVTP_MATCH_B, 0, 0, 0, 4490 0, 0, 0, 0,
4543 /* IP2_23_21 [3] */ 4491 /* IP2_23_21 [3] */
4544 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, 4492 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
4545 FN_AVB_AVTP_CAPTURE_B, 0, 0, 0, 4493 0, 0, 0, 0,
4546 /* IP2_20_18 [3] */ 4494 /* IP2_20_18 [3] */
4547 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, 4495 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
4548 FN_VSP, FN_CAN_CLK_C, FN_TPUTO2_B, 0, 4496 0, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
4549 /* IP2_17_16 [2] */ 4497 /* IP2_17_16 [2] */
4550 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, 4498 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
4551 /* IP2_15_14 [2] */ 4499 /* IP2_15_14 [2] */
@@ -4573,19 +4521,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4573 FN_RD_N, FN_ATACS11_N, 4521 FN_RD_N, FN_ATACS11_N,
4574 /* IP3_29_27 [3] */ 4522 /* IP3_29_27 [3] */
4575 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, 4523 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
4576 FN_MTS_N_B, 0, 0, 4524 0, 0, 0,
4577 /* IP3_26_24 [3] */ 4525 /* IP3_26_24 [3] */
4578 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, 4526 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
4579 FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B, 4527 0, FN_FMIN, FN_SCIFB2_RTS_N, 0,
4580 /* IP3_23_21 [3] */ 4528 /* IP3_23_21 [3] */
4581 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, 4529 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
4582 FN_RIF0_D0, FN_FMCLK, FN_SCIFB2_CTS_N, FN_SCKZ_B, 4530 0, FN_FMCLK, FN_SCIFB2_CTS_N, 0,
4583 /* IP3_20_18 [3] */ 4531 /* IP3_20_18 [3] */
4584 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, 4532 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
4585 FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, 4533 0, FN_BPFCLK, FN_SCIFB2_SCK, 0,
4586 /* IP3_17_15 [3] */ 4534 /* IP3_17_15 [3] */
4587 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, 4535 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
4588 FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, FN_SDATA_B, 4536 0, FN_TPUTO3, FN_SCIFB2_TXD, 0,
4589 /* IP3_14_13 [2] */ 4537 /* IP3_14_13 [2] */
4590 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, 4538 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
4591 /* IP3_12 [1] */ 4539 /* IP3_12 [1] */
@@ -4599,88 +4547,88 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4599 /* IP3_7_6 [2] */ 4547 /* IP3_7_6 [2] */
4600 FN_A24, FN_IO3, FN_EX_WAIT2, 0, 4548 FN_A24, FN_IO3, FN_EX_WAIT2, 0,
4601 /* IP3_5_4 [2] */ 4549 /* IP3_5_4 [2] */
4602 FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, 4550 FN_A23, FN_IO2, 0, FN_ATAWR1_N,
4603 /* IP3_3_2 [2] */ 4551 /* IP3_3_2 [2] */
4604 FN_A22, FN_MISO_IO1, FN_MOUT5, FN_ATADIR1_N, 4552 FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
4605 /* IP3_1_0 [2] */ 4553 /* IP3_1_0 [2] */
4606 FN_A21, FN_MOSI_IO0, FN_MOUT2, 0, } 4554 FN_A21, FN_MOSI_IO0, 0, 0, }
4607 }, 4555 },
4608 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, 4556 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
4609 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) { 4557 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) {
4610 /* IP4_31_30 [2] */ 4558 /* IP4_31_30 [2] */
4611 FN_DU0_DG4, FN_LCDOUT12, FN_CC50_STATE12, 0, 4559 FN_DU0_DG4, FN_LCDOUT12, 0, 0,
4612 /* IP4_29_28 [2] */ 4560 /* IP4_29_28 [2] */
4613 FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, 0, 4561 FN_DU0_DG3, FN_LCDOUT11, 0, 0,
4614 /* IP4_27_26 [2] */ 4562 /* IP4_27_26 [2] */
4615 FN_DU0_DG2, FN_LCDOUT10, FN_CC50_STATE10, 0, 4563 FN_DU0_DG2, FN_LCDOUT10, 0, 0,
4616 /* IP4_25_23 [3] */ 4564 /* IP4_25_23 [3] */
4617 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, 4565 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
4618 FN_CC50_STATE9, 0, 0, 0, 4566 0, 0, 0, 0,
4619 /* IP4_22_20 [3] */ 4567 /* IP4_22_20 [3] */
4620 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, 4568 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
4621 FN_CC50_STATE8, 0, 0, 0, 4569 0, 0, 0, 0,
4622 /* IP4_19_18 [2] */ 4570 /* IP4_19_18 [2] */
4623 FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, 0, 4571 FN_DU0_DR7, FN_LCDOUT23, 0, 0,
4624 /* IP4_17_16 [2] */ 4572 /* IP4_17_16 [2] */
4625 FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, 0, 4573 FN_DU0_DR6, FN_LCDOUT22, 0, 0,
4626 /* IP4_15_14 [2] */ 4574 /* IP4_15_14 [2] */
4627 FN_DU0_DR5, FN_LCDOUT21, FN_CC50_STATE5, 0, 4575 FN_DU0_DR5, FN_LCDOUT21, 0, 0,
4628 /* IP4_13_12 [2] */ 4576 /* IP4_13_12 [2] */
4629 FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, 0, 4577 FN_DU0_DR4, FN_LCDOUT20, 0, 0,
4630 /* IP4_11_10 [2] */ 4578 /* IP4_11_10 [2] */
4631 FN_DU0_DR3, FN_LCDOUT19, FN_CC50_STATE3, 0, 4579 FN_DU0_DR3, FN_LCDOUT19, 0, 0,
4632 /* IP4_9_8 [2] */ 4580 /* IP4_9_8 [2] */
4633 FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, 0, 4581 FN_DU0_DR2, FN_LCDOUT18, 0, 0,
4634 /* IP4_7_5 [3] */ 4582 /* IP4_7_5 [3] */
4635 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, 4583 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
4636 FN_CC50_STATE1, 0, 0, 0, 4584 0, 0, 0, 0,
4637 /* IP4_4_2 [3] */ 4585 /* IP4_4_2 [3] */
4638 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, 4586 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
4639 FN_CC50_STATE0, 0, 0, 0, 4587 0, 0, 0, 0,
4640 /* IP4_1_0 [2] */ 4588 /* IP4_1_0 [2] */
4641 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, } 4589 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, }
4642 }, 4590 },
4643 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 4591 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
4644 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) { 4592 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) {
4645 /* IP5_31_30 [2] */ 4593 /* IP5_31_30 [2] */
4646 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, 0, 4594 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
4647 /* IP5_29_28 [2] */ 4595 /* IP5_29_28 [2] */
4648 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_CC50_STATE26, 0, 4596 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0,
4649 /* IP5_27_26 [2] */ 4597 /* IP5_27_26 [2] */
4650 FN_DU0_DOTCLKOUT0, FN_QCLK, FN_CC50_STATE25, 0, 4598 FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0,
4651 /* IP5_25_24 [2] */ 4599 /* IP5_25_24 [2] */
4652 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, 0, 4600 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0,
4653 /* IP5_23_22 [2] */ 4601 /* IP5_23_22 [2] */
4654 FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, 0, 4602 FN_DU0_DB7, FN_LCDOUT7, 0, 0,
4655 /* IP5_21_20 [2] */ 4603 /* IP5_21_20 [2] */
4656 FN_DU0_DB6, FN_LCDOUT6, FN_CC50_STATE22, 0, 4604 FN_DU0_DB6, FN_LCDOUT6, 0, 0,
4657 /* IP5_19_18 [2] */ 4605 /* IP5_19_18 [2] */
4658 FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, 0, 4606 FN_DU0_DB5, FN_LCDOUT5, 0, 0,
4659 /* IP5_17_16 [2] */ 4607 /* IP5_17_16 [2] */
4660 FN_DU0_DB4, FN_LCDOUT4, FN_CC50_STATE20, 0, 4608 FN_DU0_DB4, FN_LCDOUT4, 0, 0,
4661 /* IP5_15_14 [2] */ 4609 /* IP5_15_14 [2] */
4662 FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, 0, 4610 FN_DU0_DB3, FN_LCDOUT3, 0, 0,
4663 /* IP5_13_12 [2] */ 4611 /* IP5_13_12 [2] */
4664 FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, 0, 4612 FN_DU0_DB2, FN_LCDOUT2, 0, 0,
4665 /* IP5_11_9 [3] */ 4613 /* IP5_11_9 [3] */
4666 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, 4614 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
4667 FN_CAN0_TX_C, FN_CC50_STATE17, 0, 0, 4615 FN_CAN0_TX_C, 0, 0, 0,
4668 /* IP5_8_6 [3] */ 4616 /* IP5_8_6 [3] */
4669 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, 4617 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
4670 FN_CAN0_RX_C, FN_CC50_STATE16, 0, 0, 4618 FN_CAN0_RX_C, 0, 0, 0,
4671 /* IP5_5_4 [2] */ 4619 /* IP5_5_4 [2] */
4672 FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, 0, 4620 FN_DU0_DG7, FN_LCDOUT15, 0, 0,
4673 /* IP5_3_2 [2] */ 4621 /* IP5_3_2 [2] */
4674 FN_DU0_DG6, FN_LCDOUT14, FN_CC50_STATE14, 0, 4622 FN_DU0_DG6, FN_LCDOUT14, 0, 0,
4675 /* IP5_1_0 [2] */ 4623 /* IP5_1_0 [2] */
4676 FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, 0, } 4624 FN_DU0_DG5, FN_LCDOUT13, 0, 0, }
4677 }, 4625 },
4678 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 4626 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
4679 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 4627 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
4680 2, 2) { 4628 2, 2) {
4681 /* IP6_31_29 [3] */ 4629 /* IP6_31_29 [3] */
4682 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, 4630 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
4683 FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0, 4631 FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
4684 /* IP6_28_26 [3] */ 4632 /* IP6_28_26 [3] */
4685 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, 4633 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
4686 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0, 4634 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
@@ -4712,14 +4660,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4712 /* IP6_8 [1] */ 4660 /* IP6_8 [1] */
4713 FN_VI0_CLK, FN_AVB_RX_CLK, 4661 FN_VI0_CLK, FN_AVB_RX_CLK,
4714 /* IP6_7_6 [2] */ 4662 /* IP6_7_6 [2] */
4715 FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0, 4663 FN_DU0_CDE, FN_QPOLB, 0, 0,
4716 /* IP6_5_4 [2] */ 4664 /* IP6_5_4 [2] */
4717 FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0, 4665 FN_DU0_DISP, FN_QPOLA, 0, 0,
4718 /* IP6_3_2 [2] */ 4666 /* IP6_3_2 [2] */
4719 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, 4667 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
4720 0, 4668 0,
4721 /* IP6_1_0 [2] */ 4669 /* IP6_1_0 [2] */
4722 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, } 4670 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, }
4723 }, 4671 },
4724 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, 4672 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
4725 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 4673 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
@@ -4750,25 +4698,25 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4750 FN_AVB_TXD3, FN_ADICHS1, 0, 0, 4698 FN_AVB_TXD3, FN_ADICHS1, 0, 0,
4751 /* IP7_8_6 [3] */ 4699 /* IP7_8_6 [3] */
4752 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, 4700 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
4753 FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0, 4701 FN_AVB_TXD2, FN_ADICHS0, 0, 0,
4754 /* IP7_5_3 [3] */ 4702 /* IP7_5_3 [3] */
4755 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, 4703 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
4756 FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0, 4704 FN_AVB_TXD1, FN_ADICLK, 0, 0,
4757 /* IP7_2_0 [3] */ 4705 /* IP7_2_0 [3] */
4758 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, 4706 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
4759 FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, } 4707 FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, }
4760 }, 4708 },
4761 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 4709 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
4762 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) { 4710 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
4763 /* IP8_31_29 [3] */ 4711 /* IP8_31_29 [3] */
4764 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, 4712 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
4765 FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, 4713 0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
4766 /* IP8_28_26 [3] */ 4714 /* IP8_28_26 [3] */
4767 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, 4715 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
4768 FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0, 4716 0, FN_TS_SCK_D, FN_BPFCLK_C, 0,
4769 /* IP8_25_23 [3] */ 4717 /* IP8_25_23 [3] */
4770 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, 4718 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
4771 FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0, 4719 0, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
4772 /* IP8_22_20 [3] */ 4720 /* IP8_22_20 [3] */
4773 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, 4721 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
4774 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0, 4722 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
@@ -4799,70 +4747,70 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4799 0, 0, 4747 0, 0,
4800 /* IP9_30_28 [3] */ 4748 /* IP9_30_28 [3] */
4801 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, 4749 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
4802 FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, 0, 4750 FN_SSI_SDATA1_B, 0, 0, 0,
4803 /* IP9_27_25 [3] */ 4751 /* IP9_27_25 [3] */
4804 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, 4752 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
4805 FN_SSI_WS1_B, FN_CAN_STEP0, FN_CC50_STATE33, 0, 4753 FN_SSI_WS1_B, 0, 0, 0,
4806 /* IP9_24_22 [3] */ 4754 /* IP9_24_22 [3] */
4807 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, 4755 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
4808 FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, 0, 4756 FN_SSI_SCK1_B, 0, 0, 0,
4809 /* IP9_21_19 [3] */ 4757 /* IP9_21_19 [3] */
4810 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, 4758 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
4811 FN_REMOCON_B, FN_SPEEDIN_B, FN_VSP_B, 0, 4759 FN_REMOCON_B, FN_SPEEDIN_B, 0, 0,
4812 /* IP9_18_17 [2] */ 4760 /* IP9_18_17 [2] */
4813 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, 4761 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
4814 /* IP9_16_15 [2] */ 4762 /* IP9_16_15 [2] */
4815 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0, 4763 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
4816 /* IP9_14_12 [3] */ 4764 /* IP9_14_12 [3] */
4817 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, 4765 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
4818 FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, 0, 4766 0, FN_FMIN_B, 0, 0,
4819 /* IP9_11_9 [3] */ 4767 /* IP9_11_9 [3] */
4820 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, 4768 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
4821 FN_RIF1_D0, FN_FMCLK_B, FN_RDS_CLK_B, 0, 4769 0, FN_FMCLK_B, 0, 0,
4822 /* IP9_8_6 [3] */ 4770 /* IP9_8_6 [3] */
4823 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, 4771 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
4824 FN_RIF1_CLK, FN_BPFCLK_B, 0, 0, 4772 0, FN_BPFCLK_B, 0, 0,
4825 /* IP9_5_3 [3] */ 4773 /* IP9_5_3 [3] */
4826 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, 4774 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
4827 FN_RIF1_SYNC, FN_TPUTO1_C, 0, 0, 4775 0, FN_TPUTO1_C, 0, 0,
4828 /* IP9_2_0 [3] */ 4776 /* IP9_2_0 [3] */
4829 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, 4777 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
4830 FN_RIF1_D1_B, FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, } 4778 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, }
4831 }, 4779 },
4832 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 4780 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
4833 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 4781 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4834 /* IP10_31_30 [2] */ 4782 /* IP10_31_30 [2] */
4835 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10, 4783 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
4836 /* IP10_29_27 [3] */ 4784 /* IP10_29_27 [3] */
4837 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, 4785 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
4838 FN_CAN_DEBUGOUT9, 0, 0, 0, 4786 0, 0, 0, 0,
4839 /* IP10_26_24 [3] */ 4787 /* IP10_26_24 [3] */
4840 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C, 4788 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
4841 FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, 0, 0, 4789 FN_SSI_SDATA4_B, 0, 0, 0,
4842 /* IP10_23_21 [3] */ 4790 /* IP10_23_21 [3] */
4843 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, 4791 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
4844 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, 4792 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0,
4845 /* IP10_20_18 [3] */ 4793 /* IP10_20_18 [3] */
4846 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, 4794 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
4847 FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, 4795 FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0,
4848 /* IP10_17_15 [3] */ 4796 /* IP10_17_15 [3] */
4849 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, 4797 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
4850 FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT, 4798 FN_SSI_SDATA9_B, 0, 0, 0,
4851 /* IP10_14_12 [3] */ 4799 /* IP10_14_12 [3] */
4852 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B, 4800 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
4853 FN_USB0_IDIN, FN_CAN_DEBUGOUT4, FN_CC50_STATE39, 0, 4801 0, 0, 0, 0,
4854 /* IP10_11_9 [3] */ 4802 /* IP10_11_9 [3] */
4855 FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, 4803 FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
4856 FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, 0, 4804 0, 0, 0, 0,
4857 /* IP10_8_6 [3] */ 4805 /* IP10_8_6 [3] */
4858 FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B, 4806 FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
4859 FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, FN_CC50_STATE37, 0, 4807 0, 0, 0, 0,
4860 /* IP10_5_3 [3] */ 4808 /* IP10_5_3 [3] */
4861 FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B, 4809 FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
4862 FN_CAN_DEBUGOUT1, FN_CC50_STATE36, 0, 0, 4810 0, 0, 0, 0,
4863 /* IP10_2_0 [3] */ 4811 /* IP10_2_0 [3] */
4864 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, 4812 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
4865 FN_CAN_DEBUGOUT0, FN_CC50_STATE35, 0, 0, } 4813 0, 0, 0, 0, }
4866 }, 4814 },
4867 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 4815 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
4868 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) { 4816 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
@@ -4870,61 +4818,60 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4870 0, 0, 0, 0, 4818 0, 0, 0, 0,
4871 /* IP11_29_27 [3] */ 4819 /* IP11_29_27 [3] */
4872 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, 4820 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
4873 FN_AD_CLK_B, 0, 0, 0, 4821 0, 0, 0, 0,
4874 /* IP11_26_24 [3] */ 4822 /* IP11_26_24 [3] */
4875 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B, 4823 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
4876 FN_AD_DO_B, 0, 0, 0, 4824 0, 0, 0, 0,
4877 /* IP11_23_21 [3] */ 4825 /* IP11_23_21 [3] */
4878 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, 4826 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
4879 FN_AD_DI_B, FN_PCMWE_N, 0, 0, 4827 0, 0, 0, 0,
4880 /* IP11_20_18 [3] */ 4828 /* IP11_20_18 [3] */
4881 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, 4829 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
4882 FN_CAN_CLK_D, FN_PCMOE_N, 0, 0, 4830 FN_CAN_CLK_D, 0, 0, 0,
4883 /* IP11_17_16 [2] */ 4831 /* IP11_17_16 [2] */
4884 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE, 4832 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
4885 /* IP11_15_14 [2] */ 4833 /* IP11_15_14 [2] */
4886 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP, 4834 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
4887 /* IP11_13_11 [3] */ 4835 /* IP11_13_11 [3] */
4888 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, 4836 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
4889 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0, 4837 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0,
4890 /* IP11_10_8 [3] */ 4838 /* IP11_10_8 [3] */
4891 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, 4839 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
4892 FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0, 4840 FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0,
4893 /* IP11_7_6 [2] */ 4841 /* IP11_7_6 [2] */
4894 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 4842 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0,
4895 FN_CAN_DEBUGOUT13,
4896 /* IP11_5_3 [3] */ 4843 /* IP11_5_3 [3] */
4897 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1, 4844 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
4898 FN_CAN_DEBUGOUT12, 0, 0, 0, 4845 0, 0, 0, 0,
4899 /* IP11_2_0 [3] */ 4846 /* IP11_2_0 [3] */
4900 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, 4847 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
4901 FN_CAN_DEBUGOUT11, 0, 0, 0, } 4848 0, 0, 0, 0, }
4902 }, 4849 },
4903 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 4850 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
4904 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) { 4851 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) {
4905 /* IP12_31_30 [2] */ 4852 /* IP12_31_30 [2] */
4906 0, 0, 0, 0, 4853 0, 0, 0, 0,
4907 /* IP12_29_27 [3] */ 4854 /* IP12_29_27 [3] */
4908 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA, 4855 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
4909 FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0, 4856 FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
4910 /* IP12_26_24 [3] */ 4857 /* IP12_26_24 [3] */
4911 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA, 4858 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0,
4912 FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0, 4859 FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
4913 /* IP12_23_21 [3] */ 4860 /* IP12_23_21 [3] */
4914 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, 4861 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0,
4915 FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0, 4862 FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0,
4916 /* IP12_20_18 [3] */ 4863 /* IP12_20_18 [3] */
4917 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, 4864 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK,
4918 FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, 0, 4865 FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0,
4919 /* IP12_17_15 [3] */ 4866 /* IP12_17_15 [3] */
4920 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, 4867 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
4921 FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0, 4868 FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
4922 /* IP12_14_13 [2] */ 4869 /* IP12_14_13 [2] */
4923 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, FN_IRD_SCK, 4870 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0,
4924 /* IP12_12_11 [2] */ 4871 /* IP12_12_11 [2] */
4925 FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, 4872 FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0,
4926 /* IP12_10_9 [2] */ 4873 /* IP12_10_9 [2] */
4927 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, 4874 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0,
4928 /* IP12_8_6 [3] */ 4875 /* IP12_8_6 [3] */
4929 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, 4876 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
4930 FN_CAN1_TX_C, FN_DREQ2_N, 0, 0, 4877 FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
@@ -4933,7 +4880,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4933 FN_CAN1_RX_C, FN_DACK1_B, 0, 0, 4880 FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
4934 /* IP12_2_0 [3] */ 4881 /* IP12_2_0 [3] */
4935 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, 4882 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
4936 FN_AD_NCS_N_B, FN_DREQ1_N_B, 0, 0, } 4883 0, FN_DREQ1_N_B, 0, 0, }
4937 }, 4884 },
4938 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 4885 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
4939 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 4886 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
@@ -4949,16 +4896,16 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4949 0, 0, 4896 0, 0,
4950 /* IP13_26_24 [3] */ 4897 /* IP13_26_24 [3] */
4951 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, 4898 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
4952 FN_TS_SPSYNC_C, FN_RIF0_D1_B, FN_FMIN_E, FN_RDS_DATA_D, 4899 FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
4953 /* IP13_23_21 [3] */ 4900 /* IP13_23_21 [3] */
4954 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, 4901 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
4955 FN_TS_SDEN_C, FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, 4902 FN_TS_SDEN_C, 0, FN_FMCLK_E, 0,
4956 /* IP13_20_18 [3] */ 4903 /* IP13_20_18 [3] */
4957 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, 4904 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
4958 FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, 4905 FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B,
4959 /* IP13_17_15 [3] */ 4906 /* IP13_17_15 [3] */
4960 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB, 4907 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
4961 FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, 0, 4908 FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0,
4962 /* IP13_14_12 [3] */ 4909 /* IP13_14_12 [3] */
4963 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, 4910 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
4964 FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0, 4911 FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
@@ -4967,38 +4914,32 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4967 FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0, 4914 FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
4968 /* IP13_8_6 [3] */ 4915 /* IP13_8_6 [3] */
4969 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, 4916 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
4970 FN_MTS_N, FN_EX_WAIT1, FN_ETH_TXD1_B, 0, 4917 0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
4971 /* IP13_5_3 [2] */ 4918 /* IP13_5_3 [2] */
4972 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, 4919 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
4973 FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, 0, 4920 FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
4974 /* IP13_2_0 [3] */ 4921 /* IP13_2_0 [3] */
4975 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, 4922 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
4976 FN_SCKZ, FN_ATACS00_N, FN_ETH_LINK_B, 0, } 4923 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, }
4977 }, 4924 },
4978 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, 4925 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
4979 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 4926 2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3,
4980 2, 1) { 4927 2, 1) {
4981 /* SEL_ADG [2] */ 4928 /* SEL_ADG [2] */
4982 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, 4929 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
4983 /* SEL_ADI [1] */ 4930 /* RESERVED [1] */
4984 FN_SEL_ADI_0, FN_SEL_ADI_1, 4931 0, 0,
4985 /* SEL_CAN [2] */ 4932 /* SEL_CAN [2] */
4986 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, 4933 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
4987 /* SEL_DARC [3] */ 4934 /* SEL_DARC [3] */
4988 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, 4935 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
4989 FN_SEL_DARC_4, 0, 0, 0, 4936 FN_SEL_DARC_4, 0, 0, 0,
4990 /* SEL_DR0 [1] */ 4937 /* RESERVED [4] */
4991 FN_SEL_DR0_0, FN_SEL_DR0_1, 4938 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4992 /* SEL_DR1 [1] */
4993 FN_SEL_DR1_0, FN_SEL_DR1_1,
4994 /* SEL_DR2 [1] */
4995 FN_SEL_DR2_0, FN_SEL_DR2_1,
4996 /* SEL_DR3 [1] */
4997 FN_SEL_DR3_0, FN_SEL_DR3_1,
4998 /* SEL_ETH [1] */ 4939 /* SEL_ETH [1] */
4999 FN_SEL_ETH_0, FN_SEL_ETH_1, 4940 FN_SEL_ETH_0, FN_SEL_ETH_1,
5000 /* SLE_FSN [1] */ 4941 /* RESERVED [1] */
5001 FN_SEL_FSN_0, FN_SEL_FSN_1, 4942 0, 0,
5002 /* SEL_IC200 [3] */ 4943 /* SEL_IC200 [3] */
5003 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, 4944 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
5004 FN_SEL_I2C00_4, 0, 0, 0, 4945 FN_SEL_I2C00_4, 0, 0, 0,
@@ -5016,8 +4957,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5016 FN_SEL_I2C04_4, 0, 0, 0, 4957 FN_SEL_I2C04_4, 0, 0, 0,
5017 /* SEL_I2C05 [2] */ 4958 /* SEL_I2C05 [2] */
5018 FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3, 4959 FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
5019 /* SEL_AVB [1] */ 4960 /* RESERVED [1] */
5020 FN_SEL_AVB_0, FN_SEL_AVB_1, } 4961 0, 0, }
5021 }, 4962 },
5022 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 4963 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5023 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 4964 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
@@ -5053,8 +4994,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5053 /* SEL_SCIFA5 [2] */ 4994 /* SEL_SCIFA5 [2] */
5054 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 4995 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
5055 FN_SEL_SCIFA5_3, 4996 FN_SEL_SCIFA5_3,
5056 /* SEL_SPDM [1] */ 4997 /* RESERVED [1] */
5057 FN_SEL_SPDM_0, FN_SEL_SPDM_1, 4998 0, 0,
5058 /* SEL_TMU [1] */ 4999 /* SEL_TMU [1] */
5059 FN_SEL_TMU_0, FN_SEL_TMU_1, 5000 FN_SEL_TMU_0, FN_SEL_TMU_1,
5060 /* SEL_TSIF0 [2] */ 5001 /* SEL_TSIF0 [2] */
@@ -5067,8 +5008,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5067 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, 5008 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
5068 /* SEL_HSCIF1 [1] */ 5009 /* SEL_HSCIF1 [1] */
5069 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, 5010 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5070 /* SEL_RDS [2] */ 5011 /* RESERVED [2] */
5071 FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, } 5012 0, 0, 0, 0, }
5072 }, 5013 },
5073 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 5014 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5074 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 5015 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 03:11:56 -0400