7 files changed, 22 insertions, 39 deletions

diff --git a/drivers/mtd/nand/raw/ingenic/Kconfig b/drivers/mtd/nand/raw/ingenic/Kconfig
index 19a96ce515c1..66b7cffdb0c2 100644
--- a/drivers/mtd/nand/raw/ingenic/Kconfig
+++ b/drivers/mtd/nand/raw/ingenic/Kconfig
@@ -16,7 +16,7 @@ config MTD_NAND_JZ4780
 if MTD_NAND_JZ4780
 
 config MTD_NAND_INGENIC_ECC
-        tristate
+        bool
 
 config MTD_NAND_JZ4740_ECC
         tristate "Hardware BCH support for JZ4740 SoC"
diff --git a/drivers/mtd/nand/raw/ingenic/Makefile b/drivers/mtd/nand/raw/ingenic/Makefile
index 1ac4f455baea..b63d36889263 100644
--- a/drivers/mtd/nand/raw/ingenic/Makefile
+++ b/drivers/mtd/nand/raw/ingenic/Makefile
@@ -2,7 +2,9 @@
 obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
 obj-$(CONFIG_MTD_NAND_JZ4780) += ingenic_nand.o
 
-obj-$(CONFIG_MTD_NAND_INGENIC_ECC) += ingenic_ecc.o
+ingenic_nand-y += ingenic_nand_drv.o
+ingenic_nand-$(CONFIG_MTD_NAND_INGENIC_ECC) += ingenic_ecc.o
+
 obj-$(CONFIG_MTD_NAND_JZ4740_ECC) += jz4740_ecc.o
 obj-$(CONFIG_MTD_NAND_JZ4725B_BCH) += jz4725b_bch.o
 obj-$(CONFIG_MTD_NAND_JZ4780_BCH) += jz4780_bch.o
diff --git a/drivers/mtd/nand/raw/ingenic/ingenic_ecc.c b/drivers/mtd/nand/raw/ingenic/ingenic_ecc.c
index d3e085c5685a..c954189606f6 100644
--- a/drivers/mtd/nand/raw/ingenic/ingenic_ecc.c
+++ b/drivers/mtd/nand/raw/ingenic/ingenic_ecc.c
@@ -30,7 +30,6 @@ int ingenic_ecc_calculate(struct ingenic_ecc *ecc,
 {
         return ecc->ops->calculate(ecc, params, buf, ecc_code);
 }
-EXPORT_SYMBOL(ingenic_ecc_calculate);
 
 /**
  * ingenic_ecc_correct() - detect and correct bit errors
@@ -51,7 +50,6 @@ int ingenic_ecc_correct(struct ingenic_ecc *ecc,
 {
         return ecc->ops->correct(ecc, params, buf, ecc_code);
 }
-EXPORT_SYMBOL(ingenic_ecc_correct);
 
 /**
  * ingenic_ecc_get() - get the ECC controller device
@@ -111,7 +109,6 @@ struct ingenic_ecc *of_ingenic_ecc_get(struct device_node *of_node)
         }
         return ecc;
 }
-EXPORT_SYMBOL(of_ingenic_ecc_get);
 
 /**
  * ingenic_ecc_release() - release the ECC controller device
@@ -122,7 +119,6 @@ void ingenic_ecc_release(struct ingenic_ecc *ecc)
         clk_disable_unprepare(ecc->clk);
         put_device(ecc->dev);
 }
-EXPORT_SYMBOL(ingenic_ecc_release);
 
 int ingenic_ecc_probe(struct platform_device *pdev)
 {
@@ -159,8 +155,3 @@ int ingenic_ecc_probe(struct platform_device *pdev)
         return 0;
 }
 EXPORT_SYMBOL(ingenic_ecc_probe);
-
-MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
-MODULE_AUTHOR("Harvey Hunt <harveyhuntnexus@gmail.com>");
-MODULE_DESCRIPTION("Ingenic ECC common driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/mtd/nand/raw/ingenic/ingenic_nand.c b/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
index d7b7c0f13909..d7b7c0f13909 100644
--- a/drivers/mtd/nand/raw/ingenic/ingenic_nand.c
+++ b/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c
index b021a5720b42..89773293c64d 100644
--- a/drivers/mtd/nand/raw/sunxi_nand.c
+++ b/drivers/mtd/nand/raw/sunxi_nand.c
@@ -51,6 +51,7 @@
 #define NFC_REG_USER_DATA(x)    (0x0050 + ((x) * 4))
 #define NFC_REG_SPARE_AREA      0x00A0
 #define NFC_REG_PAT_ID          0x00A4
+#define NFC_REG_MDMA_CNT        0x00C4
 #define NFC_RAM0_BASE           0x0400
 #define NFC_RAM1_BASE           0x0800
 
@@ -69,6 +70,7 @@
 #define NFC_PAGE_SHIFT(x)       (((x) < 10 ? 0 : (x) - 10) << 8)
 #define NFC_SAM                 BIT(12)
 #define NFC_RAM_METHOD          BIT(14)
+#define NFC_DMA_TYPE_NORMAL     BIT(15)
 #define NFC_DEBUG_CTL           BIT(31)
 
 /* define bit use in NFC_ST */
@@ -205,14 +207,13 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
  * NAND Controller capabilities structure: stores NAND controller capabilities
  * for distinction between compatible strings.
  *
- * @sram_through_ahb:   On A23, we choose to access the internal RAM through AHB
- *                      instead of MBUS (less configuration). A10, A10s, A13 and
- *                      A20 use the MBUS but no extra configuration is needed.
+ * @extra_mbus_conf:    Contrary to A10, A10s and A13, accessing internal RAM
+ *                      through MBUS on A23/A33 needs extra configuration.
  * @reg_io_data:        I/O data register
  * @dma_maxburst:       DMA maxburst
  */
 struct sunxi_nfc_caps {
-        bool sram_through_ahb;
+        bool extra_mbus_conf;
         unsigned int reg_io_data;
         unsigned int dma_maxburst;
 };
@@ -368,28 +369,12 @@ static int sunxi_nfc_dma_op_prepare(struct sunxi_nfc *nfc, const void *buf,
                 goto err_unmap_buf;
         }
 
-        /*
-         * On A23, we suppose the "internal RAM" (p.12 of the NFC user manual)
-         * refers to the NAND controller's internal SRAM. This memory is mapped
-         * and so is accessible from the AHB. It seems that it can also be
-         * accessed by the MBUS. MBUS accesses are mandatory when using the
-         * internal DMA instead of the external DMA engine.
-         *
-         * During DMA I/O operation, either we access this memory from the AHB
-         * by clearing the NFC_RAM_METHOD bit, or we set the bit and use the
-         * MBUS. In this case, we should also configure the MBUS DMA length
-         * NFC_REG_MDMA_CNT(0xC4) to be chunksize * nchunks. NAND I/O over MBUS
-         * are also limited to 32kiB pages.
-         */
-        if (nfc->caps->sram_through_ahb)
-                writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
-                       nfc->regs + NFC_REG_CTL);
-        else
-                writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,
-                       nfc->regs + NFC_REG_CTL);
-
+        writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,
+               nfc->regs + NFC_REG_CTL);
         writel(nchunks, nfc->regs + NFC_REG_SECTOR_NUM);
         writel(chunksize, nfc->regs + NFC_REG_CNT);
+        if (nfc->caps->extra_mbus_conf)
+                writel(chunksize * nchunks, nfc->regs + NFC_REG_MDMA_CNT);
 
         dmat = dmaengine_submit(dmad);
 
@@ -2151,6 +2136,11 @@ static int sunxi_nfc_probe(struct platform_device *pdev)
                 dmac_cfg.src_maxburst = nfc->caps->dma_maxburst;
                 dmac_cfg.dst_maxburst = nfc->caps->dma_maxburst;
                 dmaengine_slave_config(nfc->dmac, &dmac_cfg);
+
+                if (nfc->caps->extra_mbus_conf)
+                        writel(readl(nfc->regs + NFC_REG_CTL) |
+                               NFC_DMA_TYPE_NORMAL, nfc->regs + NFC_REG_CTL);
+
         } else {
                 dev_warn(dev, "failed to request rxtx DMA channel\n");
         }
@@ -2200,7 +2190,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = {
 };
 
 static const struct sunxi_nfc_caps sunxi_nfc_a23_caps = {
-        .sram_through_ahb = true,
+        .extra_mbus_conf = true,
         .reg_io_data = NFC_REG_A23_IO_DATA,
         .dma_maxburst = 8,
 };
diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
index e5586390026a..e6c646007cda 100644
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -180,7 +180,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
                      SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
                                      gd5fxgq4xa_ecc_get_status)),
         SPINAND_INFO("GD5F4GQ4xA", 0xF4,
-                     NAND_MEMORG(1, 2048, 64, 64, 4096, 40, 1, 1, 1),
+                     NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1),
                      NAND_ECCREQ(8, 512),
                      SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
                                               &write_cache_variants,
diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c
index 6502727049a8..21def3f8fb36 100644
--- a/drivers/mtd/nand/spi/macronix.c
+++ b/drivers/mtd/nand/spi/macronix.c
@@ -100,7 +100,7 @@ static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand,
 
 static const struct spinand_info macronix_spinand_table[] = {
         SPINAND_INFO("MX35LF1GE4AB", 0x12,
-                     NAND_MEMORG(1, 2048, 64, 64, 1024, 40, 1, 1, 1),
+                     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
                      NAND_ECCREQ(4, 512),
                      SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
                                               &write_cache_variants,
@@ -109,7 +109,7 @@ static const struct spinand_info macronix_spinand_table[] = {
                      SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
                                      mx35lf1ge4ab_ecc_get_status)),
         SPINAND_INFO("MX35LF2GE4AB", 0x22,
-                     NAND_MEMORG(1, 2048, 64, 64, 2048, 20, 2, 1, 1),
+                     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
                      NAND_ECCREQ(4, 512),
                      SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
                                               &write_cache_variants,