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-rw-r--r--arch/arm/mach-omap2/clock.c3
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c4
-rw-r--r--arch/mips/alchemy/common/clock.c2
-rw-r--r--drivers/clk/clk-composite.c2
-rw-r--r--drivers/clk/clk-divider.c2
-rw-r--r--drivers/clk/clk-fixed-factor.c2
-rw-r--r--drivers/clk/clk-fixed-rate.c2
-rw-r--r--drivers/clk/clk-fractional-divider.c2
-rw-r--r--drivers/clk/clk-gate.c2
-rw-r--r--drivers/clk/clk-gpio.c2
-rw-r--r--drivers/clk/clk-mux.c2
-rw-r--r--drivers/clk/clk-pwm.c2
-rw-r--r--drivers/clk/clk.c1
-rw-r--r--drivers/clk/mmp/clk-gate.c2
-rw-r--r--drivers/clk/ti/clk-7xx-compat.c6
-rw-r--r--drivers/clk/ti/clk-7xx.c6
-rw-r--r--drivers/clk/ti/clkctrl.c17
-rw-r--r--drivers/clk/ti/clock.h8
-rw-r--r--drivers/pwm/pwm-meson.c2
-rw-r--r--include/linux/clk-provider.h2
-rw-r--r--include/linux/clk/ti.h2
21 files changed, 50 insertions, 23 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 42881f21cede..3e0f09cc0028 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -119,6 +119,9 @@ void __init ti_clk_init_features(void)
119 if (cpu_is_omap343x()) 119 if (cpu_is_omap343x())
120 features.flags |= TI_CLK_DPLL_HAS_FREQSEL; 120 features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
121 121
122 if (omap_type() == OMAP2_DEVICE_TYPE_GP)
123 features.flags |= TI_CLK_DEVICE_TYPE_GP;
124
122 /* Idlest value for interface clocks. 125 /* Idlest value for interface clocks.
123 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 126 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
124 * 34xx reverses this, just to keep us on our toes 127 * 34xx reverses this, just to keep us on our toes
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 3a04c73ac03c..baadddf9aad4 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -648,10 +648,10 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
648 if (oh->clkdm) { 648 if (oh->clkdm) {
649 return oh->clkdm; 649 return oh->clkdm;
650 } else if (oh->_clk) { 650 } else if (oh->_clk) {
651 if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC) 651 if (!omap2_clk_is_hw_omap(__clk_get_hw(oh->_clk)))
652 return NULL; 652 return NULL;
653 clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); 653 clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
654 return clk->clkdm; 654 return clk->clkdm;
655 } 655 }
656 return NULL; 656 return NULL;
657} 657}
diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c
index d129475fd40d..a95a894aceaf 100644
--- a/arch/mips/alchemy/common/clock.c
+++ b/arch/mips/alchemy/common/clock.c
@@ -160,7 +160,7 @@ static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name,
160 id.name = ALCHEMY_CPU_CLK; 160 id.name = ALCHEMY_CPU_CLK;
161 id.parent_names = &parent_name; 161 id.parent_names = &parent_name;
162 id.num_parents = 1; 162 id.num_parents = 1;
163 id.flags = CLK_IS_BASIC; 163 id.flags = 0;
164 id.ops = &alchemy_clkops_cpu; 164 id.ops = &alchemy_clkops_cpu;
165 h->init = &id; 165 h->init = &id;
166 166
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 46604214bba0..b06038b8f658 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -218,7 +218,7 @@ struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
218 return ERR_PTR(-ENOMEM); 218 return ERR_PTR(-ENOMEM);
219 219
220 init.name = name; 220 init.name = name;
221 init.flags = flags | CLK_IS_BASIC; 221 init.flags = flags;
222 init.parent_names = parent_names; 222 init.parent_names = parent_names;
223 init.num_parents = num_parents; 223 init.num_parents = num_parents;
224 hw = &composite->hw; 224 hw = &composite->hw;
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 46852e9cd4b1..3f9ff78c4a2a 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -491,7 +491,7 @@ static struct clk_hw *_register_divider(struct device *dev, const char *name,
491 init.ops = &clk_divider_ro_ops; 491 init.ops = &clk_divider_ro_ops;
492 else 492 else
493 init.ops = &clk_divider_ops; 493 init.ops = &clk_divider_ops;
494 init.flags = flags | CLK_IS_BASIC; 494 init.flags = flags;
495 init.parent_names = (parent_name ? &parent_name: NULL); 495 init.parent_names = (parent_name ? &parent_name: NULL);
496 init.num_parents = (parent_name ? 1 : 0); 496 init.num_parents = (parent_name ? 1 : 0);
497 497
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 241b3f8c61a9..8aac2d1b6fea 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -84,7 +84,7 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
84 84
85 init.name = name; 85 init.name = name;
86 init.ops = &clk_fixed_factor_ops; 86 init.ops = &clk_fixed_factor_ops;
87 init.flags = flags | CLK_IS_BASIC; 87 init.flags = flags;
88 init.parent_names = &parent_name; 88 init.parent_names = &parent_name;
89 init.num_parents = 1; 89 init.num_parents = 1;
90 90
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index 00ef4f5e53fe..a7e4aef7a376 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -68,7 +68,7 @@ struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
68 68
69 init.name = name; 69 init.name = name;
70 init.ops = &clk_fixed_rate_ops; 70 init.ops = &clk_fixed_rate_ops;
71 init.flags = flags | CLK_IS_BASIC; 71 init.flags = flags;
72 init.parent_names = (parent_name ? &parent_name: NULL); 72 init.parent_names = (parent_name ? &parent_name: NULL);
73 init.num_parents = (parent_name ? 1 : 0); 73 init.num_parents = (parent_name ? 1 : 0);
74 74
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index 638a9bbc2ab8..d81f1d2e9129 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -167,7 +167,7 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
167 167
168 init.name = name; 168 init.name = name;
169 init.ops = &clk_fractional_divider_ops; 169 init.ops = &clk_fractional_divider_ops;
170 init.flags = flags | CLK_IS_BASIC; 170 init.flags = flags;
171 init.parent_names = parent_name ? &parent_name : NULL; 171 init.parent_names = parent_name ? &parent_name : NULL;
172 init.num_parents = parent_name ? 1 : 0; 172 init.num_parents = parent_name ? 1 : 0;
173 173
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 0c0bb83f714e..1b99fc962745 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -158,7 +158,7 @@ struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
158 158
159 init.name = name; 159 init.name = name;
160 init.ops = &clk_gate_ops; 160 init.ops = &clk_gate_ops;
161 init.flags = flags | CLK_IS_BASIC; 161 init.flags = flags;
162 init.parent_names = parent_name ? &parent_name : NULL; 162 init.parent_names = parent_name ? &parent_name : NULL;
163 init.num_parents = parent_name ? 1 : 0; 163 init.num_parents = parent_name ? 1 : 0;
164 164
diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c
index c2f07f0d077c..9d930edd6516 100644
--- a/drivers/clk/clk-gpio.c
+++ b/drivers/clk/clk-gpio.c
@@ -137,7 +137,7 @@ static struct clk_hw *clk_register_gpio(struct device *dev, const char *name,
137 137
138 init.name = name; 138 init.name = name;
139 init.ops = clk_gpio_ops; 139 init.ops = clk_gpio_ops;
140 init.flags = flags | CLK_IS_BASIC; 140 init.flags = flags;
141 init.parent_names = parent_names; 141 init.parent_names = parent_names;
142 init.num_parents = num_parents; 142 init.num_parents = num_parents;
143 143
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 893c9b285532..66e91f740508 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -175,7 +175,7 @@ struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
175 init.ops = &clk_mux_ro_ops; 175 init.ops = &clk_mux_ro_ops;
176 else 176 else
177 init.ops = &clk_mux_ops; 177 init.ops = &clk_mux_ops;
178 init.flags = flags | CLK_IS_BASIC; 178 init.flags = flags;
179 init.parent_names = parent_names; 179 init.parent_names = parent_names;
180 init.num_parents = num_parents; 180 init.num_parents = num_parents;
181 181
diff --git a/drivers/clk/clk-pwm.c b/drivers/clk/clk-pwm.c
index 8cb9d117fdbf..02b472a1f9b0 100644
--- a/drivers/clk/clk-pwm.c
+++ b/drivers/clk/clk-pwm.c
@@ -101,7 +101,7 @@ static int clk_pwm_probe(struct platform_device *pdev)
101 101
102 init.name = clk_name; 102 init.name = clk_name;
103 init.ops = &clk_pwm_ops; 103 init.ops = &clk_pwm_ops;
104 init.flags = CLK_IS_BASIC; 104 init.flags = 0;
105 init.num_parents = 0; 105 init.num_parents = 0;
106 106
107 clk_pwm->pwm = pwm; 107 clk_pwm->pwm = pwm;
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index a72520720783..3e1708747cd2 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -2851,7 +2851,6 @@ static const struct {
2851 ENTRY(CLK_SET_PARENT_GATE), 2851 ENTRY(CLK_SET_PARENT_GATE),
2852 ENTRY(CLK_SET_RATE_PARENT), 2852 ENTRY(CLK_SET_RATE_PARENT),
2853 ENTRY(CLK_IGNORE_UNUSED), 2853 ENTRY(CLK_IGNORE_UNUSED),
2854 ENTRY(CLK_IS_BASIC),
2855 ENTRY(CLK_GET_RATE_NOCACHE), 2854 ENTRY(CLK_GET_RATE_NOCACHE),
2856 ENTRY(CLK_SET_RATE_NO_REPARENT), 2855 ENTRY(CLK_SET_RATE_NO_REPARENT),
2857 ENTRY(CLK_GET_ACCURACY_NOCACHE), 2856 ENTRY(CLK_GET_ACCURACY_NOCACHE),
diff --git a/drivers/clk/mmp/clk-gate.c b/drivers/clk/mmp/clk-gate.c
index 7355595c42e2..1755916ddef2 100644
--- a/drivers/clk/mmp/clk-gate.c
+++ b/drivers/clk/mmp/clk-gate.c
@@ -108,7 +108,7 @@ struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
108 108
109 init.name = name; 109 init.name = name;
110 init.ops = &mmp_clk_gate_ops; 110 init.ops = &mmp_clk_gate_ops;
111 init.flags = flags | CLK_IS_BASIC; 111 init.flags = flags;
112 init.parent_names = (parent_name ? &parent_name : NULL); 112 init.parent_names = (parent_name ? &parent_name : NULL);
113 init.num_parents = (parent_name ? 1 : 0); 113 init.num_parents = (parent_name ? 1 : 0);
114 114
diff --git a/drivers/clk/ti/clk-7xx-compat.c b/drivers/clk/ti/clk-7xx-compat.c
index e3cb7f0b03ae..b3cd2296f84b 100644
--- a/drivers/clk/ti/clk-7xx-compat.c
+++ b/drivers/clk/ti/clk-7xx-compat.c
@@ -362,7 +362,7 @@ static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst
362 { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" }, 362 { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
363 { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 363 { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
364 { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 364 { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
365 { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 365 { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },
366 { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, 366 { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
367 { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" }, 367 { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
368 { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" }, 368 { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
@@ -662,7 +662,7 @@ static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst
662 { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, 662 { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
663 { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, 663 { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
664 { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, 664 { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
665 { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, 665 { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div", "l4sec_clkdm" },
666 { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, 666 { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
667 { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" }, 667 { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
668 { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" }, 668 { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
@@ -704,7 +704,7 @@ static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initcons
704 { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 704 { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
705 { DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, 705 { DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
706 { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" }, 706 { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
707 { DRA7_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" }, 707 { DRA7_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
708 { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 708 { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
709 { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" }, 709 { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
710 { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" }, 710 { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 597fb4a59318..79186b918d87 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -348,7 +348,7 @@ static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst
348 { DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" }, 348 { DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
349 { DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 349 { DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
350 { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 350 { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
351 { DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 351 { DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },
352 { DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, 352 { DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
353 { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 353 { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
354 { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 354 { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
@@ -590,7 +590,7 @@ static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst
590 { DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 590 { DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
591 { DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 591 { DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
592 { DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 592 { DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
593 { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "" }, 593 { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
594 { DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 594 { DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
595 { 0 }, 595 { 0 },
596}; 596};
@@ -757,7 +757,7 @@ static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initcons
757 { DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 757 { DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
758 { DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, 758 { DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
759 { DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" }, 759 { DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
760 { DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" }, 760 { DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
761 { DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 761 { DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
762 { DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" }, 762 { DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" },
763 { DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" }, 763 { DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" },
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
index 639f515e08f0..96d65a1cf7be 100644
--- a/drivers/clk/ti/clkctrl.c
+++ b/drivers/clk/ti/clkctrl.c
@@ -446,6 +446,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
446 u32 addr; 446 u32 addr;
447 int ret; 447 int ret;
448 char *c; 448 char *c;
449 u16 soc_mask = 0;
449 450
450 if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) && 451 if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) &&
451 of_node_name_eq(node, "clk")) 452 of_node_name_eq(node, "clk"))
@@ -469,6 +470,13 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
469 else 470 else
470 data = dra7_clkctrl_data; 471 data = dra7_clkctrl_data;
471 } 472 }
473
474 if (of_machine_is_compatible("ti,dra72"))
475 soc_mask = CLKF_SOC_DRA72;
476 if (of_machine_is_compatible("ti,dra74"))
477 soc_mask = CLKF_SOC_DRA74;
478 if (of_machine_is_compatible("ti,dra76"))
479 soc_mask = CLKF_SOC_DRA76;
472#endif 480#endif
473#ifdef CONFIG_SOC_AM33XX 481#ifdef CONFIG_SOC_AM33XX
474 if (of_machine_is_compatible("ti,am33xx")) { 482 if (of_machine_is_compatible("ti,am33xx")) {
@@ -501,6 +509,9 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
501 data = dm816_clkctrl_data; 509 data = dm816_clkctrl_data;
502#endif 510#endif
503 511
512 if (ti_clk_get_features()->flags & TI_CLK_DEVICE_TYPE_GP)
513 soc_mask |= CLKF_SOC_NONSEC;
514
504 while (data->addr) { 515 while (data->addr) {
505 if (addr == data->addr) 516 if (addr == data->addr)
506 break; 517 break;
@@ -562,6 +573,12 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
562 reg_data = data->regs; 573 reg_data = data->regs;
563 574
564 while (reg_data->parent) { 575 while (reg_data->parent) {
576 if ((reg_data->flags & CLKF_SOC_MASK) &&
577 (reg_data->flags & soc_mask) == 0) {
578 reg_data++;
579 continue;
580 }
581
565 hw = kzalloc(sizeof(*hw), GFP_KERNEL); 582 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
566 if (!hw) 583 if (!hw)
567 return; 584 return;
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 1c0fac59d809..e4b8392ff63c 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -83,6 +83,13 @@ enum {
83#define CLKF_HW_SUP BIT(6) 83#define CLKF_HW_SUP BIT(6)
84#define CLKF_NO_IDLEST BIT(7) 84#define CLKF_NO_IDLEST BIT(7)
85 85
86#define CLKF_SOC_MASK GENMASK(11, 8)
87
88#define CLKF_SOC_NONSEC BIT(8)
89#define CLKF_SOC_DRA72 BIT(9)
90#define CLKF_SOC_DRA74 BIT(10)
91#define CLKF_SOC_DRA76 BIT(11)
92
86#define CLK(dev, con, ck) \ 93#define CLK(dev, con, ck) \
87 { \ 94 { \
88 .lk = { \ 95 .lk = { \
@@ -303,7 +310,6 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
303int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, 310int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
304 struct clk_rate_request *req); 311 struct clk_rate_request *req);
305int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw)); 312int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw));
306bool omap2_clk_is_hw_omap(struct clk_hw *hw);
307 313
308extern struct ti_clk_ll_ops *ti_clk_ll_ops; 314extern struct ti_clk_ll_ops *ti_clk_ll_ops;
309 315
diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index c1ed641b3e26..4ae5d774443e 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -470,7 +470,7 @@ static int meson_pwm_init_channels(struct meson_pwm *meson,
470 470
471 init.name = name; 471 init.name = name;
472 init.ops = &clk_mux_ops; 472 init.ops = &clk_mux_ops;
473 init.flags = CLK_IS_BASIC; 473 init.flags = 0;
474 init.parent_names = meson->data->parent_names; 474 init.parent_names = meson->data->parent_names;
475 init.num_parents = meson->data->num_parents; 475 init.num_parents = meson->data->num_parents;
476 476
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 46d5fc3057b5..8fa494aaa34d 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -24,7 +24,7 @@
24#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 24#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
25#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 25#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
26 /* unused */ 26 /* unused */
27#define CLK_IS_BASIC BIT(5) /* deprecated, don't use */ 27 /* unused */
28#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 28#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
29#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 29#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
30#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 30#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 78872efc7be0..1e8ef96555ce 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -243,6 +243,7 @@ struct ti_clk_ll_ops {
243 243
244#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) 244#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
245 245
246bool omap2_clk_is_hw_omap(struct clk_hw *hw);
246int omap2_clk_disable_autoidle_all(void); 247int omap2_clk_disable_autoidle_all(void);
247int omap2_clk_enable_autoidle_all(void); 248int omap2_clk_enable_autoidle_all(void);
248int omap2_clk_allow_idle(struct clk *clk); 249int omap2_clk_allow_idle(struct clk *clk);
@@ -293,6 +294,7 @@ struct ti_clk_features {
293#define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2) 294#define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2)
294#define TI_CLK_ERRATA_I810 BIT(3) 295#define TI_CLK_ERRATA_I810 BIT(3)
295#define TI_CLK_CLKCTRL_COMPAT BIT(4) 296#define TI_CLK_CLKCTRL_COMPAT BIT(4)
297#define TI_CLK_DEVICE_TYPE_GP BIT(5)
296 298
297void ti_clk_setup_features(struct ti_clk_features *features); 299void ti_clk_setup_features(struct ti_clk_features *features);
298const struct ti_clk_features *ti_clk_get_features(void); 300const struct ti_clk_features *ti_clk_get_features(void);
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-26 10:58:10 -0400